E0-286 “VLSI Test” - Indian Institute of Science
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1 E0-286 “VLSI Test” 1. Scan design requirements, types of scan. Scan design optimizations, managing scan for IPs and SOCs.
Transcript of E0-286 “VLSI Test” - Indian Institute of Science
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E0-286 “VLSI Test”
1. Scan design requirements, types of scan.Scan design optimizations, managing scan forIPs and SOCs.
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Recap till now…
q Design for test overview
q Test requirements and economics
q Fault models
q Test for combinational and sequential circuits
q Algorithmic / CAD approaches for test
q This lecture is on scan design and test techniques for sequential circuits
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Optimizing sequential circuit test
q Testing an example sequential circuit:
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Optimizing sequential circuit test
q Time-frame expansion: Constraints on f0 and f1 across time-frames…
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Benefits of scan-based test
q Sequential test generation reduces to combinational test generation
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Scan Test
q Scanning the example sequential circuit
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Scan Test
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1. Shift-in in the pattern- aka load / scan-in
2. Exercise the functionality- aka capture
3. Shift-out the response- aka unload/scan-out
shift_in shift_out
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… …CLK
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Scan Pattern
q A Scan pattern consists of ¦ Scan-in / shift-in / load
? Initialize all flip-flops to known state? Takes N cycles, with N flip-flops in ‘M’ scan chains§ N*(M-1) < Total number of flip-flops <= N*M
¦ Scan capture? Exercise the functionality of the design, captures the ‘D’ (i.e. functional)
input of the flip-flop? 1 or more cycles => capture-depth
¦ Scan-out / shift-out / unload? Observe the captured response by shifting out all flip-flops
q For example, P1: {<111111XXXX>, C, <XX00001110>}
q Shifting in of a new pattern may happen in parallel with shifting out of previous pattern’s response.
q Scan test time is usually limited by the shift-in time, i.e. length of the longest scan chain
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Scan insertion
q Scan replacement¦ Converting the existing (non-scan) design into a scan
design
q Scan stitching¦ Stitching the scan flip-flops to form scan chain(s)
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Scan Implementation
Exclusive Scan pathFunctional path
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From other FF(Q)
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To other FF(D)
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Cycles 1 2 3 4 5 6 7SI1SI2SE
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Other types of scan elements
q LSSD (Level-sensitive-scan-design)D
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D flip-flop
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LSSDSCKSD
TCK
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Design requirements for scan
q Flip-Flop type requirements¦ Restrictions in mixing different flop styles¦ Restrictions in mixing different edge flops
? Posedge followed by negedge: lockup latch to avoid loss of data
q Pin requirements¦ Additional pins for scan in, scan out and scan enable
q Clocking requirements¦ Controllability of clocks from PI
q Reset requirements¦ Controllability of resets from PI
q Data-clock exclusion¦ Clock feeding as data in a register is not allowed
FF FFLA
FF FF
FF FF
TEST_MODE
RST_N
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Limitations of scan
q Test power overhead of scan¦ Higher shift power due to shifting in all flip-flops in the
design (which may not be functional scenario)¦ Higher capture power due to optimized ATPG (that
generates least patterns) with all flip-flops controllable
q Area overhead with scan, due to additional multiplexers and additional wire routes for scan chain
q Test time overhead of scan, due to shifting in all flip-flops in the design for one pattern
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Variants of scan
q Partial scan¦ Non-scan: No flip-flops are scannable¦ Full-scan: All flip-flops are part of scan chain(s)¦ Partial scan: A subset of flip-flops are scannable
? Capture depth > 1, in order to initialize non-scan flip-flops
q Hold-scan architecture¦ Additional hold latch at the output of scan flip-flop to hold the
output during scan shift¦ Additional area overhead, but helps in delay test and shift power
q Random-access scan¦ Scan flip-flops addressed as RAM, instead of shift register¦ Advantages: Update only those flip-flops necessary for test¦ Disadvantages: Area (gate area and routing) overhead
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Test points
q Test points: additional signals inserted into the design to improve controllability and/or observability
q Need for test points even in full-scan design¦ Hard to control / observe logic¦ Interface with non-scan logic/IPs¦ Multi-cycle paths
q Control point¦ 0(1)-control point: Ability to inject 0(1) by enabling a signal
¦ Generic control points? Example: controlling clocks and resets for scan design rule compliance
TEST TEST
0-control point 1-control point
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Test points with scan
q Observe point¦ An added output to observe the status of internal logic for test¦ Example: Digital logic driving analog IP boundary need to be
observed with digital test.
q Role of scan¦ Each test point may be assigned a scan flip-flop
? These are pure-DFT logic that is present in the scan chain to improve testability
¦ Group of test points may be assigned a scan flip-flop? Example: all specific control points may have one scan flip-flop to
enable them? Multiple observe points may be grouped to reduced flip-flops with
reduction logic (such as XOR) or muxes.§ Role of aliasing with reduction logic would be discussed in detail during section on BIST.
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SOC test economics
q Test economics with scan¦ Consider a SOC with 8 cores, each core has 1000 flip-flops and
SOC interface logic has 200 flip-flops§ Total flip-flops in SOC = 8200
? Let core 2 be the most complex core with 1000 test patterns? All other cores and SOC interface logic require 100 patterns
¦ If all flip-flops in SOC are always stitched together, Total test time = 8200*1000 ~ 8.2M !!
q Divide-and-conquer strategy helps reduce test time¦ Test each core separately
? Core test time = 7*1000*100 + 1000*1000 ~ 1.7M¦ Test SOC with all cores separately
? SOC test time = 8200*100 ~ 0.82M¦ Total test time ~ 2.5M
q Similar reductions are also applicable for test power
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Scan architecture for SOCs
q IP-internal logic test¦ Each IP to have scan chains to test the IP from SOC¦ SOC to provide standard access to IP scan chains
q SOC logic test (IP external test aka glue logic test)¦ Targets testing SOC logic that interfaces multiple IPs¦ Need scan chains of all (or interacting IPs) for test
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Further optimizing SOC test time
q SOC interface logic test is limiting for test time and test power
q All flip-flops of SOC interface logic are necessary
q All flip-flops within the core that interact with external world/SOC interface are necessary¦ All other flip-flops within the core that do not interact with external
world may be excluded from scan, to reduce test time? May be constrained to remain constant to also reduce test power
q Core scan architecture¦ A mode in which all core flip-flops are in scan chain¦ A mode in which only those core flip-flops that interact with
external world are in scan chain
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Class 0-3 flopsCore-internal flops
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SOC test with IP wrappers
q Cores with standard wrappers¦ Reduce test time as entire core can now be excluded and only
wrapper flops are part of SOC interface test¦ Also reduces test power as entire core can be clock-gated off
q Modes of test¦ Intest: Testing core-internal logic
? Only core-internal and core-wrapper flip-flops in scan chain¦ Extest: Testing core-external logic
? Only core-wrapper and SOC interface flip-flops in scan chain? Core-internal flip-flops are excluded from scan chain
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SOC test without IP wrappers
q Identify “natural” bounding/isolation flip-flops in the interface of each core
q Modes of test¦ Intest: Testing core-internal logic
? Only core-internal flip-flops in scan chain¦ Extest: Testing core-external logic
? Core-bounding and SOC interface flip-flops in scan chain
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Design aspects:
q Types of scan flip-flops.
q Inputs / Outputs and controls required.
q Number of scan chains and lengths.
q Order of stitching flip-flops into scan chains.
q Stitching across IPs / Domains.
q Full scan versus partial scan.
Scan: Changes state setting complexity from exponential to linear.
q Ease of controllability. Ease of observability.
q No need for scan shift simulations after scan integrity checks.
q At-speed next state generation possible without tester inputs.
Recap: Various Aspects of Scan
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Functional and Structural Tests
q Ubiquitous need for non-functional inputs:¦ Examples: Memory back-to-back reads / writes, structural redundancy in
synthesised logic (non-minimal set of minterms), functional redundancy in 3-1 mux, counter with unused states, etc.
¦ Iddq: Non-functional inputs are also required for transistor defects, e.g. 00 input to two-input NAND gate.
q Scan state itself is not functional:¦ Next state after scan shift is not necessarily functional. It is just reachable.¦ Launch-off capture and launch-off shift patterns can both have non-
functional launch states.¦ Path delay pattern: Just a valid transition, not necessarily a valid path.
q Memory RAM sequential patterns have several scan operations per pattern (five below):¦ Scan Address2 => Write Data2 (initialize).¦ Scan Address1 => Write Data1.¦ Scan Address2 => Read Data2. (Detects faults where A1 maps incorrectly
to A2).23
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Waveforms for Different Patterns
shift_in shift_outcapture
shift_in shift_out
shift_in shift_outMultiple captures
no capture
Combinational ATPG / SAF pattern.
Iddq, TGF pattern.
Sequential ATPG / TRF pattern.
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Assignments
q Convert a modulo-10 ripple counter to a scannable design, satisfying all the presented scan design rules.
q For a design with 100 pos-edge and 4 neg-edge flip-flops, how would you architect scan chains for least test time, and no impact to quality, with 8 scan chains? You may consider only stuck-at tests.
q For a design with sequential feedback (eg. CRC32), what are the candidate flops that need to be scanned, in a partial scan design, so that capture depth <= 2? What happens when capture depth <= 3?
q Compute the gate area overhead for a design with scan. Assume a design with T transistors (which include F flip-flops). Let flop = 10 transistors, mux = 4 transistors).
q Quantify the average dynamic test power reductions in SOC with Divide-and-conquer scan architecture (Pick the same example as in test time calculation. Assume FF power is same as FF count and combinational logic power is 2X FF count).
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