E-Voting Machine - Design Presentation

• Group M1• Bohyun Jessica Kim• Jonathan Chiang• Chi Ho Yoon• Donald Cober

Monday Oct 20th

Gate level SchematicsCommsBlock Update and SchematicsSRAM cell schematic and layoutUpdated Transistor Count

Secure Electronic Voting Terminal

• Updated Transistor Counts• Structural Verilog Entire System• Gate-level Schematics (Comms + SRAM)• Simulation of Individual Blocks and Whole System• Gate-level Layout• Refining Floorplan

Status Update

Immediate Issues

• Issue with Analog Simulation

Data B

us

Machine Init FSM

User ID FSM

Selection FSM

ConfirmationFSM

Display

User ID SRAM

Message ROM

Card Reader

Fingerprint Scanner

Encryption Key SRAM

User Input

Write-in SRAM

Choice SRAM

TX_Check

Selection Counter

Key Register

XOR

8 bit Full Adder

8 bit Full Adder

8 bit Full Adder

8 bit Full Adder

XOR

8 bit MUX0 1

8 bit MUX0 1

8 bit MUX0 1

8 bit Add/Sub

0 18 bit MUX

T: 128

8-bitREG

T: 88

8-bitREG

COMMS Register

Shift Register In

Shift Register Out

constant init

SRAMResized Schematics

Redone Layout32 bit by 8 bit Array Layout

Next time: Simulation

SRAM Single Cell Resized Schematic

SRAM Single Cell Layout

Last Time Updated Layout (4.095 X 2.97)

SRAM 32 by 8 Bit Cell Layout

Dimensions:131.76 by 18.72

Dimensions:131.76 by 18.72

SRAM cont’d (decoder)

Full Adder 1bit

COMMSRedesigned Implementation Walkthrough

Full schematics and gate level blocksBasic adder and xor layouts

Next time: Simulation

COMMS BLOCK Hardware Implementation 1States inA[7:0] inB[7:0] sel_out sel_shift[1:0] sel_sum v_out[7:0] (1) delta sum[7:0] 0 00 0 v_out0 = sum[7:0] (2) v1 sum[7:0] 0 01 1 v_out1= (C+D) (3) v1 << 4 k0 1 10 0 v_out2= (A+B) ^ (C+D) (4) v1 >> 5 k1 1 11 0 v_out3 = (A+B) ^ (C+D) ^ (E+F) (5) v0 out3 0 1 1 v_outx = V0 + (A+B) ^ (C+D) ^ (E+F)

States (6)-(9) same as above except using k2, k3, and flip v1, v0

Implementation goes through 9 states/clk cycles each iteration to update output function v_outx.

Reusing of:(1x) 8 bit Full adder/sub (Ripple carry) [16*8 = 128](2x) 2:1 8 bit MUX for output pass-through [4*8*2 = 64](8x) 2-input XORS [6*8 = 48](1x) 8 bit REG [11*8 = 88](1x) 4:1 8 bit MUX for shifting selection [12*8 = 96]

In addition, logic will to iterate 8 times and be controlled via FSM machine that uses:(2x) 3:1 8 bit MUX for state input selection [8*8*2 = 128](2x) 1 bit Counter adder for updating cycle [16*2 = 32](2x) 1 bit REG for storing updated cycle [11*2 = 22]Total: 606

Advantages:Saves transistors and area for Comms Block

Disadvantages:Very heavy pass-logic from MUX layers and XORHigh clk frequency required since reusing same components for calculating outx by stages. This translates to higher power consumption since we are trying to do more with less hardware.

Tradeoff:Every 8-bit MUX uses 4*8 = 32 transistors compared to 8-bit Full Adder 16*8 = 128 transistors. However MUXES have high pass-logic so area vs. power tradeoff is concerned here.

sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3);

sel_out

3:1 8 bit MUX

1-bitREGclk

1 bit Full Adder

8 bit Full Adder/Sub 8 bit MUX

8-bitREG

8’h00

inA[7:0] inB[7:0]

sel_sum

0 1

clk

T: 128

T: 48

T: 88

v_outx

4:1 8 bit MUX

00 01 10 11

sel_shift[1:0]

T: 64

8 bit MUX0 1

T: 32

T: 32

inA[7:0] sel_shift[1:0] delta 00 v1 01 v1 << 4 10 v1 >> 5 11

3:1 8 bit MUX

Logical Shifter Code

XOR

COMMS BLOCK Hardware Implementation 2

Implementation 2 does concurrent calculations for all 3 parts of function, completes full iteration of calculations in 2 clk cycles.

Uses:(1x) 8 bit Full adder/sub (Ripple carry) [16*8 = 128](3x) 8 bit Full adder (Ripple carry) [12*8*4 = 384] (4x) 2:1 8 bit MUX for output pass-through [4*8*4 = 128](16x) 2-input XORS [6*16 = 96](2x) 8 bit REG [11*8*2 = 176](1x) 1 bit Counter adder for updating cycle [16](1x) 1 bit REG for storing updated cycle [11]Total: 939

In addition, logic will not need complex FSM, just needs to do 8 iterations using 16 cycles.

Advantages:Low pass logic, speed performance, low power, MUX logic transistor count essentially halved.

Disadvantages:More Transistor Count and larger area.

Tradeoff:Larger area but low pass logic from reduced MUX and complex FSM simplifies design, increases speed and minimizes power.

sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3);

XOR

clk

T: 128

T: 88

v_outx

8 bit Full Adder

K0V1

sum

K1

T: 128 T: 128

8 bit Full Adder

8 bit Full Adder

8 bit Full Adder

V0

T: 128

XOR

sel_out

8 bit MUX0 1

T: 32

8 bit MUX0 1

8 bit MUX0 1

T: 32 T: 32

{V1[3:0], 4’b0}

{5’b0, V1[7:5]}

V1 V1

16 bit Add/Sub

delta

sel_out output 0 pass sum, V1 1 pass new sum, V0

0 116 bit MUX

T: 128

16-bitREG

clk

T: 88

8-bitREG

1-bitREGclk

1 bit Full Adder

COMMS BLOCK Hardware Implementation 3

K3K2K1K0

V0_in V1_in

V0_out V1_out

FFC

V0_inV1_in

Components

FF 8 bit (2)

FF 16 bit (1)

XOR 8 bit (4)

Inv (1)

FA 8bit (4)

FA 16 bit (1)

FA shift 4/5 bit (4)

8 bit muxes (4)

1 cycle for calculating: sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3);

Advantages:Lowest pass logic, speed performance, low power, MUX logic transistor count halved.

Disadvantages:Double Transistor Count and larger area.

Tradeoff:Larger area but low pass logic from reduced MUX, no FSM simplifies design, and 1 cycle per computation increases speed and minimizes power by factor of 2.

COMMS Full Schematic Components

FF 8 bit (2)

FF 16 bit (1)

XOR 8 bit (4)

Inv (1)

FA 8bit (4)

FA 16 bit (1)

FA shift 4/5 bit (4)

8 bit muxes (4)

Advantages:Low pass logic, speed performance, low power, MUX logic transistor count essentially halved.

Disadvantages:More Transistor Count and larger area.

Tradeoff:Larger area but low pass logic from reduced MUX and complex FSM simplifies design, increases speed and minimizes power.

COMMS cont’d (smaller blocks)

Full Adder 1bit Full Adder 8bit

COMMS cont’d (smaller blocks)

Full Adder 16 bit FF 8 bit

COMMS cont’d (smaller blocks)

Full Adder << 4 bits Full Adder >> 5 bits

COMMS cont’d (smaller blocks)

FF 16 bit XOR 8 bit

COMMS cont’d (smaller blocks)

FF 16 bit XOR 8 bit

COMMS cont’d (smaller blocks)XOR 1 bit

Full adder 1-bit layout

XOR 1-bit layout

Comms Block Structural Verilog

Comms Block Structural Verilog

Comms Block Structural Verilog

Behavioral Simulation

Structural Simulation0 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=xxxx, a1_in=xxxx, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 3 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxxx, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 7 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxxX, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 8 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxx0, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 9 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=XX00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 10 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=XX00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 11 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 80 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=0, clk=1 160 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=0, clk=0 163 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=0a00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 167 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=0000, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 168 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 178 V0_out=xx, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 179 V0_out=xX, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 180 V0_out=xX, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 181 V0_out=xX, V1_out=x8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 182 V0_out=XX, V1_out=X8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 183 V0_out=XX, V1_out=X8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 184 V0_out=X0, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 186 V0_out=X0, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 189 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 240 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=1 243 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=18, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=1 320 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=18, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 323 V0_out=20, V1_out=18, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 329 V0_out=20, V1_out=18, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 339 V0_out=20, V1_out=48, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 340 V0_out=20, V1_out=68, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 341 V0_out=20, V1_out=e9, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 342 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 400 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=1 403 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=eb, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 410 V0_out=20, V1_out=4a, V0_reg=20, V1_reg=eb, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

560 V0_out=de, V1_out=c5, V0_reg=7f, V1_reg=eb, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 563 V0_out=de, V1_out=c5, V0_reg=7f, V1_reg=c5, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 571 V0_out=de, V1_out=d5, V0_reg=7f, V1_reg=c5, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

720 V0_out=9f, V1_out=6e, V0_reg=0f, V1_reg=c5, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 723 V0_out=9f, V1_out=6e, V0_reg=0f, V1_reg=6e, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 730 V0_out=9f, V1_out=06, V0_reg=0f, V1_reg=6e, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

Structural Simulation 880 V0_out=7b, V1_out=73, V0_reg=c5, V1_reg=6e, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

883 V0_out=7b, V1_out=73, V0_reg=c5, V1_reg=73, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 890 V0_out=7b, V1_out=70, V0_reg=c5, V1_reg=73, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

1040 V0_out=7b, V1_out=2a, V0_reg=20, V1_reg=73, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1043 V0_out=7b, V1_out=2a, V0_reg=20, V1_reg=2a, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1050 V0_out=7b, V1_out=08, V0_reg=20, V1_reg=2a, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

1200 V0_out=80, V1_out=6a, V0_reg=d0, V1_reg=2a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1203 V0_out=80, V1_out=6a, V0_reg=d0, V1_reg=6a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1210 V0_out=80, V1_out=2a, V0_reg=d0, V1_reg=6a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

1360 V0_out=b4, V1_out=9c, V0_reg=c2, V1_reg=6a, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1363 V0_out=b4, V1_out=9c, V0_reg=c2, V1_reg=9c, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1370 V0_out=b4, V1_out=8c, V0_reg=c2, V1_reg=9c, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

1520 V0_out=38, V1_out=58, V0_reg=fd, V1_reg=9c, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1523 V0_out=38, V1_out=58, V0_reg=fd, V1_reg=58, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1530 V0_out=38, V1_out=50, V0_reg=fd, V1_reg=58, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

Structural simulation terminates after 8 iterations, bolded in red, at 0xfd58 like behavioral. Decryption works in the reverse fashion with adders doing subtraction instead.

FSMMachine Initialization FSM Schematics

Next time: Remaining FSM Schematics

Simulation

Machine Initialization FSM Schematic #1

Machine Initialization FSM Schematic #2

Changes during structural

● FSM Encoding:

– FSMs with 6, 12, 7 and 9 states– Binary encoding has about the same transistor count as

One-hot encoding– One-hot is much easier to layout

• Address Counter– SRAM data is accessed sequentially– Address registers are linked as counters– Counters can increment, decrement, and reset– Requires an additional type of register

Total counts 1826

FF 8 bit (2) 10*8*2 = 160

FF 16 bit (1) 160*1 = 160

XOR 8 bit (4) 6*8*4 = 192

Inv (1) 2

FA 8bit (4) 16*8*4 = 512

FA 16 bit (1) 256*1 = 256

FA shift 4/5 bit (4) 128*4 = 512

8 bit muxes (4) 4*8*4 = 32

COMMS Optimized Gate Schematics Transistor Counts

FSM Verilog Transistor Counts

Block States Address Registers Distinct Outputs

Random Transistors

Machine Init FSM 6 2 bits 5 5 50 105

User ID FSM 12 3 bits 7 13 130 207

Selection FSM 7 2 bits 5 9 90 145

Confirmation FSM 9 6 bits 10 8 80 170

FSM Optimized Gate Schematics Transistor Counts

Block State Register T Address Counter T Random Total

Machine Init FSM 54 46 38 138

User ID FSM 108 70 102 280

Selection FSM 63 46 68 177

Confirmation FSM 81 92 62 235

SRAM & Peripheral Blocks Transistor Counts

Block Old Total

Message ROM 280 80

Selection Counter 33 58

TX_Check 33 86

User Input 244 422

COMMs 1826 2363

Block Old Total

Key SRAM 228 228

Write-in SRAM 3 596 3 596

User ID SRAM 454 454

Choice SRAM 228 228

TOTAL 8345

Updated Floorplan

● The aspect ratio still about 2:1

● Doubled size in COMMS Block

● The interconnects travel heavily over the FSM

● These are mostly 1 bit enable signals and some are address lines

● The address lines and data bus are buffered

Issues

Simulation Results All Individual Functional BlocksFSM Gate-level Schematics and Layout UpdateGlobal Schematic Routing

Next Time

Persisting problem with Analog Simulation using SCMOS18 library

Questions?

Thank you!