DVB/ATSC Cable Transmitters and...

DVB/ATSC Cable Transmitters and ReceiversXilinx Solutions for Digital Transceivers in the Cable Headend

DVB/ATSC Cable Systems 2

The Cable Network

ReceiversReceivers

MPEGEncodersMPEG

Encoders

Remultiplexers(StatMuxes)

Remultiplexers(StatMuxes)

Modulators/TransmittersModulators/Transmitters

CMTS

Router

CMTS

Router

VideoServers

Web &ApplicationServers

Back

plan

e(e.g

. Fib

re C

hann

el)Ba

ckpl

ane(

e.g. F

ibre

Cha

nnel)

Cable ModemCable

Modem

Set TopBox

Set TopBox

Cable Headend Customer Premise

Internet

TV Broadcast


Introduction to DVB• Digital Video Broadcasting organisation• Formed in September 1993• DVB now has more than 300 members

– Broadcasters– Manufacturers– Network operators– Regulatory bodies

• Mission : “The creation of a harmonious digital broadcast market for all service delivery media”

• Mainly covers Europe but also promoting in U.S. and Japan• Competes against ATSC (U.S.) and ISDB (Japan)


Introduction to ATSC• Advanced Television Systems Committee• Formed in September 1982• ATSC currently has around 200 members

– Broadcasters– Manufacturers– Network operators– Regulatory bodies

• Co-ordinates television standards among different communications media focusing on digital television, interactive systems, and broadband multimedia communications. Also developing digital television implementation strategies

• Adopted by U.S., Canada, S. Korea, Taiwan and Argentina


Worldwide Digital TV AdoptionTotal worldwide digital TV market to exceed 420 million sets by 2007

Source : Ovum Consultancy Ltd


Issues & Requirements

• Higher throughput– Particularly in cable networks, higher video/data

bandwidth required• Lower cost-per-channel

– Support for multiple channels in less chips• Fast time-to-market

– Need to recoup huge infrastructure investments as soon as possible


DVB/ATSC Cable Features

• High bitrate, stationary receivers• High bitrate interactivity• Interactivity mostly using cable modem• 8MHz cable channel with DVB-C gives approx

38-40MBits/s• 6MHz cable channel with ATSC gives

38.57MBits/s


DVB-C Transmitter

Multiplexed MPEG Transport Stream Mux

Adaptation, Energy

Dispersal

Mux Adaptation,

Energy Dispersal

Reed-Solomon

Coder

Reed-Solomon

CoderConvolution Interleaver

Convolution Interleaver

Byte tom-tuple

Conversion

Byte tom-tuple

Conversion

Differential Encoding

Differential Encoding Baseband

Shaping

BasebandShaping ModulationModulation RF

Conversion

RF Conversion

RF Cable Channel

Xilinx Memory CPU Non-Xilinx Mixed Signal Embedded Logic


DVB-C Receiver

SYNC Inversion &

Energy Dispersal Removal

SYNC Inversion &

Energy Dispersal Removal

Reed-Solomon Decoder

Reed-Solomon Decoder

Convolution Deinterleaver

Convolution Deinterleaver

Symbol to Byte

Mapping

Symbol to Byte

Mapping

Differential Decoding

Differential Decoding

Matched Filter &

Equalizer

Matched Filter &

EqualizerDemodulationDemodulationRF Conversion

RF Conversion

Multiplexed MPEG Transport Stream

RF Cable Channel



ATSC Cable Transmitter

MuxMuxSegment Sync

Field Sync

MPEG Transport Stream

RF Cable Channel

DataRandomizer

DataRandomizer

Reed-Solomon Encoding


Data Interleaver

Data Interleaver MapperMapper

PilotInsertion

PilotInsertion VSB

Modulator

VSBModulator

RFUp-

converter

RFUp-

converter



ATSC Cable Receiver

DemuxDemux

DataDerandomizer

DataDerandomizer

Reed-Solomon Decoding

Reed-Solomon Decoding

Data Deinterleaver

Data DeinterleaverUnmapperUnmapper

PilotRemoval

PilotRemovalVSB

Demodulator

VSBDemodulator

RFDown-

converter

RFDown-

converter

Segment Sync

Field SyncRF Cable Channel

MPEG Transport Stream



Xilinx Reed-Solomon Encoder

• Parameterizable encoder and decoder cores available from Xilinx

• Simply select DVB or ATSC from the Code Specificationmenu

• Reed-Solomon tutorials online at Xilinx IP Centre http://www.xilinx.com/ipcenter

• Incorporates Smart-IP


Xilinx R-S Features

Enco

der

Deco

der


Xilinx Interleaver/Deinterleaver• Forney convolutional type

architecture • Parameterizable number of

branches and branch lengths • Symbol size from 1 to 256 bits • Incorporates Smart-IP• More info at

http://www.xilinx.com/ipcenter


Xilinx (De)Interleaver Features


Smart-IP Technology

• Used in all Xilinx cores• Results in predictable

implementation– Consistent functionality and

performance– Independent of core placement,

number of cores used, surrounding user logic, device size and choice of EDA tool

• Vital for easy design of multi-channel systems


Forward Error Correction IPFECReed Solomon Encoder AmphionReed Solomon Decoder AmphionReed Solomon Encoder XilinxReed Solomon Decoder XilinxViterbi Decoder XilinxViterbi 802.11 Decoder XilinxInterleaver/Deinterleaver XilinxTurbo Convolutional Codec XilinxDVB-RCS Turbo Decoder iCodingReed Solomon Encoder MemecReed Solomon Decoder MemecDVB Satellite Demodulator MemecConvolutional Encoder TILABReed Solomon Decoder TILABInterleaver/Deinterleaver TILABTurbo Decoder TILAB

Video and Image Processing IP Vendor Sign Once

www.xilinx.com/ipcenterwww.xilinx.com/ipcenter


RRC Filters in Xilinx Devices• Before transmission, signals are shaped using a filter such

as the Root Raised Cosine (RRC) filter• RRC coefficients determined using DSP tools (e.g. Matlab)

– Designer enters required roll-off and bit rate parameters into RRC generator to produce coefficients

– Suggests number of taps and shows resulting waveforms for trial and error iterations

• Final RRC coefficients simply entered into Xilinx Core Generator to build necessary FIR filter in hardware


Performance Limitation of Conventional DSP

Conventional DSP Device • Fixed inflexible architecture– Typically 1-4 MAC units– Fixed data width

• Serial processing limits data throughput– Time-shared MAC unit– High clock frequency creates

difficult system-challenge

(Von Neumann architecture, or extensions thereof)

Loop Algorithm256 times

Example256 Tap FIR Filter = 256 multiply and accumulate (MAC) operations per data sample

Data Out

RegData In

MAC unit

FPGA Performance Advantage

• Flexible architecture– Distributed DSP resources (LUT,

registers, multipliers, & memory)• Parallel processing maximizes

data throughput– Support any level of parallelism– Optimal performance/cost tradeoff

All 256 MAC operations in 1 clock cycle

FPGA

....C0

Data Out

C1 C2 C255

Reg0 Reg1 Reg2 Reg255Data In

Example256 Tap FIR Filter = 256 multiply and accumulate (MAC) operations per data sample



Traditional Processing

Control Tasks

Control Tasks

FIR Filter

C++ Code Stack

Control Tasks

FIR Filter

CPU

Math-intensive algorithms dominate the processing capacity

CPU RAMRAM

FIR Filter FIR Filter

Processing timeTraditional


Xtreme Processing™

Control Tasks

Control Tasks

FIR Filter

C++ Code Stack

Control Tasks

FIR Filter

FIR Filter FIR Filter


PowerPCProcessor

PowerPCProcessor

XTREMEProcessing™

FIR Engine (fabric/multipliers)

OCMRAMOCMRAM

3

+

2

+

0 1

+

n

+

PowerPC with Application-SpecificHardware Acceleration

The Virtex-II Pro Advantage


Xtreme Forward-Error Correction

Control Tasks

Control Tasks

Code Stack (C++)

Control Tasks

Interleaver

Reed-Solomon

ViterbiPowerPCProcessor

PowerPCProcessor

OCMRAMOCMRAM

FEC Engine(fabric/multipliers)

PowerPC with Application-SpecificHardware Acceleration

Viterbi Inter-leaver

Reed-Solomon

Viterbi Reed-Solomon


XTREMEProcessing™

The Virtex-II Pro Advantage

Interleave


Multiple Channels on the Platform FPGA

• Users should think 3D rather than 2D when designing– Reuse resources by multiplexing if extra horsepower available

Columns ColumnsRowsCy

cles p

er O

pera

tion

Rows

Single Channel16

k0 k1 k2 k3

40

16 Channels in 1

k0 k1 k2 k3

16

40

Chan 1Chan 2Chan 3Chan 4Chan 5Chan 6Chan 7Chan 8Chan 9Chan 10Chan 11Chan 12Chan 13Chan 14Chan 15Chan 16


16x16x16x

16 Channels in 1 using SRL16E

k0 k1 k2 k3

16

40


Chan [16:1]

SRL16EDistributed RAM Mode

Sync Inversion & Randomise

Sync Inversion & Randomise



Convolution Interleaver

Convolution Interleaver M-Tuple

Conversion

M-Tuple Conversion

Differential Encoding &

Mapping

Differential Encoding &

MappingSinx/x Filter

Sinx/x Filter

NCOFmod

NCOFmod

Nyquist Filter

Nyquist Filter

Nyquist Filter

Nyquist Filter

The XDS Advantage Customer's Original Design XDS SolutionDevice Required Virtex XCV2600E-6BG1156 Virtex XCV400E-6BG676Cost* $12X $X

XDS Case StudyDataOut

DataIn

• Xilinx Design Services (XDS) solution delivered >90% savings on device price over original design!

– Relatively slow speed of four paths through FPGA allowed multiplexing • Use of Xilinx FPGA enabled customer to prototype their product within 4 months• Customer able to recover one-time development cost before prototype completion• Engaging XDS enabled customer to develop successful product with viable cost

Single channel of 4-channel wireless uplink transcoder


structure and faster time-to-market*(100+ pricing for comparative purposes only)


Multiple Channels on V-II Pro• Over 100 encoder channels

on one Virtex-II Pro FPGA– Reed-Solomon, Interleaver,

Convolutional Encoder• Up to 24 Serial Transceivers!

– 622 Mbps to 3.125 Gbps– Network connectivity

• Plus up to four IBM 405 PowerPCs!!– 420 DMIPS at 300 MHz– Traffic management– Additional stream processingNot to scale


Cost Savings with Virtex-II Pro

DDCDDC

A/D

A/D

D/A

D/A

MACs

ControlDDCDDC

DUCDUC

DUCDUC

MACs

Control

DSPProcs.

DUCDUC

DUCDUC

DDCDDC DDCDDC

SDRAM

FPGA DSP Card

Hundreds of Termination Resistors

PowerP

C

SDRAM

SSTL3TranslatorsQuad

TRx

QuadTRx

ASSP

FPGA NetworkCard

SDRAM

A/D

A/D

D/A

D/A

Control

Control

PL4

CORBA

PowerPC

MACs, DUCsDDCs, Logic

PowerPC

PowerPCPowerPC

3.125 Gbps

ASSP

SDRAM


Time-to-Market Value

Time

Reve

nue

Additional Profit from

FieldUpgrades

Reduced Profit for Late Introduction

1st to MarketProfit

Fastesttime to market

Longesttime in market

Quicker time to market and reprogrammability provide the best chance of achieving full product profit potential


Xilinx DVB/ATSC Solutions• Xilinx offers programmable solutions at all digital stages of the

DVB/ATSC transmit and receive chains• Multi-channel support available on one chip

– Parameterisable FEC cores supporting DVB/ATSC available now • Plenty of gates available for “back-end” designs and value add

functions for complete system-on-chip solution– Other DSP blocks including filters and image processing cores– Network interface cores available

• Reprogrammability also gives flexibility– Faster time-to-market– Longer time-in-market

• Xilinx Design Services can help for bespoke solutions


Further Reading

• DVB - http://www.DVB.org• ATSC - http://www.ATSC.org• Xilinx FEC Press Release -

http://www.xilinx.com/prs_rls/ip/0265fecsolutions.htm

DVB/ATSC Cable Transmitters and...

Documents

Transcript of DVB/ATSC Cable Transmitters and...