DTU nr. EMI - DTU Electronic Theses and...

Ørsted•DTU nr. EMI Carried out in period: Point: 40 Examine project: Power Amplifier to Ice Sounding Radar

Abstract The objective of this master thesis is to design a broadband RF-power amplifier to ice sounding radar. The bandwidth is 85MHz at a center frequency of 435MHz. The LDMOS transistor technology is used for implementation of the power amplifier. The broadband matching networks should be constructed to satisfy the specifications, such as output average power of 35W, stability and linear phase. The matching networks are optimized by the aid of ADS program to obtain a good performance. The design is implemented on a standard FR4 board. The output power of the signal generator is not enough to drive the power amplifier to the desired output power. The RF-driver amplifier is constructed to drive the power amplifier. The output power of 35W is achieved, but the power amplifier is unstable. The impedance mismatch between the output impedance of the driver amplifier and the input impedance of the power amplifier causes the power amplifier to be unstable. Student: John Bahoor Supervisor Jens Vidkjær Censor

Power Amplifier to Ice Sounding Radar

John Bahoor

Master Thesis

Supervisor

Jens Vidkjær

Technical University Of Denmark April 2006

3

Contents Chapter 1 .............................................................................................................................. 5 Introduction ......................................................................................................................... 5

1.1 Task Description.......................................................................................................... 9 1.2 Design Specifications .................................................................................................. 9 1.3 Project Description .................................................................................................... 10 1.4 Project Writing .......................................................................................................... 10

Chapter 2 ............................................................................................................................ 11 Theory................................................................................................................................. 11

2.1 A generic RF-Power Amplifier ................................................................................. 11 2.1.1 Active Device ..................................................................................................... 13 2.1.2 Passive Input And Output Network.................................................................... 15

2.1.2.1 Inductors ...................................................................................................... 18 2.1.2.2 Capacitors .................................................................................................... 19

2.2 RF-Power Amplifier Theory ..................................................................................... 20 2.2.1 Class A Power Amplifier.................................................................................... 21 2.2.2 High-Efficiency Power Amplifier ...................................................................... 24

2.3 Scattering Parameters Properties ............................................................................... 28 2.4 Matching Network And Smith Chart......................................................................... 30 2.5 RF-Power Amplifier Stability ................................................................................... 33

2.5.1 Small-Signal Power Amplifier ........................................................................... 35 2.5.2 Large-Signal Power Amplifier ........................................................................... 38

2.6 Phase Distortion......................................................................................................... 39 2.7 Lumped Element To Transmission Line Transformation ......................................... 40

2.7.1 Microstrip ........................................................................................................... 42 2.7.1.1 Step In Width............................................................................................... 45 2.7.1.2 Radiation From Microstrip .......................................................................... 46 2.7.1.3 Attenuation In Microstrip ............................................................................ 47

2.8 Power Calculations .................................................................................................... 49 2.8.1 Capacitors Power Handling Capability .............................................................. 50 2.8.2 Microstrip Power Handling Capability .............................................................. 51

2.9 Power Dissipation And Heatsink............................................................................... 53 Chapter 3 ............................................................................................................................ 55 RF-Power Amplifier Simulation ...................................................................................... 55

3.1 Transistor ................................................................................................................... 55 3.2 Basic Configurations Of Single-Stage Power Amplifier........................................... 56 3.3 DC-Bias ..................................................................................................................... 57 3.4 Stability...................................................................................................................... 59 3.5 Design Of Input And Output-Matching Networks .................................................... 61

3.5.1 Input And Output-Matching Networks .............................................................. 65 3.5.2 Feedback Utilization........................................................................................... 76

3.6 Lumped Element To Transmission Line Transformation ......................................... 82 Chapter 4 ............................................................................................................................ 91 RF-Power Amplifier Implementation.............................................................................. 91

4.1 RF-Choke .................................................................................................................. 91 4.2 Capacitor Selection.................................................................................................... 92

4.2.1 Capacitor Power Handling Capability................................................................ 93 4.2.2 Capacitor Model ................................................................................................. 94

4

4.2.3 DC-Block Capacitors.......................................................................................... 97 4.3 Simulation With The Real Components.................................................................... 98 4.4 Layout...................................................................................................................... 104 4.5 Heatsink................................................................................................................... 106 4.6 Mounting Recommendations................................................................................... 109

Chapter 5 .......................................................................................................................... 110 RF-Power Amplifier Test................................................................................................ 110

5.1 DC-Bias ................................................................................................................... 111 5.2 Test The Power Amplifier With The Signal Generator........................................... 112 5.3 Input Reflection Coefficient (S11) Test.................................................................... 114 5.4 Power Amplifier With The Modified S11 Test ........................................................ 120 5.5 Trimmer Capacitors Utilizing.................................................................................. 122 5.6 RF-Driver Amplifier................................................................................................ 124 5.7 RF-Power Amplifier With RF-Driver Amplifier Test............................................. 127

5.7.1 RF-Driver Amplifier Test................................................................................. 129 5.7.2 Output Impedance Of The Driver..................................................................... 130 5.7.3 Attenuator Utilization ....................................................................................... 134 5.7.4 RF-Choke And Grounding Of The Power Amplifier....................................... 135

Conclusion ........................................................................................................................ 137 References ..................................................................................................................... 140

Appendix A: ..................................................................................................................... 142 Calculations Of The Stability Circles........................................................................ 142

Appendix B: ..................................................................................................................... 143 The Short And Open-Circuited Line ......................................................................... 143

Appendix C: ..................................................................................................................... 147 Wave Propagation Calculation .................................................................................. 147

Appendix D: ..................................................................................................................... 149 Microstrip Power Handling Capability ..................................................................... 149

Appendix E: ..................................................................................................................... 152 ADS Equations .......................................................................................................... 152

Appendix F:...................................................................................................................... 153 F.1 Values Of The Stability Factor, K, And Stability Measurement, B1.................. 153 F.2 Small-Signal Stability ......................................................................................... 155

Appendix G: ..................................................................................................................... 156 Method For Analysis Of Nonlinear Circuits ............................................................. 156

Appendix H: ..................................................................................................................... 158 Parasitic Inductance Simulation ................................................................................ 158

Appendix I:....................................................................................................................... 159 Measuring Equipments .............................................................................................. 159

Appendix J: ...................................................................................................................... 160 MATLAB Code......................................................................................................... 160

Appendix K: ..................................................................................................................... 179 RF-Driver Amplifier Layout ..................................................................................... 179

Appendix L: ..................................................................................................................... 180 Compact Disc (CD) ................................................................................................... 180

Introduction 5

Chapter 1

Introduction The thickness of the Antarctica ice sheet is an indicator of the circumstances of the ocean circulation and associated air-sea exchange within the Polar region, and it can have strong effect on the global heat balance. The understanding of the changes of the Antarctica ice sheet is one of the most important research areas for predicting future sea level rise. For this intention a 3-D image of ice sheet is required in order to clarify the ice sheet dynamics. Satellite-based radar would be the only that could provide a complete coverage of the Antarctica ice sheet area from the space. P-Band Ice Sounding Radar could be an appropriate solution for this task. P-Band Ice Sounding Radar, which is specified by European Space Agency (ESA), is intended to penetrate through 4km of ice in Antarctica and detect the ice/bedrock interface. The system should be installed in the aircraft, which satisfies ESA specifications, such as altitude, speed, range and stability. So, selection of the aircraft, which is suitable for carrying and operating a P-Band Ice Sounding instrument in the Antarctica conditions, is also a task. The Twin Otter aircraft, which is Figure 1, is chosen at the time being. The photo presents Twin Otter flying over the Antarctica.

Introduction 6

Figure 1 Twin Otter airplane [17]

The P-Band Ice Sounding Radar system should be mounted on the bottom of the aircraft as it is shown in the Figure 2.

Figure 2 The place where the P-Band Ice Sounding Radar is mounting [17]

Introduction 7

The ESA’s primary interest is in Antarctica, but for financial reasons, the test flights will be conducted in Greenland. The P-Band Ice Sounding Radar system design shall consist of:

− Programmable pulse waveform generation. − Transmit power amplification. − Low noise amplification. − Sampling. − Data handling and data storage. − Instrument control unit. − Instrument control software (PC based). − Power conditioning assuming use is made of the aircraft power supply. − Array antenna.

The Radio Frequency (RF) front-end of the P-Band Ice Sounding Radar will comprise, as stated previously, power amplifier for pulse transmission, which will be emphasized in this report. The average power of the power amplifier is about 300W. There are two ways to generate 300W, either a single high power amplifier with following distribution network or combine a number of power amplifiers with output power of 35W. The benefit of such construction is better system efficiency. For the present, it is not decided yet how the structure of the system is. Currently, the possible block diagram for the front-end of the P-Band Ice Sounding Radar is illustrated in Figure 3.

LNA

2×1 PA Driver

amplifier

Digital circuit

Antenna

Transmitter Receiver H

V

LNA

2×1 PA

Figure 3 Block diagram of the P-Band Ice Sounding Radar.

The block diagram consists of a patch antenna with two channels, vertical and horizontal. For each channel two power amplifiers and one low noise amplifier are connected.

Introduction 8

As stated previously, the total output power is about 300W that means there is four block diagram for the whole system. The transmitter transmits on H-channel and V-channel alternately. When the power amplifiers transmit the signal, the switches should disconnect the low noise amplifier or vice versa. A pulse-generated circuit controls the switches.

Introduction 9

1.1 Task Description The objective of this project is to design, simulate, implement and test Radio Frequency (RF) power amplifier for each of the antennas of P-Band Ice Sounding Radar. The power amplifier operates over a bandwidth of up to 85MHz at a center frequency of 435MHz. The output average power of the power amplifier is 35W. Input and output impedance for the power amplifier is 50Ω and in order to achieve this a matching network should be constructed. More precisely specifications are written in the next section.

1.2 Design Specifications The design specifications for the power amplifier in the whole frequency band are

− 28V DC-power supply. − Up to 1W input power. − Bandwidth of 85MHz at the center frequency of 435MHz. − Input return loss as high as possible. − Output average power of 35W with 1dB ripple. − High drain efficiency. − Linear phase. − The power amplifier should be stable with and without input power. − Second harmonic is low as related to the fundamental tone.

Introduction 10

1.3 Project Description

− Input and output-matching circuits should be constructed for the broadband match. − The design specifications should be maintained. − Simulation results should be related to the theory. − The test results should be related to the simulation results.

1.4 Project Writing The project is organized in four chapters:

- 2 The theory. In this chapter review the basic parameters and fundamental principles for the simple components, which are important to construct the power amplifier. In addition to that the theory part gives understanding of the functionality of the power amplifier.

− 3 RF-power amplifier simulation. The chapter concerns the construction and

simulation the power amplifier. The matching circuits are optimised and tuned by Advanced Design System (ADS) simulation program, to obtain the desire characteristics.

− 4 RF-power amplifier implementation. In this chapter the layout is constructed, the

capacitors kinds are chosen and the heatsink calculation is carried out. − 5 RF-power amplifier test. The method for testing the power amplifier is presented.

RF-driver amplifier is constructed and tested together with the power amplifier.

− Appendix. Contain simulation results, formulas, long calculations, Matlab program codes and the CD with the ADS and Matlab files. In addition to that some supplemental to reading.

− The referring to the reference. In the text is used [n, p. x] and [n, p. x, x] systems,

where n is the reference number in the reference list, p is page and x is the page number.

− Citation. The citation is indicated by quotation marks at the start and end of the

citation.

Theory 11

Chapter 2

Theory The theory of power amplifier design will be introduced in this chapter. In particular, the basic parameters and fundamental principles for the electrical components and circuits are explained. Clarifications of these issues are fundamental to the understanding of the power amplifier design.

2.1 A generic RF-Power Amplifier The single-stage power amplifier presented in this thesis consists of an active device (as the amplifying element) and a passive network (as the matching element) connected to the input and output ports of the active device, as illustrated in Figure 4.

Low power side High power side

Passive input network

Passive output network

Active device

Figure 4 A simplified diagram of a single-stage power amplifier.

Dividing the circuit into three different types of blocks, it is reasonable to investigate the duties of each block in order to achieve the design goals, which include parameters like output power, power gain, efficiency and stability. The purpose of the passive input network is to transform the impedance level at the input port of the active device to a desired interface level, e.g. 50 Ω; this is known as matching. The major purpose of the input matching is to obtain optimal power from the output of the previous circuit to the input port of the active device, and to filter out unwanted signals. The task of the active device is to amplify the input power. The device is mostly a power Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) or power Bipolar Junction Transistor (BJT). Requirements on operating frequency, maximum output power, and power gain determine the choice of the type.

Theory 12

The objective of the passive output network is to transform the impedance level of the load (in this case the load is an antenna with impedance of 50 Ω) to output port of the active device. In addition to the power optimisation, the role of the output network is also to provide a proper wave shaping. It means that it short-circuits a particular list of harmonics. Hence, the voltage and current waves flowing through the active device are properly shaped. The ideal input and output-matching networks are lossless in order not to dissipate signal power. The intension of the active device as well as of the passive network will be briefly be described in the following.

Theory 13

2.1.1 Active Device The popularity of power MOSFET is increasing, aside from high speed and high current capability, it does not suffer from second breakdown. In addition, power MOSFETs do not need the large base-drive currents compared to power BJTs. Second breakdown limit occurs because the current flow across the emitter-base junction is not uniform and the current density is high near the junction. This gives rise to power dissipation and thus temperature rise. The temperature increase causes a rise in current, leading to junction damage. Lateral Double Diffuse Metal-Oxide Semiconductor (LDMOS) is most popular structure for power MOSFET.

Theory 14

Current-Voltage Characteristic Of The Power MOSFET The ideal drain current ID versus gate-source voltage VGS characteristic for the power MOSFETs are similar to the small-signal MOSFETs as it is illustrated in Figure 5.

Figure 5 The ID –VGS characteristic for a power MOSFET [1, p. 794].

The segment labelled ”square law” is according to [1, p. 792]

( ) [ ]AVvL

WCi tGSoxnD2

21

−⎟⎠⎞

⎜⎝⎛= µ (1)

where µn [m2/(Vs)] is the electron mobility in the channel. Cox [f/m2] is the capacitance (Oxide capacitance) between the gate electrode and the channel. Vt [V] is the transistor threshold point1. With large values of vGS the characteristic becomes linear. The linear characteristic is given by [1, p. 794]

][)(21 AVvWUCi tGSsatoxD −= (2)

where W [m] is the channel width. Usat [m/s] is the saturated velocity for the electrons in silicon.

1 In the other literatures the threshold is denoted Vp or Vn.

Theory 15

2.1.2 Passive Input And Output Network The RLC networks (those with resistors, inductors and capacitors) are used to match the impedances, which is important for efficient power transfer. RLC networks are also called resonance circuits. There are basically two kinds of resonance circuits: parallel and series resonance circuits. Basic parallel-and series resonance circuits are illustrated in Figure 6.

Figure 6 Parallel-and series resonance circuits [4, p. 2 ,11].

It is well known, Z= R + jX where R is the resistive component and X is the reactive component. XL =ωL XC = -1/ωC And the reciprocal of impedance is admittance and it is denoted by Y= 1/Z Y= G+jB where G and B are called conductance and susceptance respectively. BL= -1/ωL BC = ωC

Theory 16

Parallel Resonance Circuit In the parallel resonance circuit, the resonance frequency (f0) is the frequency at which the inductive and capacitive susceptances cancel each other. Figure 7 shows jB as function of angular frequency.

Figure 7 jB as function of angular frequency [4, p. 2].

When an external sinusoidal voltage-source of frequency f0 is applied, the capacitive and inductive branch currents will be equal in magnitude and they balance each other. Only the resistor current flows through the terminal. The expressions for resonance frequency and for the 3dB bandwidth (BW) are given in [4, p. 2, 14].

[HzLC

fπ2

10 = ] (3)

[HzQf

BW dB0

3 = ] (4)

Aside from the resonant frequency, another parameter of interest is the quality factor, Q. The quality factor is defined as the ratio between the energy stored and the average power dissipated. The expression for Q is [4, p. 2].

opp CR

LR

Q ωω

==0

(5)

Theory 17

Series Resonance Figure 8 illustrates the behaviour of jX as function of angular frequency ω. As observe jX is zero at the angular frequency ω0.

Figure 8 jX as function of angular frequency [4, p.11].

At the resonance frequency in a series circuit, the voltages across the inductive and the capacitive reactances are equal in magnitudes but opposite in phases. The expression for Q is [4, p.11].

sos RL

CRQ 01 ω

ω== (6)

The resonance frequency and bandwidth can be calculated in Eq. (3) and Eq. (4). Having described the basic passive network, we next describe the basic elements, which construct these networks.

Theory 18

2.1.2.1 Inductors In practice, inductors have a low-value resistance and a capacitance, which is called parasitic capacitance. The electrical model for inductors is shown in Figure 9. The capacitance means that the inductors have a self-resonance frequency (parallel resonance). We can use the Figure 7 illustrates this phenomenon. There are three distinguished regions in the diagram: below the resonance frequency the reactance is inductive, at the resonance the reactances are cancel each other and only the resistive part is exist and above it the reactance is capacitive. Inductors are sometimes referred to as a chokes when used in applications as signal blocking components.

Figure 9 Equivalent circuit of an inductor [18].

Theory 19

2.1.2.2 Capacitors The capacitors, as well as inductors, have parasitic elements and low-value resistance. The equivalent circuit is shown in Figure 10.

Figure 10 Equivalent circuit of a microwave capacitor [19].

In Figure 10 C [F] is the desired capacitance. Ls [H] is the parasitic series inductance. Rs [Ω] is the series resistance. Cp [F] is the parasitic parallel capacitance. Because there are always some parasitic elements associated with capacitors, there will be a series and parallel resonance frequency. At frequencies above series resonance the capacitor acts like an inductor as illustrated in Figure 8 The parasitic parallel capacitance is very small, which results in a parallel resonance frequency a cording to Eq. (3) much higher than the series resonance. Capacitors are used in DC-block, RF-bypass and impedance matching applications. In DC-block applications, the chip capacitor is placed in series with the transmission line to prevent the DC-voltage. In this case the reactance should be very small at the lowest frequency of interest. The maximum value of the capacitor should be less than the self-resonant frequency. In the impedance matching applications, the capacitor is used to provide the required reactance. The basic elements for constructing the power amplifier are explained we next consider the basic theory of the power amplifier.

Theory 20

2.2 RF-Power Amplifier Theory The idea to design a power amplifier is to get most power and maximize the drain efficiency by which the DC-power supply is converted to the RF-output power. The efficiency is extremely desirable to extend the battery life or reduce battery weight and to avoid the massive and large cooling system. When the transistors are driven by a large-signal in power amplifiers, the transistor model turns out to be very complicated [2, p. 2]. Therefore a simplified model is being used for practical applications. “ The construction of RF-power amplifiers often involves substantial experimental efforts [2, p. 2]” We shall see in the following sections that a single-stage power amplifier has efficiency of no more than 50 % if it is driven linearly. To go away from the limiting efficiency, the transistor must be driven nonlinearly. According to the output power and the efficiency the power amplifiers can be divided into two categories, linearly driven power amplifiers (class A amplifiers) and nonlinear, high efficiency, power amplifiers (class B, AB and C amplifiers).

Theory 21

2.2.1 Class A Power Amplifier The ideal large-signal transistor model is shown in Figure 11. Vp denotes the threshold voltage. The input, output and feedback capacitances are ignored to simplify the analysis.

Figure 11 Large-signal model for MOSFET(a).

Id-Vgs characteristic (b) and Id-Vds characteristic (c) [2, p. 2]. The simplified power amplifier circuit is shown in Figure 12, assumed the device is in its optimally matched condition and the current swings from zero to Imax, the voltage VDS swings to its maximum from zero to 2Vdc as shown in Figure 13.

Figure 12 Simplified model for class A amplifier [5, p. 26].

Theory 22

Figure 13 Drain-source voltage VDS and drain current ID characteristic [5, p. 26].

RF-choke is a large inductor to feed the dc bias, which comes from the battery to the drain and is assumed to have a very high reactance at the frequency band. The device is assumed to be perfectly linear in the region between cutoff and saturation. If the bias point is placed in the middle of the linear region and the input signal never exceeds the cutoff and saturation, a perfect linear operation will result. If the drive signal is sinusoidal, the output current will be also sinusoidal and without harmonic components. The power delivered to the load and the corresponding battery power is [5, p. 27, 51].

[ ]WIVP dcdcout 21

= (7)

where

[ ]AII dc max21

= (8)

and

[ ]WIVP dcdcbat = (9)

Theory 23

The efficiency η is defined as the ratio of output power over battery power [5, p. 52].

21

==bat

out

PP

η (10)

From Eq. (10) the maximum efficiency is 50%. That means that half of the battery power is lost in the transistor. The power dissipation in the transistor can be calculated as [20].

[ ]WPPPP inoutbattrans )( +−= (11)

Theory 24

2.2.2 High-Efficiency Power Amplifier To get a high-efficiency power amplifier is to bias the device to quiescent point toward cutoff region. This configuration will decrease the conduction angle. The device is in this case driven nonlinearly, which cause higher harmonic current components. The higher harmonic current components can be shorted out by the output matching circuit. A simplified model of a power amplifier is shown in Figure 14.

Figure 14 Circuit model for of reduced conduction angle amplifier [5, p. 52].

The process of reducing the conduction angle is illustrated in Figure 15.

Figure 15 Current waveform and conduction angle [5, p. 47].

where Vo [V] is the input voltage. Vt [V] is the cutoff point. Vq [V] is the quiescent voltage. Iq [A] is the quiescent current.

Theory 25

The conduction angle, α, indicates the fraction of the cycle for which the conduction occurs. Due to symmetry of the cosine function about zero axis, the current cutoff points are ±α/2, as shown in Figure 15. As the quiescent point is varied, the conduction angle is varied and different modes of power amplifiers are obtained, as is it summarized in Table 1.

Table 1 Different mode of power amplifiers [5, p. 47].

where Vq [V] is normalized according to cutoff point Vt = 0V and Vo =1V As stated before, the device is driven nonlinearly and harmonic current components are generated. By use of Fourier analysis of the waveform, the harmonic components can be found. The mean current or DC-component Idc and fundamental current I1 are important in our design and are given by [5, p. 48]

( ) ( )( ) [ ]A

II dc 2/cos1

2/cos2/sin22max

αααα

π −−

= (12)

( ) [ ]AI

I2/cos1

sin2max

1 ααα

π −−

= (13)

Theory 26

Figure 16 shows the harmonic current components up to n = 5 (I1-I5).

Figure 16 Mean value and harmonic components current [5, p. 49].

The fundamental output power is [5, p.51]

[ ]WIVP dcout 121

= (14)

where I1 is in Eq. (13) and the battery power is

[ ]WIVP dcdcbat = (15)

where Idc is given in Eq. (12) The efficiency is calculated as

bat

out

PP

=η (16)

From Figure 16 it can be seen that for conduction angle lower than π, the DC-component drops, this resulting in, higher efficiency, as stated in Eq. (16). The same time, the fundamental component of the current also starts to drop after the conduction π, this leads to lower output power as in Eq. (14).

Theory 27

For class B condition α = π Eqs. (12) and (13) give Idc = Imax/π I1 = Imax/2 From Eq. (16) the efficiency of class B is given

( ) ( )4/1

4/1/

2/2/12/1

max

max1 πππ

η ====I

IIV

IV

dcdc

dc (17)

That means the efficiency is increased from 50% in the class A to about 78.5% in class B. From this simple calculation and Figure 16, it is clear that decreasing the conduction angle increases the efficiency and decreases the output power. The output power and the efficiency as a function of conduction angle are shown in Figure 17.

Figure 17 Output power and efficiency as a function of conduction angle [5, p. 53].

The basic theory behind the power amplifier is been explained. In the following the two-port network is considered. The two-port network can be the power amplifier or it can be the transistor. This two-port network can be described by scattering parameters (S-parameters). The S-parameters are very useful in the high frequency. They can give full description of the two-port and they can be used for determine the stability region of the transistor, when it is driven with small-signal. The S-parameters are explained in the next section.

Theory 28

2.3 Scattering Parameters Properties Figure 18 shows two-port device connecting to source and load terminations Z0.

Figure 18 Two-port network [6, p. 226].

where Ei1 and Ei2 are the incident waves. Er1 and Er2 are the reflected waves. The two-port relations can be written as [6, p.226]

2221212

2121111

aSaSbaSaSb

+=+=

(18)

where a , b are input and output variables defined as

0

22

0

11

0

22

0

11 Z

Eb

ZE

bZ

Ea

ZE

a rrii ==== (19)

That means the variables are the incident and reflected wave normalized to the square root of the characteristic impedance Z0. The square magnitude of the variable a and b equal to the power of the incident and reflected wave respectively.

Theory 29

If the input port is derived with output port terminated in Z0 sets a2 equal to zero and Eq. (18) gives

1

2

1

2211

1

1

1

111

i

r

i

r

EE

abS

EE

abS ==Γ=== (20)

In the similar fashion, terminating the input port and deriving the output port gives

2

1

2

1122

2

2

2

222

i

r

i

r

EE

abS

EE

abS ==Γ=== (21)

where Γ1 and Γ2 are input and output reflection coefficient respectively. The amount of reflected power can be estimated by input return loss, and is defined, in dB as [7, p. 67]

( ) [ ]dBIRL 1log20 Γ−= (22)

When a input return loss of IRL = 0 all power is reflected, and of IRL → ∞ no power reflected. Since S21 is a ratio of output wave to an input wave, this is yield S212 is called forward transducer power gain, in dB as [6, p. 226]

( ) [ ]dBSGT 21log20= (23)

It is important to mention that there are to kinds of S-parameters; large-signal S-parameter (LSSP) and small-signal S-parameter (SSSP). As mentioned, the S-parameters give fully description of the two-port. The variations of the S-parameters over the entire frequency band describe the difficulties of constructing broadband matching circuits. In the next section the matching technical is considered.

Theory 30

2.4 Matching Network And Smith Chart A Smith chart is a graphical calculator that allows the complicated mathematical calculations to be replaced with geometrical constructs. A Smith chart is a polar plot of the complex reflection coefficient, which represents the ratio of backward and forward waves. By use of Smith chart, the matching networks can be designed. There are different types of matching networks that can be designed. The L sections are simple to design and very practical. To design a broadband network, the Q factor for the network should be low, as stated in Eq. (4) section 2.1.2. Figure 19 illustrates different values of Q.

Figure 19 Contours for Q=1, 5 and 10 [8, p. 134].

Theory 31

The design of a broadband matching network has some difficulties because of the variations of S21, S11 and S22 with frequency as illustrated in Figure 20.

Figure 20 Magnitude of S-parameters as a function of frequency [8, p. 71].

In Figure 20 fs [Hz] is the unity gain. fB [Hz] is the cutoff frequency. To design a constant gain over a broad frequency, the matching network should compensate for the variations over the frequency band. Thus in order to compensate for the variations of S21, the matching network must decrease the gain at some frequencies and increase it at the other frequencies. The Smith chart is a starting point of our design, which can be optimized using ADS program or other programs. Negative feedback Negative feedback can also be used for designing a broadband amplifier to provide a flat gain and reduce and control the variations of S-parameters, but the negative feedback degrades the output power gain. Attenuator The attenuator of Figure 21 is a two-port T-network can be used to match two impedances with attenuation.

n
Zi
Figure 21 Two-port T-network [12, p. 265].

Theory 32

The input impedance is [ 7, p.198]

[ ]Ω++

++=

)()(

012

0121 ZRR

ZRRRZin (24)

where Z0 [Ω] is terminated impedance. The voltage V2 across Z0 can be calculated as [7, p. 198]

[ ]VRZ

ZRR

RVV

tot

tot⎟⎟⎠

⎞⎜⎜⎝

⎛++

=10

0

112 (25)

where Rtot is

( ) [ ]Ω++

+=

012

012

ZRRZRR

Rtot (26)

If R1 = 8.56Ω. R2 =141.8Ω. Z0 = 50Ω. then the input impedance Zin is 50Ω and the attenuation1 is 3dB. The stability is an important issue in designing power amplifier. By utilizing the S-parameters can the stability region determined. In the following section the stability of the power amplifier is explained.

1 The other values for resistors, which give different attenuations, are given in Matlab code in appendix J.19.

Theory 33

2.5 RF-Power Amplifier Stability We should emphasis that the theory bout stability applies only on small-signal (without input power). For large-signal analysis, the stability is complicated because of the nonlinear circuit. Figure 22 shows the FET transistor with the input and output match circuits.

Figure 22 Transistor equivalent circuit with the input and output networks [9, p. 18].

In the following demonstrate the role of K-factor of a degree-of-stability, and the feedback influence on the stability. The transfer impedance of the amplifier is calculated [9, p.18]

12212

2121 yyy

yzP −

−= (27)

where yp is expressed

))((2)( 0Ppp SjCCy −+= ωω µ (28)

and Sp0 is given by

00

0 2ω

ωj

QSP +−= (29)

where Q and ω0 are given in Eqs. (3) and (4) section 2.1.2. The Eq. (27) gives double pole at SP0 if no feedback, y12 = 0.

Theory 34

With the feedback, Cµ, the transfer impedance is [9, p. 19]

))((4 21221

PP

m

SjSjCg

z−−

−=

ωω (30)

where

⎥⎦

⎤⎢⎣

⎡⋅−−−=

Kj

QjSP

212

001

ωω (31)

⎥⎦

⎤⎢⎣

⎡⋅−+−=

Kj

QjSP

212

002

ωω (32)

where

0

22ωµCg

GKm

= (33)

The displacement between these two poles is depending on the K-factor and the K-factor is depending on the feedback, Cµ. The smaller K value, the greater displacement from SP0. This is resulting in the one of the poles is move into the right half of the s-plane makes the amplifier unstable. By connecting a resistor at the input side of the transistor the K-factor value is enhanced.

Theory 35

2.5.1 Small-Signal Power Amplifier A two-port network is shown in Figure 23.

Figure 23 Two-port network [8, p. 217].

If the power amplifier is driven with a small-signal, the stability of the power amplifier can be determined from small-signal S-parameter, input and output-matching networks and source and load impedances. The oscillation of the amplifier possibly occurs if the input or output impedance of the transistor has a negative real part and this occurs when ⎪Γin⎪> 1 or ⎪Γout⎪ > 1. This is because some of passive load and source termination can produce negative real part of output and input impedances of the transistor. There are two types of stability: Unconditional stability [8, p. 217]: If ⎪Γin⎪< 1 and ⎪Γout⎪< 1 for all passive source and load impedance. So the stability condition is [8, p. 217]

1

1

<Γ

<Γ

L

s

11 22

211211 <

Γ−Γ

+=ΓL

Lin S

SSS (34)

11 11

211222 <

Γ−Γ

+=ΓS

Sout S

SSS (35)

Theory 36

Conditional stability or potentially unstable: If ⎪Γin⎪< 1 and ⎪Γout⎪< 1 only for a definite range of passive source and load impedances. From Eqs. (34) and (35) unconditional stability is met if [8, p. 221]:

12

1

2112

2222

211 >

∆+−−=

SSSS

K (36)

01 22

222

111 >∆−−+= SSB (37)

where K and B1 is stability factor and stability measurement respectively. and ∆ is given by

21122211 SSSS −=∆ (38)

Otherwise the transistor is conditionally stable. To determine the regions where the source and load impedances (ΓS and ΓL respectively) produce ⎪Γin⎪=1 and ⎪Γout⎪=1, the input and the output stability circles are calculated1 or plotted by ADS program. For the output stability circle if ZL=Z0 then ΓL = 0 and from Eq. (34) ⎜Γin⎜ = ⎜S11⎜. If ⎜S11⎜< 1 then ⎜Γin⎜< 1 and the center of the Smith chart is in the stable region. The same holds for the input stability circle. On the other hand if ⎜S11⎜> 1 then ⎜Γin⎜> 1, the center of the Smith chart is unstable region. These are illustrated in Figure 24 and Figure 25. It should be emphasized that even when the chose of ΓS and ΓL produce Γin or Γout larger than 1, the power amplifier can be stable.

1 The equations for stability circles are in appendix A.

Theory 37

Figure 24 Output stability circle, the shaded area is stable region [8, p.220].

Figure 25 Input stability circle construction [8, p. 220].

Theory 38

2.5.2 Large-Signal Power Amplifier When the amplifier is driven with the large-signal, the theory about stability circles cannot be used. The procedure is to construct the matching circuits and the stability is checked by transient time characteristics. For stable power amplifier, the characteristic1 should be as in Figure 26, a.

Figure 26 Stable Power amplifier (a). Unstable power amplifier (b) [10, p.10].

To stabilize the power amplifier, a resistor is connected across the input of the power amplifier. The phase distortion is important issue as the stability of the power amplifier. When designing the power amplifier, the phase of the fundamental tone of the power amplifier should be controlled. In the next section a brief description of the linear phase.

1 This figure is taken from oscillator characteristic.

Theory 39

2.6 Phase Distortion Linear phase should be considered when designing a power amplifier. A nonlinear phase characteristic will give rise to distortion in the signal. Whenever a signal is transmitted through a power amplifier, some delay is introduced in the output signal in relation to input signal. If the phase response varies linearly with the frequency, a constant delay is introduced. A nonlinear phase in Figure 27 will give distortion in the output signal Mathematically, the way to control the phase is to take the derivative of the phase with respect to the frequency as in [11, p. 12-30].

[secdfddelayGroup ]φ

−= (39)

Figure 27 Phase response versus frequency [11, p. 12-30]

That means that group delay is a measurement of linearity of the phase. The theory of power amplifier including the matching elements, the stability and the phase distortion are described. In designing the power amplifier, some values of the lumped elements are not available; therefore we use a transmission line instead of the lumped elements. In addition to that it is easy to implement a transmission line. In the following section the transformation between the lumped elements and transmission line is described.

Theory 40

2.7 Lumped Element To Transmission Line Transformation To transform the lumped elements to a transmission line short and open-circuited lines can be used1. The shorted line sections ( < λ/4 [12, p. 91]) act as series inductors and open line sections ( l < λ/4) act as shunt capacitors. Due to difficulty in realizing series-connected shorted stubs in microstrip lines, a stepped-impedance (low and high-impedance) method can be used.

l

To implement low-pass filters or matching circuits in microstrip, alternating sections of high and low impedance lines can be used. The input impedance of a lossless transmission line terminated by a load ZL is given by [12, p.134]

][tantan

0

00

0

00 Ω

++

≈++

=l

l

l

l

ββ

ββ

L

L

L

Lin jZZ

jZZZ

jZZjZZ

ZZ (40)

where β [rad/m] is phase constant2. Z0 [Ω] is the characteristic impedance of the transmission line. Assume the short length lβ < π/6 and high characteristic impedance in comparison with the load impedance, the equation Eq. (40) can be reduced to

][00 Ω+=+≈

vZ

jZjZZZ LLinl

l ωβ (41)

where v [m/s] is the phase velocity of the transmission line. A small section of high impedance line is equivalent to series inductor of value equivalent to

][0 Hv

ZL

l= (42)

The highest practical value that can be chosen is 150 Ω [12, p. 135].

1 The short and open-circuited theory is illustrated in appendix B. 2 A brief calculation of wave propagation is given in appendix C.

Theory 41

From Eq. (40) the admittance can be calculated as

][tantan

0

00

0

00 S

jYYjYY

YjYYjYY

YYL

L

L

Lin

l

l

l

l

ββ

ββ

++

≈++

= (43)

The same assumption as before is used and Y0 >YL, then the input admittance is

][00 S

vY

jYjYYY LLinl

l ωβ +=+≈ (44)

That means a small section of low impedance line is equivalent to shunt capacitor of value

][0 Fv

YC

l= (45)

The lowest practical value is 10 Ω [12, p. 135]. Eqs. (42) and (45) are for the transformation between the lumped elements and the transmission lines. There are many kinds of transmission lines such as microstrip and strip line. We will use a microstrip line in our design; therefore we next present a microstrip transmission line and its prosperities.

Theory 42

2.7.1 Microstrip Microstrip is a transmission line of low loss, high dielectric constant materials and can easily be fabricated for design of most of the microwave integrated circuits. The geometry of the microstrip line is shown in Figure 28.

Figure 28 Microstrip transmission line. (a)The geometry. (b) The Electric fields E, and magnetic fields H [7, p.161].

In Figure 28 d [m] is the thickness of dielectric. W [m] is the microstrip width. εr is the relative permittivity of the substrate. The line consists of a thin conductor (usually copper with a conductivity σ of 5.813 ×107 S/m [7, p. 704]) of width W and ground plane separated by low-loss dielectric (relative permittivity of glass fiber, εr = 4,6 as an example). The electromagnetic field lines in the microstrip are not contained entirely in the substrate. It has some of its field lines in the dielectric region and some fraction in the air as illustrated in Figure 28. Since some of the field lines are in the air and some in the substrate, the effective dielectric constant εe is in the range [7, p.161]

re εε <<1 (46)

The effective dielectric constant εe for a microstrip line can be calculated as [7, p. 162],

2/1

1212

12

1 −

⎟⎠⎞

⎜⎝⎛ +⋅

−+

+=

Wdrr

eεε

ε (47)

Theory 43

For given dimensions of the microstrip line the characteristic impedance can be calculated as [7, p.162]

( )[ ]⎪⎪⎩

⎪⎪

⎨

⎧

≥+++

≤⎟⎠⎞

⎜⎝⎛ +

=1/

444.1/ln667.0393.1/120

1/4

8ln60

0

dWfordWdW

dWford

WWd

Z

e

e

επ

ε (48)

For given characteristic impedance and the effective dielectric constant the W/d ratio can be calculated as [7, p.162]

( ) ( )⎪⎪⎩

⎪⎪⎨

⎧

>⎥⎦

⎤⎢⎣

⎡

⎭⎬⎫

⎩⎨⎧

−+−−

+−−−

<−

=2/61.039.01ln

2112ln12

2/2

82

dWforBBB

dWfore

e

dW

rr

r

A

A

εεε

π

(49)

where

r

rr

rr

ZB

ZA

επ

εεεε

0

0

2377

11.023.011

21

60

=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

+−

++

=

(50)

Theory 44

All dielectrics have a finite amount of conductivity σ. At microwave frequency this property is expressed in terms of the material’s dielectric loss tangent (tan δ), and it can be expressed as [12, p. 22]

0

tanεωε

σδr

= (51)

where ε0 = 8.854 × 10-12 [F/m] is permittivity of free-space [7, p. 704]. The phase velocity of microstrip line is given by [7, p.161.]

[ smcve

/ε

= ] (52)

where c = 3×108 [m/s] is a velocity of the light in free space [7, p. 704].

Theory 45

2.7.1.1 Step In Width Conductor width discontinuities consist of an abrupt change in width from w1 to w2, without any change in the thickness of the conductor or the permittivity εr. Width discontinuities cause field discontinuities, which is due to current density increase from wider to narrower conductor and field scattered on the front edge of the wider side. This is illustrated in Figure 29.

Figure 29 Microstrip step in width [13, p. 273].

In Figure 29 ZL1 and ZL2 are the impedances of the wide and the narrow lines respectively. εr,eff1 and εr, eff2 are the effective dielectric constants of the wide and the narrow lines respectively.

The current compression can generate series inductor and scattered field generates parallel capacitor, as it shown in the equivalent circuit in Figure 30.

Figure 30 Equivalent circuit for step in width [13, p. 273].

Ls and Cp refer to cross-section T in Figure 29. The symbol T1 is for the other equivalent circuits. One way of eliminating these reactive components is by constructing an equivalent circuit for the discontinuity and includes it in the design of the circuit to compensate for the effects by adjusting other circuit parameters.

Theory 46

2.7.1.2 Radiation From Microstrip The radiated power from a microstrip is in two dimensions. One is parallel to the substrate and the other dimension is perpendicular to the substrate as illustrated in Figure 31.These radiations lead to parasitic coupling between various parts of the circuit. So a housing is a good way to isolate the microstrip from other parts of the circuit.

Figure 31 Radiation from microstrip [13, p. 312].

Theory 47

2.7.1.3 Attenuation In Microstrip The attenuation in the microstrip line is caused by dielectric loss or conductor loss. The total attenuation constant is therefore given by [7, p.163]

[ ]mNpcd /ααα += (53)

where αd [Np/m] is the attenuation constant due to dielectric loss. αc [Np/m] is the attenuation constant due to conductor loss. The attenuation due to dielectric loss can be calculated as

[ mNpk

re

erod /

)1(2tan)1(

−

−=

εεδεε

α ] (54)

where k0 is the wave number and it can be determined as

[ mradcfk /2

0 ]π= (55)

The attenuation due to conductor loss is given by

[ mNpWZ

R

o

sc /=α ] (56)

where Rs is the surface resistivity of the inductor and it is given by

[ ]Ω=σ

ωµ2

osR (57)

where σ [S/m] is the conductivity of the transmission line. µ0 = 4π×10-7 [H/m] is the permeability of free-space [7, p. 704].

Theory 48

The attenuation can be calculated in dB as

[ ] [ ]mdBe mNp /log20 /αα = (58)

We are designing power amplifier, therefore all the components and the transmission line should handle high power. It is important to know maximum power the components can handle. In the following the output power calculations and afterwards the power handling capability of the components being used in the design.

Theory 49

2.8 Power Calculations The power calculations at the load impedance ZL, which is driven by a single tone of frequency f0 are summarized. Subsequently the power handling capability of the capacitors and the microstrip are expressed. Instantaneous Power The instantaneous current and voltage at a time t is [4, p. 113]

][)cos()(][)cos()( 00 VtVtVAtItI VLIL φωφω +=+= (59)

where ω0 = 2πf0 [rad/s] is angular frequency. IL [A] and VL [V] are the amplitude of the current and the voltage respectively. ϕI and ϕV [rad] are the corresponding phase angle. The instantaneous power at time t absorbed by the load is expressed

][)cos()cos()()()()( 00 WtVtItPtVtItP VLILLL φωφω ++== (60)

The instantaneous power, or peak power, is an important quantity in applications, because its maximum value must be limited for all physical devices. Average Power The time integral of the instantaneous power over a complete period, divided by the period, and by complex notation, the average power is expressed [4, p.113]

[ ]WviVIP LLVLLLavgL ⋅=+= *, Re)cos(

21 φφ (61)

where iL and vL are rms (root mean square) current and voltage respectively. The average power is also given by

[ ]WRiP LLavgL ⋅= 2, (62)

Theory 50

2.8.1 Capacitors Power Handling Capability The power rating of the capacitor is dependent on the thermal breakdown and voltage breakdown. Thermal breakdown is a temperature rise in the capacitor because of the power dissipation in the capacitor. If the heat generated in the capacitor is greater than it can be conduced away, thermal runaway is created. The voltage breakdown limits the maximum power capability of the capacitor and depends on dielectric material, and separation of the electrodes. Current Rating The equivalent series resistance (ESR) and operating current (Irms) can be used to determine the actual power dissipation as stated in the following formula [21].

[ ]WESRIP rms ⋅= 2)( (63)

Theory 51

2.8.2 Microstrip Power Handling Capability The power handling capability of a microstrip line is limited by the heating caused by the ohmic and dielectric losses, and by dielectric breakdown. The Average Power The average power can be calculated by [14, p. 78]

][max WTTT

P ambavg ∆

−= (64)

where Tmax = 130 [oC] is the maximum operating temperature of the substrate [29]. Tamb [oC] is the ambient temperature and it is equal to 25oC. ∆T [oC/W] is the rise in temperature per watt1. The average power for the microstrip is given by

[ ]WTTT

P ambavg 3.734

108.14325130

3max =

⋅−

=∆−

= − (65)

The Peak Power The maximum peak voltage that can be applied in a microstrip line without causing dielectric breakdown limits the peak power handling capability. The peak power can be expressed by [14, 79]

[ ]WZ

VP o

peak0

2

2= (66)

where V0

[V] is the maximum voltage a line can handle. Z0 [Ω] is the characteristic impedance of the microstrip line. The peak power for the microstrip line is given by

[ ]WZ

VP o

peak6

23

0

2

1015.333.542)1060(

2⋅=

⋅⋅

== (67)

where V0 = 60 [kV] is the dielectric breakdown [29]. Z0 =54.3 [Ω] is calculated by Eq. (48) section 2.7.1.

1 In appendix D is the detail calculation of ∆T.

Theory 52

We should be aware that the transistor dissipates amount of power. That means we will use the heatsink. The heatsink size is depending on the amount of the power dissipation. In the next section we will illustrate the heatsink calculation.

Theory 53

2.9 Power Dissipation And Heatsink The performance reliability and life expectancy of electronic component are inversely related to the component temperature of the component. Therefore, long-time and reliable performance of the component may be achieved by controlling the operating temperature of the device. Junction Temperature Power transistors dissipate large amounts of power in their drain-gate junctions. The dissipated power is converted to heat, which results in raising the junction temperature. The junction temperature Tj must not exceed the specified maximum Tjmax, which is in the range from 150oC to 200oC [1, p.773]. The device manufacturer specifies maximum junction temperature. Thermal Resistance When the transistor dissipates power, the heat in the junction will be conducted away from the junction to the case and from the case to the surrounding. The temperature rise of the junction relative to the surrounding is given by [1, p. 773]

[ ]CPTT oDJAAJ θ=− (68)

where TJ and TA [oC] are the junction and the ambience temperature respectively. θJA [oC/W] is the thermal resistance, junction to ambience. PD [W] is the power dissipating. The thermal resistance gives rise in junction temperature over ambience for each watt dissipated. The value of thermal resistance is usually specified in the data sheet of the transistor. As stated above, TJ must not exceed the maximum TJmax. Therefore it is desirable to have small value of thermal resistance. Eq. (68) can be used to calculate maximum allowable power dissipation by setting TJ =TJmax and TA usually to 25oC. If ambience temperature TA approaches maximum junction temperature TJmax, the power dissipation derates with the value equivalent to 1/θJA. This value is usually written in datasheet.

Theory 54

Heatsink A heatsink is a devise that enhances the heat dissipation from the case of the transistor to air. Heat transfer a cross the interface between the solid surface and the air is the greatest barrier for heat dissipation. A heatsink reduces this barrier by increasing the area that is in contact with the air. The thermal resistance θJA is expressed [1, p. 775]

[ ]WCoSACSJCJA /θθθθ ++= (69)

where θJC [oC/W] is the thermal resistance, junction to case, usually given in datasheet. θCS [oC/W] is the thermal resistance, case to sink. θSA [oC/W] is the thermal resistance, sink to ambience.

.

RF-Power Amplifier Simulation 55

Chapter 3

RF-Power Amplifier Simulation In this chapter a power amplifier will be constructed and simulated by aid of ADS. The design construction is based on the theory, which is described in chapter 2. In the beginning the ideal lumped elements (capacitors and inductors) are used, afterwards the distributed elements (transmission lines) are used instead of the inductors. All the equations for the simulation are in appendix E.

3.1 Transistor In chapter 1, in the design specifications, the amplifier is working at 28V power supply and it should give 35W average power with no more than input power of 1W. LDMOS transistor of type MRF373A [26] is used in this design. The advantages of LDMOS are; simpler biasing circuit, higher power gain than comparable bipolar transistor. The disadvantage is, the gate is very sensitive to electrostatic charge. Transistor Technical Data MRF373ALR1 is n-channel enhancement broadband RF-power MOSFET, designed for broadband applications from 470MHz to 860MHz with 28/32V. Typical performance at 860MHz, 32V, and narrowband fixture gives Output peak power 75W. Power gain of 18.2dB. Efficiency of 60%.


3.2 Basic Configurations Of Single-Stage Power Amplifier There are three basic configurations of single-stage amplifiers; common-gate, common-drain and common-source. The common-gate exhibits a voltage gain as high as common-source, but the input resistance is much lower than common-source. Usually, the common-gate amplifiers are used in cascade circuits. The common-drain amplifier (also known as source follower) provides voltage gain less than unity. The common-drain amplifier is utilized as the output stage in a multistage amplifier. It is used at the output stage because it exhibits a high input resistance and low output resistance. The common-source amplifier can be designed to supply very high voltage gain and exhibits very high input resistance. In this project the common-source power amplifier is utilized.


3.3 DC-Bias The first part in the design of power amplifier is to select a suitable DC-bias operating point. Power supply (VDS) is 28V and gate-source (VGS) voltage is chosen after the threshold point (Vt) is specified. DC-bias network is shown in Figure 32, which is taken from datasheet of the transistor1 (MRF1535NT1).

FSL_MRF_MET_MODELMRF1

CTH=-1RTH=-1TSNK=25MODEL=MRF373A

RR3R=500 Ohm

V_DCSRC1Vdc=Vgs

DC_FeedDC_Feed1

LL7

R=L=47.5 nH

CC19C=150 pF

RR1R=33 kOhm

CC18C=10 uF

CC17C=1.2 pF

CC16C=0.1 uF

CC15C=160 pF

V_DCSRC2Vdc=28

CC11C=150 pF

I_ProbeI-Probe1

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

Figure 32 DC-bias set-up.

1 There is no test set-up for MRF373ALR1, therefore a test set-up for other model is used.


A power supply of 28V is connected through the RF-choke (DC-Feed) to the transistor drain. Gate-source voltage VGS is connected through inductor and resistor R3 (labelled with a circle in the figure) to the gate, the VGS is the same on the gate (ideally). The purpose of the resistor R3 is to stabilize the amplifier, when it is driven with large-signal and the RF-choke is high-impedance at the RF-frequency to prevent RF-signal from being shorted by the bias supply. The other capacitors are to remove the noise from the power supplies. The gate-source voltage VGS is swept at VDS of 28V in order to find the voltage threshold point Vt. The simulation result is shown in Figure 33.

1 2 3 4 50 6

5

0

10

Vgs [V]

Dra

in c

urr

en

t [A

]

Figure 33 Drain current characteristic. The drain current ID characteristic in Figure 33 has a linear characteristic with the gate- source voltage VGS larger than 4.3, as it is explained in Eq. (2) section 2.1.1. From Figure 33 can be seen that the threshold Vt is about 3.2V, therefore the VGS voltage is chosen to be 3.5V, as explained in section 2.2.2. The voltage VGS will be adjusted later on for better performance.


3.4 Stability For small-signal applications the stability criteria, K-factor and stability measurement B1 should be calculated to find out the transistor unconditional stable or potentially unstable. For these calculations S-parameters are utilized. The set-up in Figure 34 is used to simulate the small-signal S-parameters.



V_DCSRC2Vdc=28 V

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

CC11C=150 pF

DC_FeedDC_Feed1

LL1

R=L=47 nH

RR2R=500 Ohm

CC15C=160 pF

CC16C=0.1 uF

CC17C=1.2 pF

CC18C=10 uF

RR1R=33 kOhm

V_DCSRC1Vdc=3.5 V

TermTerm2

Z=50Num=2

DC_BlockDC_Block2Term

Term1

Z=50 OhmNum=1 DC_Block

DC_Block1

CC19C=150 pF

Figure 34 Schematic for simulation the stability factor and stability measurement.

In Figure 34 the transistor has four terminals. We leave the one labelled with T disconnected it does not have influence on the characteristic. By the simulation at 435MHz, the small-signal S-parameters are

freq

435.0 MHz

S(1,1)

0.974 / -172.880

S(1,2)

0.005 / -66.500

S(2,1)

1.093 / 16.674

S(2,2)

0.956 / -162.583

The K-factor and B1 are calculated by using Eqs. (36) and (37) section 2.5.1 and the ADS equations in appendix E

( )( ) ( )86.24929.0

)674.16093.1(5.66005.058.162956.088.172974.021122211

∠=∆∠−∠−−∠−∠=∆

−=∆ SSSS (70)

183.0)005.0(2

929.0956.0974.012

1 222

2112

2222

211 =

+−−=

∆+−−=

SSSS

K (71)

169.0929.0956.0974.011 2222222

2111 =−−+=∆−−+= SSB (72)


By the simulation the K factor and B1 are given

freq

435.0 MHz

StabFact1

0.183

StabMeas1

0.169

The value for K is less than one. The K-factor is simulated1 for the entire frequency band and they are less than one. Therefore, for this transistor at the frequency band, the transistor is potentially unstable. Since the transistor is potentially unstable the stability circles are utilized to find the stable regions. The relations found in appendix A can calculate the stability circles, and the result can be plotted on the Smith chart. The stability circles can also be simulated by ADS by using the SStabCircle and LStabCircle items. Figure 35 shows input and output stability circles. Since magnitude of S11 and S22 are less than one, the center of Smith chart is a stable region. To design matching circuits, ΓS and ΓL should be chosen in the stable region, then use the matching technique to 50Ω. For large-signal application, which is our case, this technique is not utilized, therefore matching networks should be constructed and afterwards the stability investigated.

Figure 35 Input stability circle (left), and output stability circle (right).

1 In appendix F.1 the simulation of K, B1 , S11 and S22 in the entire frequency band.


3.5 Design Of Input And Output-Matching Networks The design of input and output circuits is considered. In the initial designs the power amplifier without negative feedback connection is considered, and afterwards the feedback is utilized to see the influence on the amplifier performance. Later on we decide if we use the feedback or without feedback in the final set-up. Input And Output Impedances To design matching network we need to know the value of input and output impedances of the transistor. The power transistor behaves in a way such that the input and output impedances are change under varying load, input power and bias conditions. Using probes at the input side and output side of the transistor we can measure the impedances. With the input power of 100mW1 the set-up is simulated with Harmonic Balance2 to find the voltage at the input and the output side of the transistor. The schematics for the input and the output impedance simulation are in Figure 36 and Figure 37 respectively. For the input impedance at 435MHz, the simulation gives the voltage and current at the input side of the transistor V = 0.388V∠-70.43o

I = 0.124A∠4.93o

The input impedance is given as

[ ]Ω−∠=∠−∠

== 36.75129.393.4124.0

43.70388.0IVZin (73)

1 Input power 100mW is chosen arbitrarily. 2 In appendix G the concept of Harmonic Balance is explained.


For the output impedance at 435MHz, the simulation gives the voltage and current at the output side of the transistor V = 0.943V∠-71.531o

I = 0.122A∠9.992o The output impedance is given as

[ ]Ω−∠=∠−∠

== 523.81740.7992.9122.0

531.71943.0IVZout (74)


Vinput

vout



CC21C=270 pFC

C20C=270 pF

LL7

R=L=47.5 nH

RR3R=500 Ohm

CC11C=150 pF

CC19C=150 pF

V_DCSRC2Vdc=28 V

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

DC_FeedDC_Feed1

V_DCSRC1Vdc=3.5 V

P_1TonePORT1

Freq=LSSP_freqP=100 mWZ=50Num=1

TermTerm2

Z=50Num=2

I_ProbeI_Probe2

I_ProbeI_Probe1

CC15C=160 pF

CC16C=0.1 uF

CC17C=1.2 pF

CC18C=10 uF

RR1R=33 kOhm

Figure 36 The input impedance set-up.

Vinput

vout



CC20C=270 pF

CC21C=270 pF

P_1TonePORT1


I_ProbeI_Probe2

TermTerm2

Z=50Num=2

LL7

R=L=47.5 nH

RR3R=500 Ohm

CC11C=150 pF

CC19C=150 pF

V_DCSRC2Vdc=28 V

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

DC_FeedDC_Feed1

V_DCSRC1Vdc=3.5 V

I_ProbeI_Probe1

CC15C=160 pF

CC16C=0.1 uF

CC17C=1.2 pF

CC18C=10 uF

RR1R=33 kOhm

Figure 37 The output impedance set-up.


The input and the output impedances in the whole frequency band are plotted in Smith chart by ADS program and the results are shown in Figure 38.

m1LSSP_freq=Gama_out=0.958 / -162.559impedance = Z0 * (0.022 - j0.153)

4.350E8m1LSSP_freq=Gama_in=0.970 / -impedance = Z0 * (

173.0390.015 - j0.061)

4.350E8

LSSP_freq (392000000.000 to 477000000.000)

Ga

ma

_in

m1

m1LSSP_freq=Gama_in=0.970 / -173.039impedance = Z0 * (0.015 - j0.061)

4.350E8

LSSP_freq (392000000.000 to 477000000.000)

Ga

ma

_o

ut

m1

m1LSSP_freq=Gama_out=0.958 / -162.559impedance = Z0 * (0.022 - j0.153)

4.350E8

Figure 38 Input impedance (left) and output impedance (right).

The impedances at the center frequency 435MHz are used in the design process.


3.5.1 Input And Output-Matching Networks The input and output impedances should be transferred to 50Ω, by plotting them in the Smith Chart Program1. Matching procedure starts at the point indicated by no.1, which represents the input of the transistor and ends in the middle of the Smith chart (which represents 50Ω impedance) as illustrated in Figure 39.

Figure 39 Input impedance and matching circuit. ZL is the input impedance of the transistor. Similarly with the output impedance as it is shown in Figure 40.

Figure 40 Output impedance and matching circuit. ZL is the output impedance of the transistor.

1 Smith Chart program is not ADS program.


The values of the elements are found directly from the program. The input and output-matching circuits are connected to the transistor through the DC-block1 capacitor of 270pF as it shown in Figure 41. The matching circuits should match the input and output impedances of the transistor to the source and the load impedance, respectively in the whole frequency band. The matching network, which is found, is only for one frequency (center frequency). That means that further optimisation and tuning by ADS are needed in order to realise the broadband matching. To get a broadband match only by optimisation is not enough, therefore the parameters (capacitors and inductors) should be tuned manually. Initially we use the input power of 100mW and simulate with large-signal S-Parameter (LSSP). The input power will be adjusted later on for better performance.

vout


CTH=-1RTH=-1

TSNK=25MODEL=MRF373A

P_1TonePORT1

Freq=LSSP_freqP=100 mWZ=50

Num=1

CC30C=43.296 pF

CC28C=33.2068 pF

LL7

R=L=5.31888 nH

RR2R=500 Ohm

CC19C=150 pF

CC11C=150 pF

LL14

R=L=47.5 nH

CC20C=270 pF

CC25C=6.6 pF

LL13

R=L=2.2 nH

CC21C=270 pF

Term

Term2

Z=50Num=2

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

DC_FeedDC_Feed1

V_DCSRC1

Vdc=3.5 V

CC29C=10 pF

V_DCSRC2Vdc=28 V

CC15C=160 pF

CC16C=0.1 uF

CC17C=1.2 pF

CC18C=10 uF

RR1R=33 kOhm

Figure 41 The input and output-matching circuits.

After the optimisation and the tuning, the gain and input return loss are calculated by using Eqs.(22) and (23) section 2.3. To do these calculations, we first simulate the magnitudes of S11 and S21 and the results are shown in Figure 42.

1 The DC-block is chosen arbitrarily.


3.5

E8

4.0

E8

4.5

E8

5.0

E8

5.5

E8

3.0

E8

6.0

E8

2

4

0

6

ma

g(S

(1,1

))

m4

ma

g(S

(2,1

))

m3

m3LSSP_freq=mag(S(2,1))=5.923

4.320E8m4LSSP_freq=mag(S(1,1))=0.366

4.320E8

f [MHz] Figure 42 The magnitude of S11 and S21.

Gain and input return loss at 432MHz (is chosen arbitrarily) are calculated as

[ ]dBSGT 4.15)9.5log(10log10 2221 =⋅== (75)

[ ]dBSIRL 73.8)366.0log(20log20 11 =⋅=−= (76)

The ADS simulator can simulate S11 in dB and the simulation result is shown in Figure 43.

4.0E8 5.0E83.0E8 6.0E8

0

10

-10

20

dB(S

(1,1

))

m1dB(S

(2,1

))

m2

m1LSSP_freq=dB(S(1,1))=-8.738

4.320E8m2LSSP_freq=dB(S(2,1))=15.451

4.320E8

f [MHz] Figure 43 Gain and Input return loss.

We can see that the characteristic is a small band. By using low Q factor, as it is written in section 2.4, the bandwidth is enhanced by implementing a multistage matching circuit as illustrated in Figure 44 and Figure 45.


Figure 44 Input impedance and its equivalent matching circuit.

Figure 45 Output impedance and its equivalent matching circuit.


The input and output-matching circuits of Figure 44 and Figure 45 are connected to the transistor as it is shown in Figure 46. The configuration in Figure 46 gives the characteristic in Figure 47, after the set-up is optimised and tuned.

vout

LL14

R=L=47.5 nH

CC11C=150 pF

P_1TonePORT1


CC28C=18.96 pF

LL7

R=L=3.64 nH

LL8

R=L=2.47 nH



CC21C=270 pF

CC20C=270 pF

V_DCSRC1Vdc=3.5 V

CC19C=150 pF

RR2R=500 Ohm

CC26C=14.0 pF

LL10

R=L=7.52 nH

LL13

R=L=2 nH

CC22C=3.17 pF

CC23C=70.21 pF

DC_FeedDC_Feed1

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

CC25C=9.93 pF

I_ProbeI_Probe1

V_DCSRC2Vdc=28 V

TermTerm2

Z=50Num=2

CC15C=160 pF

CC16C=0.1 uF

CC17C=1.2 pF

CC18C=10 uF

RR1R=33 kOhm

Figure 46 The input and output-matching networks.

3.5E8 4.0E8 4.5E8 5.0E8 5.5E83.0E8 6.0E8

-10

0

10

20

-20

30

dB

(S(1

,1))

m3m4

dB

(S(2

,1))


4.780E8m4LSSP_freq=dB(S(1,1))=-1.399

3.920E8

f [MHz] Figure 47 Gain (S21) and input return loss (S11).

Figure 47 shows that the characteristics are still small band. To obtain a broader band, several sections should be used. Unfortunately, the Smith Chart Program is a demo program and that is why we cannot use more than five elements. Therefore extra components are added and optimisation and tuning is carried out. Figure 48 and Figure 49 show the input and output-matching networks after they are optimised and tuned.


CC29C=7.98 pF

CC30C=0.2 pF

CC23C=155.99 pF

CC28C=0.1 pF

CC22C=18.7 pF

LL7

R=L=2.2 nH

LL16

R=L=2 nH

LL15

R=L=2.2 nH

LL8

R=L=2.01 nH

PortP1Num=1

PortP2Num=2

Figure 48 Input matching network.

LL16

R=L=2.34 nH

LL13

R=L=4.43 nH

LL10

R=L=13.66 nH

CC25C=27.54 pF

CC26C=9.3 pF

PortP1Num=1

PortP2Num=2

CC30C=19.74 pF

Figure 49 Output matching network. The input power of the set-up is 99mW and the gate-source voltage VGS of 3.85V. The specifications such as output power drain efficiency, linear phase, second harmonic and stability are simulated. Later on we simulate the power amplifier without input power to see if it is stable with the input and output-matching circuits. The gain and the input return loss are shown in Figure 50.

3.5E8 4.0E8 4.5E8 5.0E83.0E8 5.5E8

-10

0

10

20

-20

30

dB(S

(1,1

))

m3m4dB(S

(2,1

))

m1


4.770E8m4LSSP_freq=dB(S(1,1))=-8.921

3.930E8m1LSSP_freq=dB(S(2,1))=25.425

4.290E8


The marks m3 and m4 represent the bandwidth.


The output average power is calculated as in Eq. (62) section 2.8.

RIP peakout ⋅=2

21 (77)

To simulate the average power we use a probe at the load and simulate the magnitude of the current Ipeak and by using Eq. (77) the average power is shown in Figure 51.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

34.5

35.0

35.5

34.0

36.0

f [MHz]

Ave

rage

pow

er [

W]

m2

m2LSSP_freq=P_average=35.547

4.110E8

Figure 51 Output average power.

To calculate the efficiency we use the Eq. (16) section 2.2.2.

VIP

D

out

28⋅=η (78)

That means we need to simulate the DC-drain current ID.

Similarly, by using a probe at the drain of the transistor, the DC-drain current can be simulated as shown in Figure 52.


4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

2.3

2.4

2.5

2.2

2.6 m6

m6LSSP_freq=real(I_Probe1.i[::,0])=2.538

4.110E8

f [MHz]

ID [

A]

Figure 52 Drain current as a function of frequency.

To calculate the drain efficiency at 411MHz (which is chosen arbitrarily)

%501002853.2

5.3510028

=⋅⋅

=⋅⋅

=VI

P

D

outη (79)

The simulation result can be seen in Figure 53, m5. The simulation result of the drain efficiency in the entire frequency band is illustrated in Figure 53.

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

50

52

54

48

56

f [MHz]

Eff

icie

ncy

%

m5

m5LSSP_freq=real(efficiency)=50.016

4.110E8

Figure 53 Drain efficiency.


By using Harmonic Balance simulation the phase can be simulated. The phase of the fundamental tone over all swept values is illustrated in Figure 54.

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

0

50

100

150

-50

200

f [MHz]

De

gre

e [

C]

Figure 54 Phase characteristic.

The group delay can be calculated by Eq.(39) section 2.6

[sec]dfddelayGroup φ

−= (80)

In the ADS we can differentiate the phase by writing an equation in the equation field. The group delay is simulated and the result is shown in Figure 55.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

1.8E-6

2.0E-6

2.2E-6

2.4E-6

1.6E-6

2.6E-6

f [MHz]

Tim

e [s

ec]

Figure 55 Group delay.


The second harmonic can also be simulated with the Harmonic Balance. The second harmonic in dB over all swept values is shown in Figure 56.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

0

10

20

30

40

-10

50

f [MHz]

dBm

(vou

t[::

,1])

dB(v

out[

::,2

])

Figure 56 Second harmonic as related to fundamental tone.

As mentioned in section 2.5.2 the resistor R3 is used to stabilize the power amplifier. By adjusting R3 to 30Ω, the power amplifier stability characteristic at 435MHz is shown in Figure 57, which is stabilizing after 250nsec. In order to check the stability in the entire frequency band, the transient time simulation will be performed also at the several frequencies.

50 100 150 200 250 300 350 400 4500 500

-20

0

20

-40

40

Time [nsec]

Vo

ut [

V]

Figure 57 Transient time simulation.

To simulate the stability of the set-up without input power we use small-signal S-parameter. We simulate the K-factor1 and B1. The simulation results of K-factor are less than 1. Thus the power amplifier is potentially unstable. As stated in section 2.5.1, even the transistor has a negative real part of the input or output impedance the power amplifier can be stable.

1 The set-up for the simulation is in appendix F.2.


Sub-Conclusion Input return loss (S11) depends on the input and output-matching circuits. There is a trade off between (S11) and output power characteristic. We can obtain a good (S11) but undesirable output power and vice versa. The bandwidth of the power amplifier is depending on the number of the sections. It is found that the several sections give a broader bandwidth. Figure 50 illustrates the broadband matching with input return loss of minimum (-8dB), which is acceptable. The output average power of around 35W in the range between 392MHz and 478MHz with the ripple of 1dB satisfies the specification, sees in Figure 51. With regard to efficiency as it is seen in Figure 53 about 50% of the battery power is dissipated in the transistor, and it is a good efficiency. The output voltage of the fundamental tone varies in a delay as related to input as it is shown in Figure 55. There is no specific specification about the group delay. The Second harmonic is attenuated 45dB as related to the fundamental tone, which is good result, as it can be seen in Figure 56. Finally the stability is achieved by adjusting the resistor R3 to 30Ω, and the power amplifier is stabilized after 250nsec, as it is shown in Figure 57. The small-signal stability simulation is performed and the power amplifier is potentially unstable. We should be aware of the stability of the power amplifier without input power in the DC-test in the test process.


3.5.2 Feedback Utilization The most common methods for using negative feedback are shunt resistor between drain and gate or series resistor between source and ground. In the design project a shunt resistor is utilized as shown in Figure 58. The capacitor is for the DC-block.

Figure 58 Transistor with shunt feedback resistor. We connect the feedback configuration to the previous set-up and optimise the input and output-matching circuits. The final components values are in Figure 59 and Figure 60 and the input power of 231mW and the gate-source voltage VGS of 3.85V. The feedback resistor is 186Ω and the capacitor is 75.11pF.

PortP2Num=2

CC30C=9.2544 pF

CC22C=17.39 pF

CC29C=3.93912 pF

CC28C=40.032 pF

CC23C=128.4893 pF

LL16

R=L=1.99 nH

LL7

R=L=1.80531 nH

LL15

R=L=4.31508 nH

LL8

R=L=1.72332 nH

PortP1Num=1

Figure 59 Input circuit of the feedback set-up.


CC30C=14.46016 pF

CC25C=30.284 pF

CC26C=9.403 pF

LL10

R=L=12.345 nH

LL13

R=L=4.96335 nH

LL16

R=L=2.19114 nH

PortP2Num=2

PortP1Num=1

Figure 60 Output circuit of the feedback set-up. We use the equations in the previous section to calculate and simulate the characteristics of the power amplifier. The gain and input return loss are shown in Figure 61.

3.5E8 4.0E8 4.5E8 5.0E83.0E8 5.5E8

-10

0

10

20

-20

30

dB(S

(1,1

))

m1m2

dB(S

(2,1

))

m5


4.770E8m2LSSP_freq=dB(S(1,1))=-15.343

3.900E8m5LSSP_freq=dB(S(2,1))=21.739

4.380E8



The output average power is presented in Figure 62.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

34.6

34.8

35.0

35.2

35.4

34.4

35.6

f [MHz]

Ave

rage

pow

er [

W]

m3 m4


3.920E8m4LSSP_freq=P_average=34.964

4.780E8


The drain current is simulated as it shown in Figure 63.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

2.60

2.65

2.70

2.55

2.75

f [MHz]

ID [

A]

Figure 63 Drain current characteristic.


Drain efficiency is illustrated in Figure 64.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

46.5

47.0

47.5

48.0

46.0

48.5

f [MHz]

Eff

icie

ncy

%

Figure 64 Efficiency of the feedback set-up.

The phase characteristic and its derivative are shown in Figure 65 and Figure 66.

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

50

100

150

0

200

f [MHz]

De

gre

e [

C]

Figure 65 Phase characteristic over all swept values.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

1.7E-6

1.8E-6

1.9E-6

2.0E-6

2.1E-6

1.6E-6

2.2E-6

f [MHz]

Tim

e [s

ec]

Figure 66 The group delay.


The second harmonic is illustrated in Figure 67.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

0

10

20

30

-10

40

dB(v

out[

::,1

])dB

(vou

t[::

,2])

f [MHz] Figure 67 The second harmonic as related to fundamental tone.

The stability is simulated at 435MHz and the result is shown in Figure 68.

0.2 0.4 0.6 0.80.0 1.0

-20

0

20

-40

40

Time [usec]

Vo

ut

[V]



Sub-Conclusion The input return loss in Figure 61 is improved compare with Figure 50 (the set-up without feedback). The phase and the second harmonic are acceptable as in Figure 66 and Figure 67 respectively. The efficiency of the power amplifier in Figure 64 is not so good as it is without the feedback in Figure 53. This is because the drain current as it is shown in Figure 63 is higher than the drain current illustrated in Figure 52. The high input power leads to a large conducting angel. Figure 16 section 2.2.2 shows that the DC-current is high with the large conducting angel. From Eqs. (15) and (16) section 2.2.2 the high drain current result in low efficiency. Comparing Figure 50 and Figure 61, the gain in the feedback configuration is 3.7dB less than the one without feedback connection. This is the drawback of using the feedback configuration. Figure 68 shows that the amplifier is stabilizing after 0.6µsec after adjusting the resistor R3 to 10Ω. Without feedback the power amplifier stabilizes after 0.2µsec. It shows the influence of negative feedback on the behaviour of the power amplifier. Because of the efficiency, the gain and the stability the feedback will not be utilized in the set-up.


3.6 Lumped Element To Transmission Line Transformation The values of the inductors in Figure 48 and Figure 49 are not existing therefore we use transmission lines. To transform the lumped element to transmission line Eq. (42) section 2.7 is used. We maintain the impedance to specified value and vary the length. As stated Eq. (48) in section 2.7.1 the width and the impedance are related together. That means the width of transmission line is fixed to a defined value and the length is varied. For practical reasons the width of all the transmission lines should be the same. For 50Ω impedance the width of the line is calculated1 by using Eq. (49) section 2.7.1 gives W= 2.8 [mm] From Eq. (47) εe is calculated as

46.31212

12

1 2/1

=⎟⎠⎞

⎜⎝⎛ +⋅

−+

+=

−

Wdrr

eεε

ε (81)

where d = 1.55 [mm] is the thickness of the dielectric [29] εr = 4.6 is the dielectric constant of the glass fibber [29]. The phase velocity is calculated by Eq. (52) section 2.7.1, which gives

[ smcve

/103.16146.3

103 68

⋅=⋅

==ε

] (82)

The length of the line is from Eq. (42)

][0

HZ

vL ⋅=l (83)

where Z0 is 50Ω.

1 In appendix J.1 a Matlab code to calculate the width of the transmission line.


The lengths of the lines of Figure 48 Figure 49 are calculated, and the values are given in Table 2.

Input circuit inductor [nH] Transmission line [mm] 2.01 6.48 2.2 7.09 2 6.45

Output circuit inductor [nH] Transmission line [mm] 2.34 7.54 4.43 14.29 13.66 44

Table 2 Inductor to transmission line calculation.

The input and output-matching circuits for transmission line are in Figure 69 and Figure 70 respectively.

CC29C=7.98 pF

PortP2Num=2

PortP1Num=1

CC22C=18.7 pF

CC28C=0.1 pF

CC23C=155.99 pF

CC30C=0.2 pF

MLINTL4

L=6.4 mmW=2.8 mmSubst="MSub1"

MLINTL3

L=7 mmW=2.8 mmSubst="MSub1"

MLINTL2


MLINTL1



MLINTL2


MLINTL1


CC25C=27.54 pF

CC26C=9.3 pF

CC30C=19.74 pF

MLINTL3


PortP2Num=2

PortP1Num=1

Figure 70 Output matching network.


With the same gate-source voltage VGS of 3.85V and input power of 99mW the characteristics of amplifier are shown in Figure 71 and Figure 72.

3.5E8 4.0E8 4.5E8 5.0E83.0E8 5.5E8

-10

0

10

20

-20

30dB

(S(1

,1))

m3m4dB(S

(2,1

))m5


4.760E8m4LSSP_freq=dB(S(1,1))=-10.937

3.940E8m5LSSP_freq=dB(S(2,1))=24.530

4.300E8

f [MHz]

Figure 71 Gain (S21) and return loss (S11).

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

30

31

32

33

29

34

f [MHz]

Ave

rag

e p

ow

er

[W]

m1m2



4.770E8


The result in Figure 71 and Figure 72 demonstrate the theory of lumped element to transmission line transformation. We can see the matching circuits need optimisation to obtain the desire output power. Any way, there are two things, which should be taken into consideration before we continue the design.


The DC-block capacitors should be removed and placed at the end of the transmission line to avoid the reactive component, which occurs from the step in width. The other thing is that the transistor has two copper tongs flange and they should be simulated as transmission lines. The set-up of Figure 69 and Figure 70 is modified with extra transmission lines and capacitors. We use the set-up of Figure 73 with the input and output-matching circuits of Figure 74 Figure 75. The length and width of transmission lines and the capacitors are optimised. The transmission lines width of the input and output-matching circuits become 2.8mm and 2.5mm respectively.

vinput

vout

P_1TonePORT1

Freq=LSSP_freq

P=200 mWZ=50Num=1

V_DCSRC1

Vdc=3.7 V


CTH=-1RTH=-1TSNK=25

MODEL=MRF373A

TermTerm2

Z=50Num=2

inputidealX1

I_ProbeI_Probe5outputideal

X2

DC_FeedDC_Feed1

I_ProbeI_Probe4

V_DCSRC2Vdc=28 V

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

CC11C=150 pF

C

C19C=150 pF

L

L1

R=L=47 nH

R

R1R=33 kOhm

C

C18C=10 uF

C

C17C=1.2 pF

C

C16C=0.1 uF

C

C15C=160 pF

RR2R=30 Ohm

Figure 73 Power amplifier with transmission lines.

These two boxes, X1 and X2, are contain input and output circuits.


MLINTL4


CC23C=3.9 pF

CC22C=33 pF

CC33C=39 pF

CC28C=27 pF

CC30C=100 pF

MLINTL7


MLINTL11


MLINTL5


MLINTL9


CC32C=15 pF

MLINTL10

L=10 mmW=2.8 mmSubst="MSub1" MSTEP

Step1

W2=7 mmW1=2.8 mmSubst="MSub1"

MLINTL8

L=6.9 mmW=7 mmSubst="MSub1"

PortP2Num=2

CC31C=270 pF

PortP1Num=1


MLIN

TL8

L=9.9 mmW=2.5 mm

Subst="MSub1"

MLIN

TL9

L=3 mmW=2.5 mm

Subst="MSub1"

MLIN

TL6

L=23.4 mmW=2.5 mm

Subst="MSub1"

MLIN

TL10

L=18.7 mm

W=2.5 mmSubst="MSub1"

CC35

C=7.5 pFC

C25C=10 pF

CC30

C=10 pF

C

C33C=18 pF

MLINTL1

L=7.8 mm


Port

P1

Num=1

MLIN

TL4

L=7.50039 mm

W=7 mmSubst="MSub1"

MSTEPStep1

W2=2.5 mm

W1=7 mmSubst="MSub1"

Figure 75 Output matching network.

The MSTEP (labelled with circle) is added because the different in wtransistor tongs and transmission lines to compensate for the reactancexplained in section 2.7.1.1.

Simulate the tong of the transistor

C

C34C=5.6 pF

CC32

C=270 pF

Port

P2

Num=2
Simulate the tong of the transistor
idth between the e components as


It should be emphasised that, the matching circuits are tuned to the values of the capacitors that we can find. It would be waste of time if the capacitors values did not exist, even if we get better performance. The gate-source voltage VGS of 3.7V give drain current Id0 equal to 400mA and input power of 200mW. The characteristics of this set-up are in the following: Input return loss and gain is in Figure 76.

3.5E8 4.0E8 4.5E8 5.0E83.0E8 5.5E8

-10

0

10

20

-20

30

dB

(S(1

,1))

m2m3dB

(S(2

,1))

m5


4.770E8m3LSSP_freq=dB(S(1,1))=-8.812

3.930E8m5LSSP_freq=dB(S(2,1))=22.339

4.290E8

f [MHz]

Figure 76 Input return loss (S11), gain (S21). The marks m2 and m3 represent the bandwidth. Output average power and drain current are shown in Figure 77 and Figure 78.

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

33

34

35

32

36

f [MHz]

Ave

rag

e p

ow

er

[W] m1

m4



4.770E8

Figure 77 Output average power. The marks m1 and m4 is the bandwidth.


4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

2.7

2.8

2.6

2.9

f [MHz]

ID [

A]

Figure 78 Drain current.

The efficiency of the power amplifier is in Figure 79.

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.9

E8

4.8

E8

43

44

45

46

42

47

f [MHz]

Eff

icie

ncy

%


The phase characteristic is shown in Figure 80.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

-200

-150

-100

-50

-250

0

f [MHz]

Deg

ree

[C]

Figure 80 Phase of fundamental tone over all swept values.


The group delay is simulated in Figure 81.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

2.0E-6

2.1E-6

2.2E-6

2.3E-6

2.4E-6

2.5E-6

1.9E-6

2.6E-6

f [MHz]

Tim

e [s

ec]


Second harmonic over all swept values is illustrated in Figure 82.

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.9E8

4.8E8

10

20

30

0

40

dB(v

out[

::,1

])

m6

dB(v

out[

::,2

])

m7

m6LSSP_freq=dB(vout[::,1])=35.221

4.770E8m7LSSP_freq=dB(vout[::,2])=13.293

4.770E8

f [MHz]

Figure 82 Second harmonic as related to fundamental tone.

With R3 is 30Ω the stability of the power amplifier at 435MHz is in Figure 83.

50 100 150 200 250 300 350 400 4500 500

-20

0

20

-40

40

Time [nsec]

Vou

t [V

]



Sub-Conclusion In this chapter the transformation from lumped elements to transmission lines is completed. We found out how many sections we need to design the power amplifier to obtain the specified characteristics. The power amplifier can be tuned to the better performance, but the capacitors values are not exist. We can see from Figure 76 the return loss is lower than –7dB, which is accepted. The output power is around 35W and with about 1dB ripple satisfies the specification, as shown in Figure 77. The efficiency is lower than 50% as expected, see Figure 79. As explained in sub-conclusion in the feedback section, that the high input power leads to high drain, which results in low efficiency. We do not have problems with the phase characteristic and the stability as illustrated in Figure 81 and Figure 83 respectively. The second harmonic at the high end of the bandwidth is the lowest, but it is attenuated more than 20dB as related to fundamental tone as it is shown in Figure 82.

RF-Power Amplifier Implementation 91

Chapter 4

RF-Power Amplifier Implementation In chapter 3, the power amplifier with the ideal components is constructed. In this chapter we have to realize the RF-choke and to find the capacitors that can handle high power. We will also simulate the set-up of Figure 73 section 3.6 with the capacitor models instead of the capacitors in Figure 74 and Figure 75 to see the influence of the parasitic elements on the power amplifier characteristics. The layout and the heatsink size will be constructed and calculated respectively. Finally the mounting recommendation considered.

4.1 RF-Choke The choke should be chosen in order not to influence the tuning circuit. The set-up in Figure 73 is simulated with different inductor instead off the DC-feed values and it is noticed that the inductor with 0.5µH is not influencing on the characteristics. To obtain this value an air coil inductor is constructed from Wheeler formula [23]

[ ]HAr

NrL254228

001.0 22

+= (84)

where r [m] is the radius of coil. N is the number of turns. A [m] is the length of winding. By using inductance calculator [24], which is based on Eq. (84), with 7 turns, r = 6.5mm and coil length 10mm can the 0.5µH inductor be obtained.


4.2 Capacitor Selection There are many kinds of capacitors for RF application such as AVX and ATC multilayer ceramic capacitors. ATC 100 B Series capacitors [30] are chosen because they have following specifications: High self-resonance. Ultra-stable performance. Low noise. Low ESR. Besides there are two designing kits (10pF-100pF and 100pF-1000pF) available in the EMI department at Ørsted•DTU.


4.2.1 Capacitor Power Handling Capability The maximum current rating is stated in two ways. Voltage limited or power dissipation limit as it is shown in Figure 84.

Figure 84 Relationship between current Irms, capacitance and frequency [21].

The voltage limited is the solid line and the power dissipation limit is the dotted line. For 1pF capacitor at 500MHz the power handling capability is

[ ]WVIP rmsrms 353707.05001 =⋅⋅=⋅= (85) where Vrms = 500 ×0.707 V [30]


4.2.2 Capacitor Model The model for the capacitors were not available at the website or in ADS program, therefore a model for the capacitor is built up as illustrated in section 2.1.2.2 chapter 2 The model is consist of series connection of capacitance, parasitic inductance and Equivalent Series Resistance (ESR). The parasitic inductance for the capacitors was not specified in the application note. To estimate the parasitic inductance utilizes the ATC given S-parameter. The file with the S-parameter was downloaded from [31] and inserted in ADS in S2P data-element1. Plot of the admittance Y11=g11+jb11 [4, p.12] is shown in Figure 85.

2 4 6 80 10

0.2

0.4

0.6

0.8

0.0

1.0

f (GHz)

ab

s(Y

11

)

m1

m1freq=B=0.936

6.000GHz

1 2 3 4 5 6 7 8 90 10

-100

0

100

-200

200

f (GHz)

Pha

se (

Y1,

1)

m3

m3freq=phas=-166.391

6.000GHz

Figure 85 The magnitude of Y11 (left) and the phase of Y11 (right) for 3.9pF capacitor.

From resonance frequency Eq. (3) section 2.1.2 the series inductance is calculated as

( )[pH

CfLS 180

109.310621

)2(1

12292 =⋅⋅⋅⋅

=⋅

=−ππ

]

(86)

1 The simulation set-up is in the appendix H.


The same method is utilized for the all capacitors of Figure 74 and Figure 75 and the values are written in Table 3.

Input circuit capacitors [pF] Parasitic inductance [pH] 270 65 15 73 3.9 180 33 59.2 39 63.4 27 61 100 70

Output circuit capacitors [pF] Parasitic inductance [pH] 10 90.7 18 79.7 7.5 140 5.6 125

Table 3 Parasitic inductance of the capacitors. The models for ATC capacitors, which we have constructed, have low parasitic inductance they are less than 1nH. A normal rule of thumb states that this size of capacitor has inductance around 1 nH, but this is the only method we have to find the parasitic inductance. Concerning series resistance, Figure 86 shows curve for Equivalent Series Resistance. The value of capacitors and associated ESR is stated in Table 4.

Figure 86 The Equivalent Series Resistance [30].


Input circuit capacitors [pF] ESR [Ω]

270 0.04 15 0.07 3.9 0.09 33 0.04 39 0.04 27 0.04 100 0.02

Output circuit capacitors [pF] ESR [Ω]10 0.06 18 0.04 5.6 0.07 7.5 0.06

Table 4 ESR values. From Table 3 and Table 4 we can construct the model for all the capacitors in the matching circuits.


4.2.3 DC-Block Capacitors For DC-block capacitors of 270pF the self-resonance is 3.9GHz. Under this value the capacitor behaves as a capacitor. It has a reactance at a lowest frequency (392MHz) is given by

[ ]Ω=⋅⋅⋅

=⋅

= − 5.110270103922

12

1126ππ Cf

X L (87)


4.3 Simulation With The Real Components Table 3 and Table 4 are used to make the model for the capacitors. As an example, the model for the DC-block is

270pF 65pH 0.04Ohm

Similarly for all the capacitors as it is shown in Figure 87 and Figure 88. The set-up in Figure 73 section 3.6 is used with input and output-matching in Figure 87 and Figure 88 respectively and 0.5µH RF-choke. The set-up is simulated with the same input power of 200mW and gate-source voltage VGS of 3.7V, which gives quiescent drain current Id0 of 400mA. It should be mentioned that the length of the transmission lines are optimised.

R

R2R=0.07 Ohm

LL6

R=L=73 pH

RR1

R=0.04 Ohm

LL7

R=L=65 pH

C

C32C=15 pF

CC31C=270 pF

PortP1Num=1

MLINTL4


MLINTL8

L=6.9 mmW=7 mmSubst="MSub1"

MSTEPStep1

W2=7 mmW1=2.8 mm

Subst="MSub1"

PortP2Num=2

R

R7R=0.02 Ohm

L

L1

R=L=70 pH

C

C30C=100 pF

MLINTL7


R

R6R=0.04 Ohm

C

C28C=27 pF

MLINTL11


LL2

R=L=60 pH

MLINTL5


CC33

C=39 pF

R

R5R=0.04 Ohm

CC22

C=33 pF

R

R4R=0.04 Ohm

LL4

R=L=59 pH

LL3

R=L=63 pH

MLIN

TL9


L

L5

R=L=180 pH

MLINTL10

L=12 mmW=2.8 mm

Subst="MSub1"

RR3

R=0.09 Ohm

CC23

C=3.9 pF

Figure 87 Input circuit with parasitic elements.

RR6R=0.06 Ohm

RR7R=0.07 Ohm

R

R3R=0.04 Ohm

LL5

R=L=125 pH

LL4

R=L=140 pH

LL1

R=L=79 pH

C

C35C=5.6 pF

CC36

C=7.5 pF

CC33C=18 pF

LL3

R=L=90.7 pH

LL2

R=L=90.7 pH

RR1R=0.04 Ohm

LL6

R=L=65 pH

RR5R=0.08 Ohm

C

C25C=10 pF

R

R4R=0.08 Ohm

CC30C=10 pF

MLINTL4

L=7.50039 mmW=7 mmSubst="MSub1" MLIN

TL1

L=7.5 mm


MLIN

TL8

L=8.9 mm


MLIN

TL6

L=26 mm


MLINTL10


MLINTL9


CC32C=270 pF

Port

P2Num=2

MSTEPStep1

W2=2.5 mmW1=7 mm

Subst="MSub1"

Port

P1Num=1

Figure 88 Output circuit with parasitic elements.


The final length of transmission lines and the capacitors values are listed in Table 5. The width of the input and the output of the transmission lines are 2.8mm and 2.5mm respectively.

Input circuit components

C31, 270 [pF] TL10, 12 [mm]C32, 15 [pF] TL9, 14.5 [mm]C23, 3.9 [pF] TL5, 11.3 [mm]C22, 33 [pF] TL11, 14 [mm]C33, 39 [pF] TL7, 14 [mm]C28, 27 [pF] TL4, 2.7 [mm]C30, 100 [pF] TL8, 6.9 [mm]

Output circuit components C32, 270 [pF] TL4, 7.5 [mm] C33, 18 [pF] TL1, 7.5 [mm] C30, 10 [pF] TL9, 3 [mm] C25, 10 [pF] TL8, 8.9 [mm] C36, 7.5 [pF] TL6, 26 [mm] C35, 5.6 [pF] TL10, 17 [mm]

Table 5 The components values of Figure 87 and Figure 88. The configuration is simulated and the gain and the input return loss is shown in Figure 89.

3.9E8

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.8E8

4.8E8

-10

0

10

20

-20

30

dB(S

(1,1

))

m3m4dB(S

(2,1

))


4.680E8m4LSSP_freq=dB(S(1,1))=-8.006

3.900E8

f [MHz]

Figure 89 Gain (S21) and input return loss (S11).


The output average power is represented in Figure 90.

3.9

E8

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.8

E8

4.8

E8

24

26

28

30

32

34

22

36

f [MHz]

Ave

rag

e p

ow

er

[W]


The drain characteristic is in Figure 91.

3.9

E8

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.8

E8

4.8

E8

2.4

2.6

2.8

2.2

3.0

f [MHz]

ID [

A]

Figure 91 Drain current as a function of frequency.

The efficiency of the amplifier is illustrated in Figure 92.

3.9

E8

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.8

E8

4.8

E8

40

42

44

46

38

48

f [MHz]

Eff

icie

ncy

%



Phase characteristic and group delay is in Figure 93 Figure 94.

3.9E8

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.8E8

4.8E8

-200

-150

-100

-50

-250

0

f [MHz]

Deg

ree

[C]

Figure 93 Phase characteristic.

3.9E8

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.8E8

4.8E8

2.2E-6

2.3E-6

2.4E-6

2.1E-6

2.5E-6

f [MHz]

Tim

e [s

ec]


The second harmonic is investigated and the result is in Figure 95.

3.9E8

4.0E8

4.1E8

4.2E8

4.3E8

4.4E8

4.5E8

4.6E8

4.7E8

3.8E8

4.8E8

10

20

30

0

40

dB

(vo

ut[

::,1

])d

B(v

ou

t[::

,2])

f [MHz]

Figure 95 The second harmonic.


The stability characteristic of the power amplifier is shown in Figure 96.

50 100 150 200 250 300 350 400 4500 500

-40

-20

0

20

40

-60

60

Time [nsec]

Vou

t [V

]



Sub-Conclusion In this section we simulate the final set-up with the real components. The output characteristics are changed in spite of the low values of the parasitic and ESR. It shows the influence of the parasitic on the output characteristics. However, all the performances are acceptable.


4.4 Layout The layout construction is based on the result on section 4.3 (Table 5) by using ADS program. The layout is split in two sections, input and output sections as shown Figure 97 and Figure 98. The microstrip is made of copper with 35µm thickness and the dielectric of FR4 glass fibber with 1.55mm thickness and grounded on the other side.

VGS

Ground

SMA

Ground

Figure 97 Input section, scale 1:1.

RF-choke

VDS

Ground

SMA

Ground

Figure 98 Output section, scale 1:1. RF-choke is not on the layout. 50 Ω SMA connector is mounted at the input and output of the power amplifier. The components sizes are in Table 6.


Components at the VDS Size 10µf 73430.1µf 06031.2pf 0603150pf 1210

Components at the VGS Size 160pf 06030.1µf 06031.2pf 060310µf 734333kΩ 060347nH 0603150pf 1210

Capacitors input and output matching circuits

Size

ATC B Series capacitors 1210Table 6 Components size.

Ground The ideal ground plane is a zero potential. There is no potential between the points in an ideal ground. The ideal ground plane cannot be built it can only be approximated. The multipoint grounding is most effective for our design. So the 10mm width, which is labelled ground, is the ground of the power amplifier. We make multi connections between the topside and the bottom side of the board.


4.5 Heatsink The transistor has a shape as shown in Figure 99. To mount the transistor directly on the heatsink would be impractical. A brass is therefore cut with dimensions matching the transistor case as it is shown in Figure 100. In this case we can change the heatsink if we want.

Figure 99 Case 360B, style 1 NI.360 MRF373ALR1 [26].

Figure 100 Brass structure (156×53mm) between the transistor and the heatsink.

To calculate thermal resistance, the Eq. (68) section 2.9 is used

[ ]CPTT oJAAJ θ=− (88)

where [ ]WCo

SABSCBJCJA /θθθθθ +++= (89)

where θJC [oC/W] is the thermal resistance, junction to case. θCB [oC/W] is the thermal resistance, case to brass. θBS [oC/W] is the thermal resistance, brass to sink. θSA [oC/W] is the thermal resistance, sink to ambient.


Calculating the thermal resistances θCB and θBS are complicate. We assume there is no temperature difference between the case and the brass and between the brass and the sink, therefore they are assumed to be zero. The heatsink is calculated from the maximum power dissipation in the transistor. We use the simulation results from section 4.3 to calculate the heatsink. The battery power is simulated by using Eq. (15) section 2.2.2

[ ]WVIP dcdcbat ⋅= (90)

where Idc is from the simulating result in Figure 91. Vdc is the power supply equal to 28V.

3.9

E8

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.8

E8

4.8

E8

65

70

75

80

60

85

f [MHz]

Ba

tte

ry p

ow

er

[W]

Figure 101 The battery power.

The power dissipation simulation is based on Eq. (11) section 2.2.1

[ ]WPPPP inoutbattrans )( +−= (91)

where Pin = 200 [mW]. Pout is from the result in Figure 90.


3.9

E8

4.0

E8

4.1

E8

4.2

E8

4.3

E8

4.4

E8

4.5

E8

4.6

E8

4.7

E8

3.8

E8

4.8

E8

40

42

44

46

38

48

f [MHz]

Po

we

r d

issi

pa

tion

[W

] m7

m7LSSP_freq=P_trans=46.318

4.410E8

Figure 102 The power dissipation in the transistor.

To calculate the required heatsink Eqs. (88) and (89) are used

[ ]WCP

TT oBSCBJC

trans

AJSA /)(max θθθθ ++−

−≤ (92)

[ ]WCoSA /88.2)0089.0(

318.4625200

=++−−

≤θ (93)

where Ptrans = 46.318 [W] is from Figure 102. θJC = 0.89 [oC/W] is from the datasheet of the transistor [26]. TJmax = 200 [oC] is from the datasheet of the transistor [26]. TA = 25 [oC] is the ambient temperature. From [27] the dimension of the heatsink belongs to this thermal resistance can be found. In the EMI department at Ørsted•DTU, a heatsink with 0.54 oC/W thermal resistance is available. With 0.54 oC/W, the maximum junction temperature TJmax will be

( )[ CT

PTTo

J

SAJCtransAJ

91)54.089.0(318.4625max

max

=+⋅+=

++= θθ

] (94)

This means that with this big heatsink we have built a margin of safety and compensated for the other thermal resistances (θCB and θBS).


4.6 Mounting Recommendations The LDMOS transistor is sensitive to damage from electrostatic charge [26], therefore the iron soldering should be grounded. The heatsink should be flat and a thermal compound is recommended with a thin layer. The compound reduces the thermal resistance between the two surfaces.

RF-Power Amplifier Test 110

Chapter 5

RF-Power Amplifier Test In this chapter the test of the power amplifier will be carried out. The test will be compared with the simulation results in section 4.3 chapter 4. First we will find the DC-bias point. Second the power amplifier is tested with the signal generator. Finally, the power amplifier is tested with the driver amplifier. The test instruments are listed in appendix I and the Matlab codes for the figures are in appendix J.


5.1 DC-Bias The power amplifier should be terminated with 50Ω on both input and output before the DC-bias point is adjusted. This is to avoid damage to the transistor. If the power amplifier is not terminated and the transistor is not stable, then all the power will reflect back to the transistor and damage the transistor. Therefore the termination must be taken into consideration. The drain-source voltage VDS must be 28V and the gate-source voltage VGS is adjusted to give a drain current of 400mA. For a given transistor, the gate-source voltage VGS of 3.68V will give drain current of 400mA. Ideally, the gate current is zero, but the test gives 108µA, which is within acceptable range. The power amplifier is then connected to the spectrum analyzer to test the stability of the power amplifier with the specified DC-bias. The block diagram is shown in Figure 103.

Termination 50Ω

Power supply

Power supply

DUT

Spectrum analyzer

Input port Output port

RF IN

Figure 103 Block diagram of stability test. The input port of the power amplifier is terminated with 50Ω. The output of the power amplifier (DUT) is connected to the spectrum analyzer through an attenuator and a DC-block. The attenuator and the DC-block are put in to avoid damage of the instrument. The maximum RF-input power of the spectrum analyzer is 1W (30dBm). The test was carried out and there were no oscillations noticed in the whole frequency band. That means the power amplifier is stable with the specified bias point and without input power.


5.2 Test The Power Amplifier With The Signal Generator The power amplifier is driven with the input power by signal generator. It was interesting to see if there was amplification. The block diagram for this set-up is shown in Figure 104. The maximum output power from the signal generator is +20dBm.

DUT

Spectrum analyzer


Power supply

Power supply

Signal generator

Figure 104 Block diagram of the test set-up.

The signal generator is set to 0dBm and read 10 points on the spectrum analyzer from 392MHz to 482MHz. The simulator is also run with 0dBm.The points from the simulator and the test are plotted by using Matlab program as it is shown in Figure 105. Similarly, the tests are run with +10dBm and +20dBm and the results for +10dBm and +20dBm in Figure 106.


Figure 105 Output power amplifier with 0dBm input power.

Figure 106 Output power amplifier with +10dBm input power (left) and +20dBm input power (right).

Clearly, the amplifier is not amplifying the signal. The signal is attenuated totally. The reason is the matching networks are not matching the source and the load properly to the input and the output of the transistor.


5.3 Input Reflection Coefficient (S11) Test The directional coupler can be used to test the input reflection coefficient. The block diagram for the test set-up is seen in Figure 107. The directional coupler is connected at the input of the power amplifier. The reflected signal is attenuated 20dB and can be read at the spectrum analyzer. In dB, the deference between the reflected signal and the incident signal is the input reflection coefficient (S11). In the same way, 10 points from the simulator and the test at 0dBm input power are plotted in Matlab program. The result is illustrated in Figure 108.

Spectrum analyzer

Signal generator

Power supply

Power supply

Input port

DUT

Output port

Termination 50Ω

-20dB

Termination 50Ω

Test port

Directional coupler

Figure 107 Block diagram to test S11.


Figure 108 Input reflection coefficient of the simulation and the test.

Figure 108 shows the input reflection coefficient is close to zero in the whole frequency band. That means almost all the incident power is reflected. That is the reason why we do not have any amplification.


Adjusting The Input Reflection Coefficient (S11) There are two ways to adjust the reflect coefficient, the capacitors values and the length of the transmission lines. The length of the transmission lines can be adjusted by changing the position of the capacitors. Both the input and output-matching networks have influence on the input reflection coefficient. Therefore the input and the output circuits are adjusted. To adjust the input reflection coefficient require a considerable a mount of work. Every time the capacitor value or the position was changed the test was carried out to measure the input reflection coefficient in the whole frequency band. The input power is set to 0dBm and the capacitors values and the transmission lines were adjusted until the input reflection coefficient has the characteristic close to the characteristic in the simulation. The signal generator is set to 0dBm in order to not to strain the transistor. The result is shown in Figure 109.

Figure 109 The adjusted S11.

Figure 109 shows input reflection coefficient of the test and the simulation of 0dBm input power. The test result is not so close to the simulation, but it has improved compared with the Figure 108. In Table 7, the capacitors values and the length of the transmission lines after the adjusting are written.


Simulation value Test value Input circuit Input circuit

C32, 15 [pF] C32, 18 [pF] C23, 3.9 [pF] C23, 3.9 [pF] C22, 33 [pF] C22, 47 [pF] C33, 39 [pF] C33, 30 [pF] C28, 27 [pF] C28, 30 [pF] C30, 100 [pF] C30, 30 [pF] C31, 270 [pF] C31, 270 [pF]

TL10, 12 [mm] TL10, 7.3 [mm] TL9, 14.5 [mm] TL9, 13.8 [mm] TL5, 11.3 [mm] TL5, 15 [mm] TL11, 14 [mm] TL11, 17.5 [mm]TL7, 14 [mm] TL7, 9.1 [mm]TL4, 2.7 [mm] TL4, 3.4 [mm]TL8, 6.9 [mm] TL8, 6.9 [mm]

Simulation value Test value Output circuit Output circuit C33, 18 [pF] C33, 15 [pF] C30, 10 [pF] C30, 24 [pF] C25, 10 [pF] C25, 20 [pF] C36, 7.5 [pF] C36, 10 [pF] C35, 5.6 [pF] C35, 5.6 [pF] C32, 270 [pF] C32, 270 [pF]

TL4, 7.5 [mm] TL4, 7.5 [mm] TL1, 7.5 [mm] TL1, 7.5 [mm] TL9, 3 [mm] TL9, 4 [mm] TL8, 8.9 [mm] TL8, 9.5 [mm] TL6, 26 [mm] TL6, 15.8 [mm] TL10, 17 [mm] TL10, 25.6 [mm]

Table 7 The adjusted capacitors and the transmission lines. From Table 7 we can see the difference between the value of the components from the simulation and the test. It is mentioned in section 3.5 that the input impedance of the power transistor is changed with the input power. To see this change the power amplifier is again driven with +10dBm and +20dBm and the input reflection coefficient is measured. Figure 110 and Figure 111 show the input reflection coefficient of the simulation and the test with +10dBm and +20dBm respectively.


Figure 110 Input reflection coefficient with +10dBm input power.

Figure 111 Input reflection coefficient with +20dBm input power.


If we put the curves for the input reflection coefficient altogether can we better notice the change of the input impedance of the transistor. Figure 112 illustrates the input reflection coefficient of the power amplifier driven by 0dBm, +10dBm and +20dBm.

Figure 112 The measured values of S11 for the power amplifier, which driven with 0dBm, +10dBm and

+20dBm.


5.4 Power Amplifier With The Modified S11 Test The power amplifier is tested again after the input reflection coefficient is adjusted. The block diagram for this test is the same as in Figure 104. The signal generator is set to 0dBm, +10dBm and +20dBm and the test is performed and the results are shown in Figure 113, Figure 114 and Figure 115, respectively.

Figure 113 Output power amplifier of 0dBm input power.


Figure 114 Output power amplifier of +10dBm input power.

Figure 115 Output power amplifier of +20dBm input power.

The test result shows the power amplifier does not give the desirable output power. To get better result we need more capacitors values and the procedure takes too much time. To save the time and to get a good result we use trimmer capacitors instead of ATC capacitors.


5.5 Trimmer Capacitors Utilizing The trimmer capacitors should handle high power. In the EMI institute, there are trimmer capacitors called Arco variable capacitors. Arco capacitors have the capability to handle high power. The capacitors are very old and we do not have information about how much power they can handle, but they are for RF-applications. The adjusting was carried out by changing some of the ATC capacitors with the trimmer capacitors. The trimmer capacitors are adjusted and the positions changed. The power amplifier is shown in Figure 116.

Figure 116 The power amplifier. The test result of +20dBm input power is shown in Figure 117. From Figure 117 it can be ascertained that the input power of +20dBm is not enough to drive the power amplifier with full power.


Figure 117 The Output power of the power amplifier of Figure 116.

It was not possible to get a signal generator that can give more than +20dBm, therefore the driver amplifier should be constructed.


5.6 RF-Driver Amplifier The main purpose of the driver is to deliver more power to the power amplifier than the signal generator can deliver. The specifications of the driver should be

− Output power up to 1W (30dBm). − The driver should works at frequency between 392.5MHz and 477.5MHz. − The input and output-impedance of 50 Ohm at the whole frequency band.

The most critical point in the specifications is the (working) frequency. The driver amplifier, which fits the specifications best, is found from [28] with the following features

− Broadband operation. − 250MHz to 4000MHz working frequency. − RF-output power of 31dBm. − High efficiency.

The problem with this driver is the lack of application notes. There are three schematics diagram of 900MHz, 1900MHz and 2140MHz and besides, there are no S-parameters or a model of the transistor that can be downloaded. That means, if we want the driver to fulfil our specifications, the input and output-matching circuits should be constructed. We took the schematic of 900MHz, as it is shown in Figure 118, as a starting point 1. For this schematic, the DC-block C1 and C2 are 1000pF, C4 is 7pF and C8 is 8.2pF. 1 The layout of the driver is in appendix K.


Figure 118 900MHz schematic [28].


The test set-up of the driver is shown in Figure 119. The driver runs off a single +5V power supply and typically draws 420mA.

DUT

Spectrum analyzer


Power supply

Signal generator

Figure 119 Test set-up for the driver amplifier.

We change the capacitors C1 and C2 with a value of 270pF. The capacitors C4 and C8 are adjusted to get the desired output power. The output power should be as flat as possible in the frequency band. The values of C4 and C8 are set to 7.5pF and 9.1pF respectively. With these capacitors values the output power of the driver is shown in Figure 120.

Figure 120 Output power of the driver amplifier.

Figure 120 shows we can get more than +25dBm output power if it is driven with +20dBm input power.


5.7 RF-Power Amplifier With RF-Driver Amplifier Test The test set-up of Figure 104 is used to test the power amplifier. A single and separate power supply to the driver is used in the test, which is not in the block diagram. The output power of the power amplifier is shown in Figure 121. Figure 121 shows the output power of the power amplifier is close to the specifications, but the power amplifier is unstable.

Figure 121 Output power amplifier.

On the spectrum analyzer we have seen the phenomenon like in Figure 122, which indicates the instability.


Figure 122 Output power amplifier.

There are two possibilities for instability. First, the output impedance of the driver is not perfectly matched to 50Ω and second, the power amplifier is become unstable when it is driven by high input power. To find out what the problem is, we make several tests on the driver alone and together with the power amplifier.


5.7.1 RF-Driver Amplifier Test Before we check the output impedance of the driver we make a simple test, which we compare +20dBm from the signal generator and +20dBm from the driver. In section 5.5 we tested the power amplifier with the signal generator of +20dBm.The output power of the test is in Figure 117 and the power amplifier was stable. Now we connect the driver to the signal generator and adjust the signal generator such that we get +20dBm output power from the driver. There is a bottom in the signal generator that we can adjust the output of the signal generator. The driver (of +20dBm output power) is then connected to the power amplifier. The test is carried out and the power amplifier is still unstable. This is a first indication that the driver output impedance is not broadband match to 50Ω.


5.7.2 Output Impedance Of The Driver We investigate the first possibility. The network analyzer is used to test the output impedance of the driver. The test set-up is shown in Figure 123.

DUT

Network analyzer


Power supply

Termination 50Ω

Figure 123 Output reflection coefficient test set-up.

The input port of the driver is terminated with 50Ω. The network analyzer must first be calibrated before the driver is connected. The output reflection coefficient (S22) was measured in the whole frequency band and it is shown in Figure 124.

Figure 124 Output reflection coefficient (S22).


Clearly the output impedance is not good matched to 50Ω. A good match is the S22 should be very low. One way to make it match to 50Ω is to modify the output matching circuit of the driver. We start to read the output impedance value at the center frequency (435MHz) in the network analyzer. Then the output impedance is plotted in the Smith Chart program. From this point we add a parallel coil and then series capacitor as is shown in Figure 125.

Figure 125 The output impedance and the equivalent circuit. ZL is the output impedance of the driver.


The modification is obviously a small band solution. The output reflection coefficient of the driver was tested again and the result is shown in Figure 126.

Figure 126 The modified input reflection coefficient of the driver.

The result is, as expected a small band match, but it is better matched to 50Ω. The output power of the modified driver is shown in Figure 127. As we can see that the output of the driver is not flat.


Figure 127 Output driver amplifier.

The modified driver amplifier is seen in Figure 128.

Figure 128 The driver amplifier.

The modified driver is then connected again to the power amplifier and tested. The test is carried out and the power amplifier is still unstable. There is another way to bring the output impedance of the driver amplifier close to the input impedance of the power amplifier. The attenuator, which explained in section 2.4, can be used as a matching circuit with attenuation.


5.7.3 Attenuator Utilization We connect a variable attenuator between the output of the driver and the input of the power amplifier. The test is carried out and it is indicated that the 3dB attenuator makes the power amplifier stable. With this test the power amplifier is stable but with attenuation. We could not get the desire power even if we tuned the input and output-matching circuits. We mentioned in 5.7 at there are two possibilities of instability, the output impedance of the driver and the power amplifier it self. We will in the next section investigate the power amplifier.


5.7.4 RF-Choke And Grounding Of The Power Amplifier The inductor, which is mounted at the output side of the power amplifier, is a bout 0.5µH. We changed this inductor to the value less than 0.5µH to see if it has influence on the stability. The inductor value is reduced to 0.1µH by using the same technique as in section 4.1. After the inductor value is changed, the test result indicates that the power amplifier is still unstable. The inductor does not have influence on the stability. The ground is investigated, but without any improvements.


Sub-Conclusion We have seen that the power amplifier is stable without input power, which satisfies the specification. It was a big difference between the simulation result and the test result of the output power as it is shown in Figure 105 and Figure 106. This is because the grounding and parasitic reactance occurs from the soldering and the capacitors. The input reflection coefficient should be modified before we could get amplification, as illustrated in Figure 113, Figure 114 and Figure 115. It was difficult to obtain high amplification without trimmer. With ATC capacitors we obtained output power of 32dBm, see Figure 115. With trimmer capacitors we could get up to 39.5dBm. We used driver amplifier to deliver more than +20dBm to the power amplifier. When the driver was connected to the power amplifier the output power of 35W (45.44dBm) was obtained, as it is shown in Figure 121, but the power amplifier was unstable. We made several tests to specify the instability problem:

1. We tested the power amplifier with input power of +20dBm from the signal generator and the result showed that the power amplifier was stable. We tested the power amplifier with input power of +20dBm from the driver amplifier; the result was the power amplifier was unstable.

2. Output impedance of the driver amplifier is investigated and it was not broadband

match to 50Ω, see Figure 124. The output impedance is improved, but still small band match, as it is shown in Figure 126. The test is carried out, but the instability maintained.

3. We used two-port attenuator device and the power amplifier was stable, but with

attenuation we could not get the desire output power.

4. The RF-choke value is reduced from 0.5µH to 0.1µH and the ground was investigated, but the power amplifier was unstable.

From these tests we can conclude that the mismatch between the output impedance of the driver and the input impedance of the power amplifier cause the instability. As long as the power amplifier is unstable we cannot make the efficiency test and the other tests.

Conclusion 137

Conclusion In this project the broadband RF-power amplifier is constructed, simulated, implemented and tested. The power amplifier must give an output average power of 35W. The stability and the linear phase as well as the output power should be maintained in the frequency band from 392MHz to 478MHz at the center frequency of 435MHz. The power amplifier is a part of P-Band Ice Sounding Radar front-end. The basic parameter and fundamental principles of the electrical components are summarized. The theory of a simplified structure of a power amplifier is considered. S-parameters utilizations for small-signal power amplifier stability are detailed. Matching network technique for the broadband applications is presented. The lumped element to transmission line transformation calculation is detailed. Power handling capability of the various parts of the power amplifier is illustrated and the heatsink dimension calculation is demonstrated as well. MRF373A LDMOS power MOSFET transistor is chosen for designing the power amplifier. A basic configuration of common-source single-stage and DC-bias network is selected from the datasheet. Input and output-matching networks with the lumped elements are constructed on the basis of the simulated input and output impedances of the transistor. Small band characteristics are obtained with a few elements of capacitors and inductors. The bandwidth is enhanced with several elements and the desire specifications are achieved. Input return loss is10dB and 8dB at the ends of the bandwidth. A flat power gain of 25.4dB. Output power of 35W, drain efficiency of 52% and the linear phase additionally obtained. The power amplifier is stabilized after 250nsec. Negative feedback is connected to the power amplifier. The desirable properties such as input return loss, output power and the bandwidth are obtained. These characteristics are attained at the expense of a reduction in gain and degradation of the stability and the efficiency. Input return loss is raised, especially at the extremities of the bandwidth, with around 5dB. The gain is reduced 3.6dB. The efficiency of 47% and the power amplifier is stabilized after 600nsec. In view of the gain, efficiency and the stability the feedback is not implemented in the final set-up. Values of the inductors did not exist; therefore a microstrip lines are used. The input matching network of the final set-up of an ideal components is 68.2mm length with 6 capacitors connected to the ground. Output matching network is 60.8mm with 5 capacitors. All simulation results of the set-up are satisfied. With input power of 200mW the output power of 35W with 1dB ripple is obtained. Input return loss is around 13dB and 8dB at the extremities of the bandwidth. The drain efficiency is about 44% and the phase is a linear in the entire frequency band as well as the stability is achieved after 200nsec. The final set-up is then simulated with the model of the capacitors. The output characteristics are changed even if the parasitic are all very low. However, the desired output is achieved.

Conclusion 138

Power amplifier is implemented on FR4 board of glass fibber. The ATC 100 B series multiplayer ceramic capacitors are chosen due to their performance such as high self-resonance, low noise and low ESR. Following the calculations of thermal resistance we should use a heatsink that has a thermal resistance of 2.88 oC/W. We used a heatsink has a thermal resistance equal to 0.54 oC/W. This big heatsink gave us a margin of safety. The power amplifier runs off 28V power supply and biased with gate-source voltage VGS of 3.68V give drain current equal to 400mA. With this bias point the power amplifier was stable. Signal generator derived the power amplifier and there was no amplification. The test is carried out with 0dB, +10dB and +20dB. The input reflection coefficient of the power amplifier is tested with directional coupler and it was a bout -1dB. With the change of values of the capacitors and their positions the input reflection coefficient is improved from –1dB to around –7dB. The signal generator again derived the power amplifier. With the maximum input power of +20dBm we obtained output power gain around 10dB. We could not achieve the desire output power with the ATC capacitors. Arco trimmer capacitors are utilized instead of some of the ATC capacitors. The trimmers were adjusted and positions changed. With this configuration and input power of +20dBm we got output power approximately +39.5dBm. The simulator run also with input power of +20dBm and it was about +3dB greater than the test. Because of the maximum output power of the signal generator is +20dBm, the RF-driver amplifier is constructed. It was not possible to find a driver matched to 50Ω and working at frequency band from 392MHz to 478MHz. The one we found and implemented is working at around 900MHz, therefore the input and output-matching circuits of the driver are changed to obtain the desire output power in the frequency range. The modified driver amplifier with the output power of +26dBm is connected to the power amplifier. The output power of 35W was achieved, but the power amplifier was unstable. We made four tests to specify the problem:

- Signal generator with output power of +20dBm is derived the power amplifier and the power amplifier was stable. We connect the driver with +20dBm output power to the power amplifier and the test displayed the power amplifier was unstable.

− The output impedance of the driver is investigated and appeared a small band

matched to 50Ω. Output matching circuit of the driver is improved, but still small band matched. The driver is connected again to the power amplifier and tested. The power amplifier still unstable.

Conclusion 139

- A variable attenuator is utilized and connected between the driver and the power

amplifier. The test result displayed the power amplifier was stable, but with attenuation we could not get the desirable output power.

- The RF-choke value is reduced from 0.5µH to 0.1µH but the effort was failed, the

power amplifier was unstable. Form these four tests we can conclude that the output impedance of the driver is not broadband matched to 50Ω. The mismatch between the output impedance of the driver amplifier and the input impedance of the power amplifier causes the instability. To obtain 35W output power and stable power amplifier, we need RF-driver amplifier matched to 50 in the frequency band from 392MHz to 478MHz. The driver should deliver output power of maximum 30dBm. In addition to that when the all parts of the front-end are constructed, the radiation problem should be taken into consideration. All parts of the front-end should be isolated from each other.

140

References [1] A. S. Sedra / K. C. Smith, Microelectronic Circuit., 4th ed, Oxford.1998. [2] J. Vidkjær, Chapter V, Power and Nonlinear RF-Amplifiers, Class notes, 31415 RF- Communication Circuits Autumn 2003. [3] David A. Johns, Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997. [4] J. Vidkjær, Chapter II, RF –Circuits, Class notes, 31415 RF-Communication Circuits Autumn 2003. [5] Steve C. Cripps, RF Power Amplifiers for Wireless Communications, Artech House, Inc.1999. [6] Thomas H. Lee, The design of CMOS radio-frequency integrated circuits, 2nd ed, Cambridge 2004. [7] David M. Pozar, Microwave Engineering,2nd ed, John Wiley & sons, Inc.1998. [8] Guillermo Gonzalez, Microwave Transistor Amplifiers Analysis and design, 2nded, Prentice-Hall, Inc.1997. [9] J. Vidkjær, Linear Active Two-Ports, Class notes, 31415 RF-Communication Circuits Autumn 2005. [10] J. Vidkjær, Chapter V, Oscillators, Class notes, 31415 RF-Communication Circuits Autumn 2003. [11] Edward C. Jordan, Reference Data for Engineers: Radio, Electronics, Computer, and Communications,7thed, Howard W. Sams & Co., Inc. 1985. [12] Peter A. Rizzi, Microwave Engineering Passive Circuits, Prentice-Hall, Inc.1988. [13] Reinmut K. Hoffmann, Handbook of Microwave Integrated Circuits, Artech House, Inc. 1987. [14] K. C. Gupta, Ramesh Garg, I.J.Bahl, Microstrip Lines and Slotlines, Artech 1979. [15] T. C. Edwards, Foundations For Microstrip Circuit Design, John Wiley & Sons 1981. [16] Stephen A. Mass, Nonlinear Microwave and RF Circuits, Artech house, Inc.2003.

141

[17] Jørgen Dall, Electromagnetic Systems Section (EMI), Ørsted•DTU. [18] http://www.hills2.u-net.com/electron/induct.htm, Basics of Inductors. [19] https://www.avx.com/docs/catalogs/micintro.pdf, Introduction to Microwave Capacitors. [20] http://www.mitsubishichips.com, Mitsubishi RF power module, RA07H4047M. [21] www.atceramics.com, RF Ceramic Chip Capacitors in High RF Power Applications. [22] Motorola, RF Power device impedances: Practical Considerations, AN1526. [23] Google / An introduction to the Air cored Coil. [24] Google / Approximate Air Coil Inductance Calculator. [25] www.freescale.com, Mounting Recommendations for Copper Tungsten Flanged Transistors, AN1617. [26] www.freescale.com, MRF373ALR1 Technical Data. [27] Farnell In One, Elektronik-komponenter & Måleudstyr, 1, 2005. [28] http://www.tycoelectronics.com, RF Driver Amplifier, MAAMSS0050. [29] www.bungard.de, Technical data standard for RF4 substrate.

[30] www.atceramics.com, ATC 100 B Series Porcelain Superchip Multilayer Capacitors. [31] http://www.atceramics.com/designsupport/index.asp. Software Microsoft Word 2000. Fritz Dellsperger, Juerg Tschirren and Roger Wetzel, Software for Easy Circuit, Design with Smith Chart V 1.9. Agilent Technologies, Advanced Design System 2004A, 1983-2004. MATLAB Version 6.5.0.180913a Release 13 June 18, 2002.

http://www.hills2.u-net.com/electron/induct.htm

https://www.avx.com/docs/catalogs/micintro.pdf

http://www.mitsubishichips.com/

http://www.atceramics.com/

http://www.freescale.com/

http://www.freescale.com/

http://www.tycoelectronics.com/

http://www.bungard.de/

http://www.atceramics.com/

http://www.atceramics.com/designsupport/index.asp

Appendix A 142

Appendix A: Calculations Of The Stability Circles Output stability circle with a center CL and radius RL [7, p. 613]

2222

2112

2222

**1122 )(

∆−=

∆−

∆−=

SSSR

SSS

C

L

L

(95)

Input stability circle with a center Cs and radius Rs

2211

2112

2211

**2211 )(

∆−=

∆−

∆−=

SSSR

SSS

C

S

S

(96)

where

21122211 SSSS −=∆ (97)

Appendix B 143

Appendix B:

The Short And Open-Circuited Line The Short-Circuited Line The input impedance of a lossless shorted line is [12, p. 90]

][tan0 Ω== lβjZjXZ inin (98)

where Z0 [Ω] is the characteristic impedance of the line. β [rad/m] is the phase constant, see appendix C. l [m] is the length of the line. The normalized input impedance is [12, p. 90]

][tan0

__Ω=== lβj

ZjX

XjZ ininin (99)

The normalized input reactance versus lβ can be shown in Figure 129.

Appendix B 144

Figure 129 Normalized input reactance versus [12, p. 91]. lβ

For lβ < π/2 ( < λ/4) the input impedance is inductive since the reactance is positive. l

The reactance Xin is [12, p. 91]

][Ω= LX in ω (100)

][tan0 HZX

L in lβωω

== (101)

Appendix B 145

The Open-Circuited Line The input impedance is given [12, p. 93]

][cot0 Ω−= lβjZZin (102) and the input admittance is

][tan10 SjYjB

ZY in

inin lβ=== (103)

the normalized input admittance is

][tan0

__Sj

YjB

BjY ininin lβ=== (104)

The normalized input susceptance Bin versus lβ is illustrated in Figure 130.

Figure 130 Normalized input susceptance versus [12, p. 94]. lβ

Appendix B 146

For lβ < π/2 ( < λ/4) the input is capacitive since the susceptance Bl in is positive. The susceptance Bin is given

][SCBin ω= (105)

where

][tan0 FY

C lβω

= (106)

Appendix C 147

Appendix C: Wave Propagation Calculation The velocity of light in free space is given [12, p.29]

[ smvRR

/1

00 εεµµ= ] (107)

[ smc /1

00εµ= ] (108)

where µR is a relative permeability. µR =1 is a relative permeability for free space. µ0 = 4π × 10-7 [H/m] is permeability of free space [12, p. 11]. εR is relative permittivity or dielectric constant. εR =1 is relative permittivity for free space. ε0 ≈ 1/36π × 10-9 [F/m] is permittivity of free space [12, p. 11].

[ smc /10310

361104

1 8

97

×≈×⋅×

=−−

ππ

] (109)

In the free-space v is equal to c. The velocity of wave in the isolator is given by [12, p. 31]

[ smcvRR

/εµ

= ] (110)

Appendix C 148

The wavelength in free space denoted by λ0 and calculated as

[ ]mfc

=0λ (111)

in the insulator is [12, p. 31]

[ ]mRRεµ

λλ 0= (112)

The phase constant is given by

[ mradv RR /2

0

µελ

]πωβ == (113)

Appendix D 149

Appendix D: Microstrip Power Handling Capability The rise in temperature per watt can be calculated from [14, p. 76]

[ WCfWWK

hT o

eff

d

eff

c /)(2

2303.0⎟⎟⎠

⎞⎜⎜⎝

⎛+=∆

αα ] (114)

where h [m] is the thickness of the substrate. K [W/mK] is the thermal conductivity of the substrate. αc [dB/m] is the attenuation coefficient due to loss in the conductor and can be calculated from Eq.(56) section 2.7.1.3. αd [dB/m] is the attenuation coefficient due to loss in the dielectric and can be calculated form Eq. (54) section 2.7.1.3. Weff (f) [m] is the effective width of the model in Figure 131 and it is given by [14, p.74]

][

1

)( 2 m

ff

WWWfW

p

effeff

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−+= (115)

where fp [Hz] is given by[15, p. 82]

][2

HzW

cfeeff

p ε= (116)

Weff [m] is the equivalent width of the strip in the model, and it is given by [15, p. 82]

Appendix D 150

][0

mZ

hWe

eff εη

= (117)

where η= 376.7 [Ω] is the characteristic impedance of free space [15, p. 82].

Figure 131 Model for microstrip [15, p. 81].

∆T can be calculated at the center frequency of 435MHz as

[ ]Ω⋅=⋅⋅

⋅⋅⋅⋅== −

−3

7

76

1043.510813.52

1041043522

ππσ

ωµosR (118)

[ mNpWZ

R

o

sc /04.0

105.23.541043.5

3

3

=⋅⋅

⋅== −

−

α ] (119)

[ ]mdBe c

c /347.0log20 == αα (120)

[ mradcfk /1.9

1031043522

8

6

0 = ]⋅

⋅⋅==

ππ (121)

[ mNpk

re

erod /114.0

)16.4(42.32015.0)142.3(6.41.9

)1(2tan)1(

=−⋅⋅−⋅⋅

=−

−=

εεδεε

α ] (122)

[ ]mdBe dd /99.0log20 == αα (123)

Appendix D 151

][1081.542.33.541055.17.376 3

3

0

mZ

hWe

eff−

−

⋅=⋅

⋅⋅==

εη (124)

][1096.1342.31081.52

1032

93

8

HzW

cfeeff

p ⋅=⋅⋅⋅

==−ε

(125)

[ ]mfW

m

ff

WWWfW

eff

p

effeff

32

9

6

3.33

2

108.5

1096.13104351

105.21081.5105.2)(

][

1

)(

−−−

− ⋅=

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅

⋅+

⋅−⋅+⋅=

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−+=

(126)

[ ]

[ ]WCT

T

WCfWWK

hT

o

o

eff

d

eff

c

/108.143108.52

99.01081.5

347.036.0

1055.12303.0

/)(2

2303.0

3

33

3

−

−−

−

⋅=∆

⎟⎠⎞

⎜⎝⎛

⋅⋅+

⋅⋅⋅

=∆

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⋅=∆

αα

(127)

where h = 1.55 × 10-3 [m] is given in [29]. µ0 = 4π ×10-7 [H/m] is the permeability of free-space [7, p. 704]. W = 2.5 ×10-3 [m] is the width of the microstrip line. Z0= 54.3 [Ω] is the impedance of the microstrip line and it is calculated by the Matlab code in appendix J.1, which is based on Eq. (48) section 2.7.1 c = 3 ×108 [m/s] is the velocity of light in free-space. tanδ =0.015 is the dielectric loss tangent and it is given in [29]. εr = 4.6 is the dielectric permittivity and it is given in [29]. εe =3.42 is the effective permittivity and it is calculated by Matlab code in appendix J.1. K= 0.36 [W/mK] is the thermal conductivity of the dielectric and it is given in [29]. σ =5.813×107 [S/m] is the conductivity of the copper [7, p. 704].

Appendix E 152

Appendix E: ADS Equations

Output Power P_average=1/2*pow(mag(I_Probe5.i[::,1]),2)*50 Battery Power P_bat=real(I_Probe4.i[::,0])*28 Power Dissipation P_trans=P_bat-(P_average+0.200) Drain Efficiency efficiency=100*P_average/(28*real(I_Probe4.i[::,0])) Phase Characteristic Phase1=unwrap(phase(vout[::,1])) Group Delay G_Delay=-diff(Phase1) Stability Delta=S(1,1)*S(2,2)-S(1,2)*S(2,1) S_=mag(S(1,2)*S(2,1)) K_factor=(1-pow(mag(S(1,1)),2)-pow(mag(S(2,2)),2)+pow(mag(Delta),2))/(2*S_) B1=(1+pow(mag(S(1,1)),2)-pow(mag(S(2,2)),2)-pow(mag(Delta),2))

Appendix F 153

Appendix F: F.1 Values Of The Stability Factor, K, And Stability Measurement, B1

freq

390.0 MHz393.0 MHz396.0 MHz399.0 MHz402.0 MHz405.0 MHz408.0 MHz411.0 MHz414.0 MHz417.0 MHz420.0 MHz423.0 MHz426.0 MHz429.0 MHz432.0 MHz435.0 MHz438.0 MHz441.0 MHz444.0 MHz447.0 MHz450.0 MHz453.0 MHz456.0 MHz459.0 MHz462.0 MHz465.0 MHz468.0 MHz471.0 MHz474.0 MHz477.0 MHz

StabFact1

0.1580.1600.1610.1630.1650.1660.1680.1700.1710.1730.1750.1760.1780.1800.1820.1830.1850.1870.1890.1900.1920.1940.1960.1980.2000.2010.2030.2050.2070.209

StabMeas1

0.2020.2000.1970.1950.1920.1900.1880.1850.1830.1810.1790.1770.1750.1730.1710.1690.1670.1650.1630.1610.1600.1580.1560.1540.1530.1510.1500.1480.1460.145

Appendix F 154

Values Of S11 And S22

freq

390.0 MHz393.0 MHz396.0 MHz399.0 MHz402.0 MHz405.0 MHz408.0 MHz411.0 MHz414.0 MHz417.0 MHz420.0 MHz423.0 MHz426.0 MHz429.0 MHz432.0 MHz435.0 MHz438.0 MHz441.0 MHz444.0 MHz447.0 MHz450.0 MHz453.0 MHz456.0 MHz459.0 MHz462.0 MHz465.0 MHz468.0 MHz471.0 MHz474.0 MHz477.0 MHz

S(1,1)

0.970 / -171.6...0.970 / -171.7...0.970 / -171.8...0.971 / -171.9...0.971 / -172.0...0.971 / -172.1...0.971 / -172.1...0.972 / -172.2...0.972 / -172.3...0.972 / -172.4...0.972 / -172.5...0.973 / -172.5...0.973 / -172.6...0.973 / -172.7...0.973 / -172.8...0.974 / -172.8...0.974 / -172.9...0.974 / -173.0...0.974 / -173.0...0.974 / -173.1...0.975 / -173.2...0.975 / -173.3...0.975 / -173.3...0.975 / -173.4...0.976 / -173.5...0.976 / -173.5...0.976 / -173.6...0.976 / -173.7...0.976 / -173.7...0.976 / -173.8...

S(2,2)

0.948 / -160.3...0.948 / -160.4...0.949 / -160.6...0.950 / -160.8...0.950 / -160.9...0.951 / -161.1...0.951 / -161.2...0.952 / -161.4...0.953 / -161.5...0.953 / -161.7...0.954 / -161.8...0.954 / -162.0...0.955 / -162.1...0.955 / -162.3...0.956 / -162.4...0.956 / -162.5...0.957 / -162.7...0.957 / -162.8...0.958 / -162.9...0.958 / -163.1...0.959 / -163.2...0.959 / -163.3...0.960 / -163.5...0.960 / -163.6...0.961 / -163.7...0.961 / -163.8...0.961 / -164.0...0.962 / -164.1...0.962 / -164.2...0.963 / -164.3...

Appendix F 155

F.2 Small-Signal Stability The input and output-matching circuits are in Figure 48 and Figure 49.

vinput

vout

HarmonicBalanceHB2

ArcMaxValue=ArcMinValue=MaxShrinkage=1.0e-5SamanskiiConstant=1FundOversample= Order[1]=8Freq[1]=LSSP_freq

HARMONIC BALANCEFSL_TECH_INCLUDEFTI1

FSL_TECH_INCLUDE

S_StabCircleS_StabCircle1S_StabCircle1=s_stab_circle(S,51)

SStabCirc le

L_StabCircleL_StabCircle1L_StabCircle1=l_stab_circle(S,51)

LStabCirc le

S_ParamSP1

Step=3.0 MHzStop=480.0 MHzStart=390.0 MHz

S-PARAMETERS

StabFactStabFact1StabFact1=stab_fact(S)

StabFact

TermTerm1

Z=50 OhmNum=1

V_DCSRC1Vdc=3.85 V

CC21C=577.6 pFC

C20C=364 pF



CC11C=150 pF

CC19C=150 pF

V_DCSRC2Vdc=28 V

RR1R=33 kOhm

CC18C=10 uF

CC17C=1.2 pF

CC16C=0.1 uF

CC15C=160 pF

LL14

R=L=47.5 nH

RR2R=30 Ohm

VARVAR1LSSP_freq=435 MHz

EqnVar

DC_FeedDC_Feed1

CC12C=1.2 pF

CC13C=0.1 uF

CC14C=10 uF

I_ProbeI_Probe2

I_ProbeI_Probe1

input3X1

ouput3X2

TermTerm2

Z=50Num=2

Appendix G 156

Appendix G: Method For Analysis Of Nonlinear Circuits This section about the non-linear circuits and how the harmonic balance is used in the analysis them. Nonlinear circuits are characterized as either weakly nonlinear or strongly nonlinear. A weakly nonlinear can be described by a first few terms of Taylor series expansion, and it is assumed that the excitation level is weak around operating point. Otherwise it is strongly non-linear circuits. The Concept Of Harmonic Balance If we have circuit like in Figure 132, which contain linear and nonlinear part

Figure 132 The diode circuit [16, p. 122].

The diode is excited by RF generator at the frequency ωp and the circuit has a complex impedance Z(ω). Because of the diode is a nonlinear circuit, it will generate harmonics of current and voltage, therefore the impedance will be a function of the harmonics Z(kωp). where k is the harmonic number. For analysing this kind of circuit we do the following:

• Assume we know the diode voltage V(kωp). After this assumption we can create the equivalent circuit as it is shown in Figure 133, which contain the linear part.

Figure 133 The linear part of the diode [16, p. 122].

Form circuit in Figure 133 we can calculate the current ILIN in the frequency domain as [16, p. 122]

)()()(

)(p

pSppLIN kZ

kVkVkI

ωωω

ω−

= (128)

Appendix G 157

where ILIN is the current in the linear part.

• V(t) is calculated using Inverse Fourier Transformation on V(kωp). The equivalent circuit for the nonlinear part is shown in Figure 134.

Figure 134 The nonlinear part of the diode [16, p. 122].

The diode current is then can be calculated as [16, p. 122]

1)( )( −= tV

satNL eItI δ (129)

KTq

ηδ = (130)

whrer INL is the current in the nonlinear part. q =1.6×10-19 [coul] is the electron charge. η is account for unavoidable imperfections in the junction. K =1.37×10-23[J/K] is Boltzmann’s constant [16, p.62].

• INL(kωp) is calculated by Fourier Transformation of INL(t).

Now we have both the ILIN (kωp) and INL(kωp).

• Use Kirchoff’s current law [16, p. 123]

0)()( =+ pNLpLIN kIkI ωω (131) If Eq. (37) is satisfied, then the initial estimation of V(kωp) is correct otherwise the V(kωp) is modified and the process is repeated.

Appendix H 158

Appendix H: Parasitic Inductance Simulation

S2PSNP1File="C:\unzipped\s2mp\100B3R9C.S2P"

21

Ref

S_ParamSP1

Step=100 MHzStop=10.0 GHzStart=100 MHz

S-PARAMETERS

TermTerm2

Z=50 OhmNum=2

TermTerm1

Z=50 OhmNum=1

Appendix I 159

Appendix I: Measuring Equipments In the following the specifications of the equipments, which are used in the test Fluke 87 Multimeter Spectrum Analyzer HP 8563 E-Series Signal Generator HP 8640 B with output power from –130dBm to +20dBm and frequency range up to 1GHz DC Power Supply HP E3615A, 0-20V, 0-3A DC Power Supply Thurlby Thandar Inatruments (TTi) EX354T Triple Power Supply, 0-35V, 0-5A 50Ω Termination, 40W Narda 20dB Attenuator,100W Tage Olsen A/S RF Limiter Agilent 11867 A, DC to 1800MHz DC-Block Model 7003 & 7006, 10kHz to 18GHz Dual Directional Coupler HP 778D 20dB Attenuator 6dB Attenuator, 20W Narda, 766-6

Appendix J 160

Appendix J: MATLAB Code J.1 Code For Microstrip Line %The Effective Dielectric Constant Of A Microstrip Line d=1.55e-3; W=2.8e-3; Er=4.6; Ee=((Er+1)/2)+((Er-1)/2)*(1/sqrt(1+(12*d)/W)); check=W/d; %The Characteristic Impedance Of A Microstrip Line %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% if check <= 1 Z0=(((60)/(sqrt(Ee)))*log(((8*d)/(W))+((W)/(4*d)))); %for W/d =< 1 else Z0=(120*pi)/(sqrt(Ee)*((W/d)+1.393+0.667*log((W/d)+1.444))); %for W/d =>1 end %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % The Width Of The Microstrip Line A=(((Z0)/(60))*sqrt((Er-1)/2))+(((Er-1)/(Er+1))*(0.23+(0.61/Er))); B=(377*pi)/(2*Z0*sqrt(Er)); if check < 2 W=((8*exp(A))/(exp(2*A))-2)*d % for W/d <2 else W= ((2/pi)*(B-1-log(2*B-1)+((Er-1)/(2*Er))*(log(B-1)+0.39-(0.61/Er))))*d % for W/d >2 end

Appendix J 161

J.2 Code For Figure 105 %test 0 dBm input x=[392:10:482]; y=[-15 -10 -6 -5 -5 -5 -4 -2 -1 -0 ] %simulation x1=[392:10:482] y1=[20.67 21.1 21.3 21.35 21.34 21.37 21.45 21.44 21.0 19.9]; plot(x,y,'-o') hold on plot(x1,y1,'-rp') hold off text(460,1,' \downarrow test','FontSize',16) text(450,20,' \uparrow simulation','FontSize',16) title('Power Amplifier','FontSize',16) ylabel('Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 162

J.3 Code For Figure 106 %test 10dBm input x=[392:10:482]; y1=[3 2 3 3 5 6 6 5.4 8.8 10] %simulation x1=[392:10:482]; y=[31.0 31.5 31.7 31.8 31.87 31.95 31.95 31.91 31.4 30.1]; plot(x,y,'-rp') hold on plot(x1,y1,'-o') hold off text(455,11,' \downarrow test','FontSize',16) text(430,30,' \uparrow simulation','FontSize',16) title('Power Amplifier','FontSize',16) ylabel('Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 163

J.4 Code For Figure 106 %test 20 dBm input x=[392:10:482]; y1=[ 11 13 13 14.2 15.7 15.9 16.4 16.4 18.5 20] %simulation x1=[392:10:482]; y=[42.4 42.8 42.9 42.9 42.9 42.9 42.9 42.7 42.1 40.8]; plot(x,y,'-rp') hold on plot(x1,y1,'-o') hold off text(455,20,' \downarrow test','FontSize',16) text(430,41,' \uparrow simulation','FontSize',16) title('Power Amplifier','FontSize',16) ylabel('Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 164

J.5 Code For Figure 108 %test 0dBm input x=[392:10:482]; y=[-2.0 -2.0 -1.0 -1.0 -1.0 -1.7 -1.5 -1.3 -0.8 -0.8 ]; %simulation x1=[392:10:482]; y1=[-4.56 -6.25 -8.104 -9.7 -11.11 -13.19 -18.613 -22.4 -10.3 -5.2]; plot(x,y,'-o') hold on plot(x1,y1,'-rp') hold off text(420,-8,' \downarrow simulation','FontSize',16) text(420,-2.5,' \uparrow test','FontSize',16) title('Power Amplifier','FontSize',16) xlabel('f [MHz]','FontSize',16) ylabel('S11 [dB]','FontSize',16) grid on

Appendix J 165

J.6 Code For Figure 109 %S11 test 0 dBm input x2=[392:10:482]; y2=[-17.0 -9.5 -8.0 -7.3 -7.2 -7.3 -8.3 -7.8 -6.2 -6.0]; %simulation x1=[392:10:482]; y1=[-4.56 -6.25 -8.104 -9.7 -11.11 -13.19 -18.613 -22.4 -10.3 -5.2]; plot(x1,y1,'-rp') hold on plot(x2,y2,'-o') hold off text(395,-12,' \leftarrow test','FontSize',12) text(420,-16,' simulation\rightarrow','FontSize',12) title(' Power Amplifier') xlabel('f [MHz]') ylabel('S11 [dB]') grid on

Appendix J 166

J.7 Code For Figure 110 %S11 test 10 dBm input x=[392:10:482]; y=[-12 -10 -8.7 -8.8 -9.5 -9.3 -7.8 -5.2 -4.7 -5.2]; %simulation x1=[392:10:482]; y1=[-4.6 -6.4 -8.4 -10.1 -11.6 -13.9 -20.5 -20.6 -9.8 -5.1]; plot(x1,y1,'-rp') hold on plot(x,y,'-o') hold off text(438.3,-9.5,' \uparrow test','FontSize',12) text(410,-14,' Simulation\rightarrow','FontSize',12) title('Power Amplifier') xlabel('f [MHz]') ylabel('S11 [dB]') grid on

Appendix J 167

J.8 Code For Figure 111 %S11 test 20 dBm input x=[392:10:482]; y=[-12.7 -9.8 -7.7 -8.7 -10.3 -10 -7.7 -4 -4.3 -5.5]; %simulation x1=[392:10:482]; y1=[-5.7 -8.3 -11.2 -13.5 -15.5 -19.5 -29.65 -14.3 -7.9 -4.4]; plot(x1,y1,'-rp') hold on plot(x,y,'-o') hold off text(452,-6,' \leftarrow test','FontSize',12) text(400,-16,' Simulation\rightarrow','FontSize',12) title('Power Amplifier') xlabel('f [MHz]') ylabel('S11 [dB]') grid on

Appendix J 168

J.9 Code For Figure 112 x=[392:10:482]; x1=[392:10:482]; x2=[392:10:482]; %test 0 dBm input y2=[-17.0 -9.5 -8.0 -7.3 -7.2 -7.3 -8.3 -7.8 -6.2 -6.0]; %test 10 dBm% y1=[-12 -10 -8.7 -8.8 -9.5 -9.3 -7.8 -5.2 -4.7 -5.2]; %test 20 dBm y3=[-12.7 -9.8 -7.7 -8.7 -10.3 -10 -7.7 -4 -4.3 -5.5]; plot(x1,y1,'-rp') hold on plot(x2,y2,'-o') hold on plot(x2,y3,'--+g') hold off text(395,-14,' \leftarrow 0 dBm','FontSize',16) text(398,-10,' 10 dBm\uparrow','FontSize',16) text(426,-5.5,' 20 dBm\rightarrow','FontSize',16) title('Power Amplifier','FontSize',16) xlabel('f [MHz]','FontSize',16) ylabel('S11 [dBm]','FontSize',16) grid on

Appendix J 169

J.10 Code For Figure 113 %test 0 dBm input x=[392:10:482]; y=[22.3 21.2 20.3 19.3 18.5 18 16 13 9.7 6.5] %simulation x1=[392:10:482]; y1=[20.67 21.1 21.3 21.35 21.34 21.37 21.45 21.44 21.0 19.9]; plot(x,y,'-o') hold on plot(x1,y1,'-rp') hold off text(460,12,' \leftarrow test','FontSize',12) text(450,20,' \uparrow Simulation','FontSize',12) title('Power Amplifier') ylabel('Output power [dBm]') xlabel('f [MHz]') grid on

Appendix J 170

J.11 Code For Figure 114 %test 10dBm input x1=[392:10:482]; y1=[29 28.8 28.5 27.8 27.3 27.3 25 23.5 20.7 16.7] %simulation x=[392:10:482]; y=[31.0 31.5 31.7 31.8 31.87 31.95 31.95 31.91 31.4 30.1]; plot(x,y,'-rp') hold on plot(x1,y1,'-o') hold off text(455,24,' \leftarrow test','FontSize',12) text(430,31,' \uparrow simulation','FontSize',12) title('Power Amplifier') ylabel('Output power [dBm]') xlabel('f [MHz]') grid on

Appendix J 171

J.12 Code For Figure 115 %test 20 dBm input x1=[392:10:482]; y1=[32 31.2 30.2 31 31.8 31.6 29 28.3 27 26] %simulation x=[392:10:482]; y=[42.4 42.8 42.9 42.9 42.9 42.9 42.9 42.7 42.1 40.8]; plot(x,y,'-rp') hold on plot(x1,y1,'-o') hold off text(455,30,' \leftarrow test','FontSize',12) text(430,41,' \uparrow simulation','FontSize',12) title('Power Amplifier') ylabel('Output power [dBm]') xlabel('f [MHz]') grid on

Appendix J 172

J.13 Code For Figure 117 %test 20 dBm input x1=[392:10:482]; y1=[39.2 39.3 39.0 39.1 39.8 39.5 38.8 39.3 38.8 38.9] %simulation x=[392:10:482]; y=[42.4 42.8 42.9 42.9 42.9 42.9 42.9 42.7 42.1 40.8]; plot(x,y,'-rp') hold on plot(x1,y1,'-o') hold off text(421,40.4,' \downarrow test','FontSize',16) text(410,42.4,' \uparrow simulation','FontSize',16) title('Power Amplifier','FontSize',16) ylabel(' Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 173

J.14 Code For Figure 120 %Test 10 dBm input x1 = [392:10:482]; y1=[22.7 22.4 22.4 21.9 22.0 22.4 22.4 22.2 21.4 21.0] %Test 20 dBm input x = [392:10:482]; y= [25.5 26.0 26.0 26.2 25.7 25.5 26.0 26.7 26.8 26.8] plot(x,y,'-ro') hold on plot(x1,y1,'-o') hold off text(430,25,' \uparrow 20dBm input power','FontSize',16) text(420,21.6,' \uparrow 10dBm input power','FontSize',16) title('RF Driver Amplifier','FontSize',16) ylabel(' Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 174

J.15 Code For Figure 121 %Test Output Power Amplifier x1=[392:10:482]; y1=[45.2 43.9 43.9 44.5 43.7 45.7 44.9 44.4 43.4 43.0] x=[392:10:482]; y2=[45.4 45.4 45.4 45.4 45.4 45.4 45.4 45.4 45.4 45.4] %Test Input [20dBm] x=[392:10:482]; y= [24.2 24.4 25.2 25.5 25.0 24.6 24.5 24.7 26.8 26.8] plot(x,y2,'--g') hold on plot(x,y,'-ro') hold on plot(x1,y1,'-o') hold off text(430,25.8,' \downarrow input ','FontSize',12) text(430,42,' \uparrow output ','FontSize',12) text(400,47,' \downarrow 35[W] ','FontSize',12) title('Power Amplifier') ylabel(' Output power [dBm]') label('f [MHz]') grid on

Appendix J 175

J.16 Code For Figure 122 %Power Amplifier With The Driver x=[387:4:487]; y=[0 0 0 0 0 20 0 0 0 0 1.0 3.0 43.0 3.0 1.0 0 0 0 15 0 0 0 0 0 0 0]; x1=[403 407 411]; y1=[0 20 0]; x2=[455 459 463]; y2=[0 15 0]; plot(x,y,'-o') hold on plot(x1,y1,'-ro') hold on plot(x2,y2,'-ro') hold off xlabel('f [MHz]') ylabel('Ouput power [dBm]') text(440,35,'\leftarrow wanted ouput power','FontSize',16) text(447,22,'undesirable','fontsize','FontSize',16,12) text(447,20,'ouput power','fontsize','FontSize',16,12) text(457,17,'\downarrow','fontsize','FontSize',16,12) title('Output Power Amplifier','FontSize',16) grid on

Appendix J 176

J.17 Code For Figure 124 And Figure 126 %S22 Driver y=[-5.5 -6 -6.8 -7.3 -7.8 -7.8 -7.4 -6.9 -6 -5.5]; x=[392:10:482]; %y1=[-7 -8.5 -10 -12 -15 -20 -15 -11.5 -8.8 -7] plot(x,y,'-o') hold on %plot(x,y1,'-ro') hold off text(450, -16,'\leftarrow modified driver', 'fontsize',12) title('Driver Output Port') xlabel('f [MHz]') ylabel('S22 [dB]') grid on

Appendix J 177

J.18 Code For Figure 127 %Test Input [10dBm] y1=[22.0 21.0 21.2 22.5 22.0 21.8 21.5 21.5 20.5 20.0] x1=[392:10:482]; %Test Input [20dBm] x=[392:10:482]; y= [24.2 24.4 25.2 25.5 25.0 24.6 24.5 24.7 26.8 26.8] plot(x,y,'-ro') hold on plot(x1,y1,'-o') hold off text(410,26,' \downarrow 20dBm input power' ,'FontSize',16) text(410,22.9,' \downarrow 10dBm input power','FontSize',16) title('RF Driver Amplifier','FontSize',16) ylabel(' Output power [dBm]','FontSize',16) xlabel('f [MHz]','FontSize',16) grid on

Appendix J 178

J.19 Code For Variable Attenuator % Attenuation in dB from 0.1dB to 1dB 10^(-0.1/10); 10^(-0.2/10); 10^(-0.3/10); 10^(-0.4/10); 10^(-0.5/10); 10^(-0.6/10); 10^(-0.7/10); 10^(-0.8/10); 10^(-0.9/10); 10^(-1/10); %Attenuation L(dB) calculation [12, p.265] %L=20log[(1+R1)/(1-R1)] %R1 Calculation, R1 is normalized to 50 Ohm L=30.0; X=L/20; y=10^X; R1=(y-1)/(1+y); %R2 Calculation, R2 is normalized to 50 Ohm X=L/20; y=10^X; R1=(y-1)/(1+y); R2=(1-R1^2)/(2*R1); % Input impedance calculation [7, p.198] %Gama=(Zin-Z0)/(Zin+Z0)|Z0 on port 2 % R1 and R2 multiplied by 50 R_1=R1*50; R_2=R2*50; Zin= R_1+[R_2*(R_1+50)]/(R_2+R_1+50);

Appendix K 179

Appendix K: RF-Driver Amplifier Layout

Appendix L 180

Appendix L: Compact Disc (CD)

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