DSP Design – Lecture 1 Introduction and DSP Basics … · – Keshab K. Parhi, VLSI Digital...
-
Upload
nguyendieu -
Category
Documents
-
view
275 -
download
5
Transcript of DSP Design – Lecture 1 Introduction and DSP Basics … · – Keshab K. Parhi, VLSI Digital...
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Design Lecture 1
Introduction and DSP Basics
Fredrik Edman, PhD
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Lecturers
Fredrik Edman (course responsible) Mail: [email protected] Room E:2538 Mojtaba Mahdavi (exercises & labs) Mail: [email protected] Room E:2339 and several invited speakers! Course Aministrator
Anne Andersson [email protected] Room E:3152b (3rd floor in the north-west part of the building)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Course information www.eit.lth.se/course/etin45
Lectures Tuesdays 13-15 in E:2517 and Thursdays 13-15 in E:3139
Seminars Wednesdays and Fridays 10-12 in E:3139, E: 1407 No seminar 1st week
Labs - Lab 1 Friday 2nd Feb between 8 - 12 - Lab 2 Friday 9th Feb between 8 - 12 - Lab 3 Friday 16th Feb between 8 - 12 - Lab 4 Friday 2nd March between 8 - 12
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Compulsary Parts
Pass 4 Laborations (MATLAB & Hardware design in CatapultC) Pass Homework exercises & Homework seminar results in grade 3
Written exam for grade 4 & 5
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Litterature
Course Litterature Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation
Extended Reading
Alan V. Oppenheim, Ronald W. Schafer with John R. Buck, Discrete-Time Signal Processing, Prentice Hall, 1999, ISBN 0-13-754920-2.
John G. Proakis and Dimitris Manolakis, Digital Signal Processing: Principles, Algorithms and Applications, Prentice Hall, 1995, ISBN 0133737624.
Sanjit K. Mitra, Digital Signal Processing. A Computer Based Approach, McGRAW-HILL, 2001 ISBN: 0-07-118175-X
Lars Wanhammar, DSP Integrated Circuits, Academic Press, 1999, ISBN 0-12-734530-2 etc.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Scope of the Course
How to get from a signal processing algorithm to an EFFICIENT implementation using a number of tools such as;
Different numbering systems Pipelining Parallelism Unfolding/Folding Strength reduction, i.e. complexity of operations. etc, etc,...
in a structured way according to the specification!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Goals Aims: Knowledge After completing the course the student should:
have gained an understanding for the relationship between parameters such as calculation capacity, power consumption and silicon area
be familiar with transformations that help the designer to develop different solutions for a given signal processing algorithm.
understand how different number representations affect the solution. Aims: Skills After completing the course the student should:
be able to suggest an architecture from a given set of criteria. be able to analyze an architecture and suggest alternative solutions.
Aims: Attitude
After completing the course the student should: have gained an overview of the field of implementation aspects of signal
processing algorithms. feel well equipped to design an application specific processor given a
specification using the methodologies covered in the course.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Introduction to DSP
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Definition DSP (Digital Signal Processing) Digital signal processing (DSP) is the mathematical manipulation of
an information signal to modify or improve it in some way. It is characterized by the representation of discrete time, discrete frequency, or other discrete domain signals by a sequence of numbers or symbols and the processing of these signals.
Digital signal processing (DSP) is the process of analyzing and
modifying a signal to optimize or improve its efficiency or performance. It involves applying various mathematical and computational algorithms to analog and digital signals to produce a signal that's of higher quality than the original signal.
Wikipedia
Technopedia
Be aware that sometimes DSP = Digital Signal Processor!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Example of DSP Applications Speech & Audio
coding, MP3 recognition echo cancellation
Image coding, MPEG4 Filtering
Wireless Communication channel coding/decoding equalization channel estimation smart antennas
beam forming MIMO, Multiple Input Multiple Output
Seismology classification recognition
Radar and sonar classification detection
Financial signal processing
filtering classification Calculations Bvlock chain technology
Biomedicin
smart sensors telemedicin pacemakers Image processing
ESS, MAX IV, etc.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Definition DSP (Digital Signal Processor) Digital signal processor (DSP) A digital signal processor (DSP) is a
specialized microprocessor, with its architecture optimized for the operational needs of digital signal processing. The goal of DSPs is usually to measure, filter and/or compress continuous real-world analog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but dedicated DSPs usually have better power efficiency thus they are more suitable in portable devices such as mobile phones because of power consumption constraints.
Wikipedia
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Programmable or Custom DSPs What to use depends on requirements
Sample rate Throughput Energy consumption Area Wordlength precision Flexibility Time to market Volume/size
Different types of Digital Signal Processors
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Extremely Low Power
Where do we find them?
Very Low Power
Low Power
Large volume of data
High performance computing
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Whats happening inside the DSP?
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
In the DSP an (DSP) algorithm is executed!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The heart of DSP algorithms are usually DSP Primitives
Convolutions Filters
FIR IIR Wave digital
Correlation FFT - fast Fourier transform DCT - discrete cosine transform LMS Least Mean Square etc...
Examples:
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design An application is often comprised of
several DSP primitives
Subband approach Reduces complexity
and achieves Faster convergence
Anders Berkeman
Example: Acoustic Echo Cancellation
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
There are several ways of implementing a DSP-algorithm in hardware. Microprocessor/controller is a small computer on a
single integrated circuit which may contain a processor core, memory, and programmable input/output peripherals.
Digital Signal Processor (DSP) a specialized
microprocessor, with its architecture optimized for the operational needs of digital signal processing.
Field-Programmable Gate Array (FPGA) - an integrated
circuit designed to be configured after manufacturing.
Application-Specific Intergated Circuit (ASIC) - is an integrated circuit customized for a particular use.
Hardware Implementation Techniques
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Architectural Options Standard Processor vs. Special Purpose
Algorithm
Standard Processor
Programable/Flexible Short design time/TTM Low price?
Special Purpose
High calculation capacity Low power consumption Low price at volume Main focus of this Course
FPGA ASIC
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Different applications, different demands... (a simplified view)
Flexibilty Complexity
Low power Low cost Flexibilty
Lower power Lower cost
Processors FPGAs
Processors ASICs
ASICs Processors
http://www.heise.de/newsticker/data/dz-30.04.02-000/aufmacher.jpghttp://www.chip.com.tr/images/content/bluetoot.jpghttp://www.mobilecomms-technology.com/projects/india_gsm/india_gsm1.htmlhttp://www.telecoms-world.co.uk/mobile-phones/sony-ericsson-t68.gif
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
This course mainly looks at specialized architectures
Could be used for either FPGA or ASIC
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Energy Efficiency
One of the key design issues!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Utilizing the computation time
MIPS
Time Max computation time
Compute as fast as we can?
Compute as slow as were allowed?
Can we control the clock frequency?
What power down options do we have? clock gating various sleep modes
Can we scale the power supply?
Dynamic How many levels
What cell library can we choose? Low power High speed
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Energy efficiency (MOPS/mW) depends on type of application
0,01
0,1
1
10
100
1000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Ener
gy an
d Ar
ea E
ffici
enci
es
Chip Number (see next slide)
Microprocessors Dedicated Designs
General Purpose
DSPs
Courtesy: Professor Bob Brodersen, UC Berkeley
Efficiencies
0.01
0.025
0.04
0.0484848485
0.0923076923
0.0952380952
0.1212727273
0.1285714286
0.6666666667
0.8
1.1666666667
1.8
1.8666666667
2.8941176471
7.2727272727
100
119.4444444444
122.2222222222
134.7368421053
135.1351351351
Energy Efficiency (MOPS/mW)
Chip Number (see next slide)
Energy and Area Efficiencies
Csw fclk
65.376344086310
46.0431654676550
64.4205372673500
42.717794257637
64.800311541000
80.1526717557450
103.4362818591667
29.9866131191450
52.2666666667300
17.7444182714100
31.9284802043200
14.6651702207180
24.4897959184350
19.603603603627
11.503267973950
17.807308970128
102.5
36.1937454545275
36.198750190581
17.411764705980
Csw (pF/mm2)
fclk (MHz)
Chip Number (see table 1)
Csw (pf/mm2) and fclk (MHz)
Aop
300
268.1327160494
107.5
133.7451171875
61.4068930041
32.75
19.9298469388
80.0540123457
7.174744898
6.46875
8.2857142857
11.6921768707
6.7515432099
7.8336720867
5.3125
0.0898507463
0.5813953488
0.0361689815
0.06328125
0.068
Aop
Chip Number (see Table I)
Aop (mm2 per operation)
Nops
1
1
2
2.5117739403
6
4
4
2
6.6666666667
32
7
12
16
9.1111111111
16
478.5714285714
34.4
16
1580.2469135803
625
Nops
Chip Number (see Table I)
Nops (Operations per clock cycle)
Data
YearNamePaperTransPwrAreaVddClkMOPS(given)Typen-wayLToxMOPSScaled CNorm AreaCswAopNopMOPS/mWMOPS/mm2
11997S/39010.37.8383002.5310Proc10.254065231065.37634408630065.37634408630010.011.0333333333
22000PPC1-SOI5.234221391.8550Proc10.183555052.6207605344268.132716049446.0431654676268.132716049410.0252.0512230216
31999G55.225252151.95001000Proc20.2540100064.420537267321564.4205372673107.520.044.6511627907
42000G65.625332151.96371600Proc2.510.232160053.3972428212335.937542.717794257133.74511718752.51177394030.04848484854.7627906977
52000Alpha5.115.2651911.651000Proc60.1832600081.0003894249368.441358024764.8003115461.406893004160.092307692316.2848167539
61998X86 MMX15.47.518.91312450Proc40.2540180080.152671755713180.152671755732.7540.095238095213.7404580153
71998Alpha18.45.7221002667Proc40.28402668103.436281859179.7193877551103.436281859119.929846938840.121272727333.467392
81999PPC5.610.57831.8450Proc20.183290037.4832663989160.108024691429.986613119180.054012345720.12857142865.6212048193
91998StrongArm18.636023002000DSP10.2840172.4285714286200052.266666666747.831632653152.26666666677.1747448986.66666666670.666666666741.8133333333
102000Comm4.242073.31003200DSP10.2540320017.744418271420717.74441827146.46875320.815.4589371981
111998Hitachi, O. Nishi18.11.2581.82001400DSP20.2540140031.92848020435831.92848020438.285714285771.166666666724.1379310345
121998Fujitsu18.21.2991.81802160DSP10.2140216014.6651702207140.30612244914.665170220711.6921768707121.815.3949090909
132000Fujitsu14.63561.83505600DSP20.1832560030.612244898108.02469135824.48979591846.7515432099161.866666666751.84
152002Matsushita22.1110.085371.527246DSP10.183224624.504504504571.373456790119.60360360367.83367208679.11111111112.89411764713.4466594595
141998NEC18.30.11851.550800DSP10.254080011.50326797398511.50326797395.3125167.27272727279.4117647059
161998EncryptJSSCP.17990.260.134432.52813400Dedicated10.25401340017.80730897014317.80730897010.0898507463478.5714285714100311.6279069767
172000Hearing aid14.51.30.00072201.22.550Dedicated10.2540861020100.581395348834.4119.44444444444.3
182000FIR4.70.0360.32.52754400Dedicated10.1840440036.19374545450.578703703736.19374545450.036168981516122.22222222227603.2
191998MPEG2-982.15.50.951001.881128000Dedicated10.254012800036.198750190510036.19875019050.063281251580.2469135803134.73684210531280
202002802.11a7.20.3742.52.58050000Dedicated10.25405000017.411764705942.517.41176470590.068625135.13513513511176.4705882353
1207
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
ISSCC Chips (0.18m 0.25m)
Energy efficiency (MOPS/mW) depends on type of application
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Complexity
A constant challenge!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Complexity Complexity of Algorithms are increasing
with new systems Number of transistors possible to implement
on a die is incresing (Moores law)
Often mature algorithms (systems) go to non-custom solutions.
But there is always new algorithms and there is power and price...
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Evolution New systems
i.e. high performance use non-standard architectures and components e.g. 5G
Mature systems
i.e. low performance compared to state of the art implemented on standard platforms mature technologies e.g. GSM, 3G
New 1 Mature 1 New 2 Mature 2 New 3
Evolution
Mature 3
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Important questions when designing hardware architectures
Which structure gets the job done? Which structure use the least amount of energy? Which structure use the least amount of area? Etc, etc, etc... How do we design architectures to achieve it?
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Basics Filters
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Digital signal processing algorithms works on samples of a continous signals. Sampling rate = nr. of samples processed/second
Analog
Digital Digital Signal
Processing
Continous signal
Sampled signal
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Two Basic DSP Structures
x(n)
D D D x(n)
h0 h3 h2 h1
y(n)
D
D
y(n)
FIR Finite Impulse Response 4-tap FIR filter No feedback
IIR Infinite Impulse Response Biquad section Feedback
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter
( ) ( ) ( )
=
=1
0
N
kknxkhny
h(.) is the impulse response which defines the filter response, e.g. low- or highpass.
D D D x(n)
h0 h3 h2 h1
y(0)
x(n-1) x(n-2) x(n-3)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter - Definitions
( ) ( ) ( )
=
=1
0
N
kknxkhny
D D D x(n)
h0 h3 h2 h1
y(0)
x(n-1) x(n-2) x(n-3)
The filter length is = N The filter order is = N-1 The number of filter taps = the filter length
A higher order filter, more taps, will result in a steeper filter function but has higher complexity!
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Quick look at filter order, length and taps
D D D x(n)
2 8 6 4
y(n)
x(n-2) x(n-3) x(n-4)
Suppose that we have the following filter: y[n]=2x[n]+4x[n2]+6x[n3]+8x[n4]
D x(n-1)
What is the filter length, filter order and number of taps?
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Quick look answer y[n]=2x[n]+4x[n2]+6x[n3]+8x[n4]
D D D x(n)
2 8 6 4
y(n)
x(n-2) x(n-3) x(n-4) D
x(n-1)
Filter length: the filter length is 5, i.e. the filter extends over 5 input samples [x(n),x(n1),x(n2),x(n3),x(n4)]. Filter order: The order of an FIR filter is filter length minus 1, i.e. the filter order in the example is 4. (The filter order is the max. delay needed, so if your filter is y(n)+y(n10)=x(n) you have a filter order of 10) # filter taps: The number of taps is the same as the filter length. In this case you have one tap equal to zero (the coefficient for x(n1)), so there is 4 non-zero taps. Still, the filter length is 5.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Example: FIR filter in Matlab D D D x(n)
h0 h3 h2 h1
y(n)
FIR-filters can be designed with the built-in filter function fir1(N,Wn) Nth order filter with the cut-off frequency Wn must be between 0 < Wn < 1.0, with 1.0 corresponding to half the sample rate.
1 2 3 4 5 6 7 8 9 0
0.05
0.1
0.15
0.2
0.25
0 5 10 15 20 25 30 35-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
32-taps 8-order
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
FIR-filter frequency response
0 200 400 600 800 1000 12000
0.2
0.4
0.6
0.8
1
1.2
1.4
Use fft to transform h(.) to frequency domain and plot.
Symmetry when real input to fft.
32-taps 8-taps
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Linear phase FIR filters
0 5 10 15 20 25 30 35-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Linear phase filters has a constant group delay in the passband, i.e. all frequency components are delayed equally no phase distortion! Linear phase filters, e.g. from fir1(), has symmetric coefficients. This can be used to simplify the filter structure.
D x(n)
h0 h2 h1
D
h4
y(n)
D
h3
D x(n)
y(n)
D
D D
D
0 5 10 15 20 25 30 35-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design The FIR filter, hardware mapped,
first clock cycle ( ) ( ) ( )
=
=1
0
N
kknxkhny
x(0)
h0 h3 h2 h1
y(0)
x(-1) x(-2) x(-3) R E G
R E G
R E G
clock
)3()2()1()0()0( 3210 +++= xhxhxhxhy
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter, second clock cycle
( ) ( ) ( )
=
=1
0
N
kknxkhny
x(1)
h0 h3 h2 h1
y(1)
x(0) x(-1) x(-2) R E G
R E G
R E G
clock
)2()1()0()1()1( 3210 +++= xhxhxhxhy
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
( ) ( ) ( )
=
=1
0:
N
kknxkhnyFIR
D D Dx(n)
h0 h3h2h1
y(n)
c MUX
REG
1 sample/cc N fixed multipliers N-1 adders
N cc/sample 1 generalized multiplier 1 adders 1 coefficient memory + control
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(n)
Sample Mem
y(n)
0
REG D D D x(n)
h0 h3 h2 h1
y(n)
How many clock cycles? Why the 0? Why the extra reg?
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(0)
Sample Mem
y(-1)
0
REG D D D x(n)
h0 h3 h2 h1
y(n)
h(0)
cc0: x(0)h(0)+0
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(-1)
Sample Mem
y(-1)
REG D D D x(n)
h0 h3 h2 h1
y(n)
h(1)
cc0: x(0)h(0)+0
cc1: x(-1)h(1)+x(0)h(0) x(0)h(0)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(-2)
Sample Mem
y(-1)
REG D D D x(n)
h0 h3 h2 h1
y(n)
h(2)
cc0: x(0)h(0)+0
cc1: x(-1)h(1)+x(0)h(0) x(-1)h(1)+ x(0)h(0)
cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(-3)
Sample Mem
y(-1)
REG D D D x(n)
h0 h3 h2 h1
y(n)
h(3)
cc0: x(0)h(0)+0
cc1: x(-1)h(1)+x(0)h(0) x(-2)h(2)+ x(-1)h(1)+ x(0)h(0)
cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0) cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(1)
Sample Mem
y(0)
REG D D D x(n)
h0 h3 h2 h1
y(n)
h(0)
cc0: x(0)h(0)+0
cc1: x(-1)h(1)+x(0)h(0)
cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0) cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
0
cc4: x(1)h(0)+0; new iteration
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeff MUX
REG
x(n)
Sample Mem
y(n)
0
REG
FSM Finite State Machine
CONTROL
load
address
reset
sample
D D D x(n)
h0 h3 h2 h1
y(n)
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form I
( ) ( ) ( )0 1
m n
i ji j
y n b x n i a y n j= =
= + The impulse response also includes feedback terms.
Steeper impulse response but possibility for unstability
y(n) x(n)
Z-1
+
Z-1
Z-1
+
+
b0
b1
bm-1
bm
Z-1
+
Z-1
Z-1
+
+
a1
an-1
an
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form II ( ) ( ) ( )
0 1
m n
i ji j
y n b x n i a y n j= =
= + Each part is a linear time-invariant system
and the order can be reversed. x(n)
Z-1 +
Z-1
Z-1
+
+
b0
b1
bm-1
bm
y(n)
Z-1 +
Z-1
Z-1
+
+
a1
an-1
an
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form II ( ) ( ) ( )
0 1
m n
i ji j
y n b x n i a y n j= =
= + The two parts can be collapsed into one with a
minimum number of delay elements.
x(n)
Z-1
+
Z-1
Z-1
+
+
a1
an-1
an
+
+
+
b1
bm-1
bm
y(n) b0
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, cascade form
( ) ( )1 2
0 1 21 2
1 1 2
; 1 / 21
sNk k k
k k k
b b z b zH z Ns Na z a z
=
+ += = +
x(n)
D
D
y(n)
Often cascaded with shorter sections which are combined, easier to design when fixed-point arithmetic. The above is often referred to as biquad sections.
D
D
D
D
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Basics DFT - FFT
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DFT - FFT
The Discrete Fourier Transform (DFT) is a mathematical operation. The Fast Fourier Transform (FFT) is an efficient algorithm for the evaluation of that operation (actually, a family of such algorithms).
The fast Fourier transform (FFT) samples a signal over a period of time (or space) and divides it into its frequency components.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DFT - FFT
The DFT/FFT is one of the most common digital signal processing algorithms.
Used to determine frequency content of a discrete signal sequence.
Transform between time and frequency domains.
The FFT is a low complexity way of computing the DFT.
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
N-point DFT
1,...,1,0,)()(1
0==
=
NkWnxkXN
n
knN
NknjknN eW
/2=
N filters of length N O(N2)
N
N
N
Only every Nth sample
x(n) X(0) X(1)
X(N-1)
The DFT determines spectral content at N equally spaced frequency points, i.e. coorelates with different frequencies,
N samples are needed.
( ) sampleanalysismf
f mN
=
Complex
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
X(3)
X(15)
X(7)
X(11)
X(1)
X(13)
X(5)
X(9)
x(12)
x(15)
x(14)
x(13)
x(8)
x(11)
x(10)
x(9)
W 8
X(2)
X(14)
X(6)
X(10) W 2
W 6
X(0)
X(12)
X(4)
X(8)
x(4)
x(7)
x(6)
x(5)
x(0)
x(3)
x(2)
x(1)
W 7
W 5
W 6
W 4
W 3
W 1
W 2
W 0
W 6
W 2
W 4
W 0
W 0
W 0
W 4
W 0
W 4
W 0
W 4
W 0
W 4
stages )(log2 N
)(log2
)(
2
2
NN
NODFT FFT
FFT is low complexity DFT
-
Fredrik Edman, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
End of Lecture 1
See you on Thursday
DSP Design Lecture 1 Introduction and DSP BasicsFredrik Edman, [email protected] 2Course informationCompulsary PartsLitteratureScope of the CourseGoalsIntroduction to DSPDefinition DSP (Digital Signal Processing)Example of DSP ApplicationsDefinition DSP (Digital Signal Processor)Different types of Digital Signal ProcessorsWhere do we find them?Whats happening inside the DSP?Bildnummer 15The heart of DSP algorithms are usually DSP PrimitivesAn application is often comprised of several DSP primitivesHardware Implementation TechniquesArchitectural Options Standard Processor vs. Special Purpose Different applications, different demands...(a simplified view) This course mainly looks at specialized architectures Energy EfficiencyOne of the key design issues!Utilizing the computation timeEnergy efficiency (MOPS/mW)depends on type of applicationISSCC Chips (0.18m 0.25m)ComplexityA constant challenge!ComplexityEvolutionImportant questions when designing hardware architecturesDSP Basics FiltersBildnummer 31Two Basic DSP StructuresThe FIR filterThe FIR filter - DefinitionsQuick look at filter order, length and tapsQuick look answerExample: FIR filter in MatlabFIR-filter frequency responseLinear phase FIR filtersThe FIR filter, hardware mapped, first clock cycleThe FIR filter, second clock cycleBildnummer 42Bildnummer 43Bildnummer 44Bildnummer 45Bildnummer 46Bildnummer 47Bildnummer 48Bildnummer 49The IIR filter, direct form IThe IIR filter, direct form IIThe IIR filter, direct form IIThe IIR filter, cascade formDSP Basics DFT - FFTDFT - FFTDFT - FFTN-point DFTFFT is low complexity DFTEnd of Lecture 1See you on Thursday