Driver Waveform Computation for Timing Analysis with Multiple Voltage

Threshold Driver Models

Peter Feldmann*, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta

IBM T.J. Watson Research, Yorktown Heights, NY*IBM Systems & Technology Group, Hopewell Junction, NY

June 11, 2008DAC 2008, Anaheim, CA

2

Introduction

Traditional gate delay characterization Capacitive loads only Output signal assumed to be a ramp Delays and slews functions of input slew

and capacitive load

Sources of inaccuracy Non-ramp-like waveforms Highly resistive modern day interconnects Inductive effects

3

Concept of effective capacitance (Ceff)

Ideally match output waveform using Ceff

instead of RC load Match charge in interval [tv=0 , tv=0.5Vdd]

Single number – not accurate enough

0 25 50 75 100 125 150 0.0

0.2

0.4

0.6

0.8

1.0

Time (ps)

Cur

rent

/ V

olta

ge a

t A

RC Line

tiA

tvA

Ceff

A

A

4

Recent industry trends

Non-linear current source models (CSM) Effective Current Source Model (ECSM)

Cadence, Magma Driving current I = fI(V, Cdyn) For given input slew, characterization data

stored as: Time = T(V, C)

CLoad

InSlew

dotLib + ECSMOp Voltage Waveform Table

t1 t2 t3 t4 t5 t6

v1v2

v3

v4

v5

v6

Op Voltage

Time

PWL*

*PWL = Piece Wise Linear

5

Recent industry trends (contd.)

Non-linear current source models Composite Current Source (CCS)

Synopsys Driving current I = fI(V, Cdyn) For given input slew, characterization data

stored as: I = I(T, C)

CLoad

InSlew

dotLib + CCSOp Current Waveform Table

PWL

t1 t2 t3 t4 t5 t6

I1

I2

I3

I4

I5

I6

Io

t0

Out

put C

urre

nt

Time

6

Simulating current source models

For a given input ramp (slew) Transformations required (T ~ time)

T = T(V, C) I = fI(V, C) I = I(T, C) I = fI(V, C)

Approximation, accuracy loss Accurate transformation requires

High degree of continuity Smoothness

7

Contributions

Accurate and efficient analytical framework for driver waveform computation

Novel algorithm for simulation of CSM Simulation along V axis and not T axis

Avoids time domain integration (requires smooth data, time step control etc.)

Requires model in MVTM* form: T= T(V, C) Same as industry standard characterized data No transformation to I = fI(V, C) Eliminates approximations Assumes monotonic piecewise linear output voltage

waveform

*Multiple Voltage Threshold Model

8

Dynamic capacitance concept (Cdyn)

A driver’s time varying instantaneous equivalent load capacitance

Generalization for multiple voltage threshold model

dt

tdvtitCdyn

)(/)()(

RC Line

i(t)

v(t)

pp

p

p

T

T

pd VV

Q

V

dtti

C

p

p

1,

1

)(

Time

1pV

pV

1pTpT

9

Driver waveform computation

Assume current state Tp, Vp

Goal: Given Vp+1, calculate Tp+1

Charge supplied by driver Assuming change in V linear for Tp

Out

put V

olta

ge

Time

pdppp

T

TCVVQdtti

p

p,1 )()(

1

1pV

pV

1pTpT

Tp

unknown

10

Driver waveform computation (contd.)

Charge flowing into load in Tp: Qp

Can be expressed analytically as f(Tp+1)

Equate charge Unknowns: Tp+1, Cd,p

Use information from driver model (characterization table)

),(),( ,,11 pdppdppp CVCVTT

RC Line ti

tvEQ1

EQ2

11

Small testcase setup

Test common gates (INV, BUFF, AND, XOR) driving RC interconnect loads Compare near-end waveforms

SPICE Traditional Ceff approach Proposed approach denoted as MVTM

(Multi voltage threshold model) Ramp of 20ps slew at gate input Krylov method used to compute

interconnect delay

12

Results

Cn (fF)R

(Ohms)Cf (fF)

Gate Delay Near-end Slew Wire Delay

Ceff MVTM Spice Ceff MVTM Spice Ceff MVTM Spice

2 342 200 20.7 20.8 22.9 153 61 73 73.3 60 60

100 342 200 40 40 40 127 95.3 93.9 66.5 62 61

200 342 200 56.5 55.4 55.5 147 123 118 68 64 64

400 342 200 88 86 86 205 181 175 72.7 68 68

400 1022 200 80 79 79 181 155 148 177 169 167

200 1022 200 51 51 51 105 85 81 167 162 159

100 1022 200 37 37 37 74 47 47 164 159 160

2 1022 200 19 19 20 246 12 14 186 157 153

2 20 200 46 46 46 70 66 67 4 4 4

100 20 200 60 60 60 96 92 92 4 4 4

200 20 200 74 75 74 124 123 120 4 4 4

400 20 200 101 102 101 184 182 176 4 4 4

Delay and slew values are in psecs

R

Cn Cf

100 m RC Line

13

Small testcase results (contd.)

In this experiment, the CMOS gate under test is a NAND2. The Cn=20fF, Cf=480fF, R=500. This experiment shows that MVTM follow SPICE while the Ceff technique incurs about 20% error in gate delay and about 40% in slew calculation.

14

Large testcase setup and results

Tested on large microprocessor units 65 nm designs

Design, runtime and memory stats

+5% +20%

15

Large testcase results (contd.)

Timing comparison with traditional Ceff based gate delay calculation Largest difference paths analyzed in SPICE Observed MTVM models more accurate

Within 3% of SPICE

DesignNum. timing points

comparedComparison

typeMax diff

(ps)Avg. diff

(ps)

1 2.45MArrival time 31.6 2.6

Slew 120.4 5.3

2 3.54MArrival time 45.3 3.1

Slew 140.5 5.4

16

Summary

Accurate and efficient timing analysis Based on Multiple Voltage Threshold Models Realistic load models can be handled

Novel algorithm for simulation of CSMs Eliminates need of intermediate transformation of

models to I = fI(V, C) Compatible with industry standards Acceptable runtime

Limitations, assumptions Driver input voltage waveform ramp Monotonic output voltage waveform