DRAM Design Overview - graphics.stanford.edu
Transcript of DRAM Design Overview - graphics.stanford.edu
Page 1
Stanford CS Junji Ogawa MH students Feb. 11th. 1999
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
DRAM Design Overview
Stanford University
Junji Ogawa
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Contents
・Trends of Standard DRAM
・History of DRAM Circuits
・Cell, Array and Major Circuits
・Embedded DRAM
・ASM Example
・Summary
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Stanford CS Junji Ogawa MH students Feb. 11th. 1999
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
90 92 94 96 98 00 02 04 06 08 10
1000
100
20
50
200
500
64M
256M
1G
Die
Siz
e(m
m2
)
Early Production
Production256M
1G
4G
0.18 0.13 0.100.35
Rule
(um)
Year
i-line ?ArF
16M
0.50
64M
0.25
4G
KrF
128M
KrF+α
Standard DRAM Development
Conference
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Bit Cost Trend of DRAMs
Ru
le(
µm)
Die
Siz
e(
mm
2)
De
nsit
y(
Mb
its)
Bit
Co
st(
$)
10-2
10-1
100
101
102
103
104 10
-0
10-6
10-5
10-4
10-3
10-2
10-1
1980 1985 1990 1995 2000 2005 2010
Rule
Die size
Density
Bit Cost
Year
16M
64M256M
1G4G
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DRAM Design Overview
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Access Time Trend
TR
AC
(/R
AS
Access T
ime :
ns)
Po
we
r S
up
ply
Vo
ltag
e (
V)
1/t
AA
(/C
AS
Access F
req
uen
cy :
MH
z)
f C
LK
(Po
pu
lar
Syn
ch
ron
ou
s F
req
uen
cy :
MH
z)
VCCx10
TRAC
1/tAA
f CLK
107
108
109
4M 16M 64M 256M 1G 4G
1
102
101
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Pro
du
ct V
olu
me [
100 m
illi
on
]
SDRAM
'98 2000Year
'97 '99
16M
4M
64M
64M
16M
>128M
Rambus
FPM
SD
EDO
SD
SD
EDO
RD
?25 --
10 --
20 --
0 --
Standard DRAM Column Access Mode
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DRAM Design Overview
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ASSP/ASIC
Sta
ndard
Operating Frequency
Custo
mizability
WRAM
VRAM
DRAM/Logic
SLDRAM
CDRAM
EDRAM
EDO
MDRAM
Function rich DRAM
100MHz 500MHz200MHz
DDR
1GHz 2GHz
High-speed DRAM
TargetSDRAM
RAMBUS
DRAM Operating Frequency v.s. Customizability
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Inte
rnall
y R
eg
ula
ted
Su
pp
ly V
olt
ag
e(v
)
Po
wer
Su
pp
ly V
olt
ag
e (
v)
Wo
rd B
oo
st
Vo
ltag
e (
v)
Bit Density
4M 16M 256M 1G 4G64M0
2
4
6
8 Internally Regulated Supply Voltage(V)
Power Supply Voltage (V)
Word Boost Level(V)
VCC & VII & WL Voltage Trend
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10-2
10-1
100
101
Acti
ve
Po
we
rtR
C=
min
. (A
)
Po
we
r S
up
ply
Vo
lta
ge
(V
)
Sta
nd
-by P
ow
er
( Lo
w P
ow
er
mo
de
:m
A)
4M 16M 64M 256M 1G 4G10
-2
10-1
100
101
Active Power
VCC
Low Power
Stand-by Power
Power Dissipation Trend
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DRAM Design Overview
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Refresh Specification Trend
Numbers of Active S/As
Refresh Cycles
Refresh Interval (max.:ms)
Busy Rate (µ s)
Distributed Refresh Interval
Nu
mb
ers
of
Acti
ve S
en
se A
mp
lifi
ers
Refr
esh
Cycle
s
Refr
esh
In
terv
al (m
ax.:
ms)
Bu
sy R
ate
(µ
S)
Dis
trib
ute
d R
efr
esh
In
terv
al
102
103
104
105
100
101
102
103
1M 4M 16M 64M256M 1G 4G
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History
・1K DRAM Intel 1103 introduced late 1971
-3Tr PMOS, 1P1M,
-Vdd=0v,Vss=16v,Vbb=20v, Trac=300ns
・4K DRAM TI TMS4030 introduced 1973
-1Tr NMOS, 1P1M, TTL I/O
-Vdd=12v,Vdd=5v, Vss=0v,Vbb=-3/-5v
・16K DRAM Mostek MK4116 introduced 1977
-1Tr NMOS, 2P1M, Address multiplex
-Vdd=12v,Vdd=5v, Vss=0v,Vbb=-5v, Trac=250ns
**Open / Folded bit line, Double poly cell, Multi-PS
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DRAM Design Overview
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Bascic Bitline Structure (1)
Memory
ArrayBL
WL
Memory
Array
/BL
S/As
Open Bitlines
Relaxed S/A layout pitch
Even WL coupling
Folded Bitlines
Memory
Array
BL
WL
/BL
S/As
Folded BL
Cell Size 8F2
WL pitch: 4F
BL pitch: 2F
Denser Memory
Uneven WL coupling
Open BL
Cell Size 6F2
WL pitch: 3F
BL pitch: 2F
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History (cont’d)・64K DRAM (’80,conference’79)
-Many changes at once - no dominant design
-Standardized, Page mode, Refresh functions
-Vcc=5v only,Vss=0v,Internal Vbb, Trac=200ns
-Boosted wordline, Active restore
・256K DRAM (’83,conference’82)
-1Tr NMOS, 3P1M(FJ), I.I. mask increasing
-Vcc=5v only, Nibble/SC/CBR func., Trac=150ns
-Open v.s. Folded, Redundancy, CMOS prototype
-Vdd bitline pre-charge
-Some ASM, Wide I/O (x4)
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DRAM Design Overview
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History (cont’d)
・1M DRAM (’86,conference’84)
-N-well CMOS, 3P1M, Vdd/2 cell plate
-Half Vdd bitline reference and pre-charge,
-Shared folded bitline
-x4/x8, Package and module variety, Test circuits
・4M DRAM (’89, conference’87)
-3D stacked or trench cell, CMOS, 4P1M,
-x16, Fast page/Self refresh, Trac=80ns
-Current-mirror data bus amp., Boosted I/O driver
-Word line strapping, Triple-well
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Basic Bitline Structure (2)
Interleaved (Multiplexed)
Used in nearly all 16M
Relaxes S/A pitch
Memory
Array
WLU
Memory
ArrayBL
L
WLL
BLs
S/As
S/As
S/As
Memory
ArrayWL
U
Folded Shared
Memory
Array
BLL
/BLL
WLL
BLU
/BLU
S/As
Less area occupied
by S/As
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
History (cont’d)
・16M DRAM (’92, conference’90)
-N-well CMOS, 4P2M
-Internal Vdd down-converter (5v ext.---3.3v int.)
-Shared Y-decoder, Interleaved S/A,
-Vpp supply WL driver, RDRAM(PLL/DLL)
・64M DRAM (’95, conference ’91)
-Triple well CMOS, Vss Substrate, 4P2M,
-Vdd=3.3v, Separate I/O PS-pin (Vddq/Vssq)
-SDRAM (clocked In, pipelined, burst I/O, term. I/F)
-COB, Staggered Sense amp.
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Circuit Evolution Picking up
・3Tr to 1Tr1C ・Address Multiplex
・Boosted Wordline ・Open BL to Folded BL
・Single Power Supply ・NMOS to CMOS
(Vbb gene., WL boost) ・Page & Refresh Mode
・Redundancy ・Appli. Specific Circuits
・Vdd/2 BL pre-charge (ex. SR for VRAM)
・ Internal DC converter ・Test mode
・ Clocked operation ・ Pipelined operation
・ PLL/DLL ・ High speed interface
・ Multi-bank core ・ Embedded core
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DRAM Design Overview
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Cell Array and Circuits
(1) 1 Transistor 1 Capacitor Cell・Size Comparison to SRAM Cell
(2) Array Example
(3) Major Circuits (today’s example)・Sense amplifier
・Dynamic Row Decoder
・Wordline Driver
The other circuits interesting for VLSI designer
・Data bus amplifier ・Voltage Regulator
・ Reference generator ・Redundancy technique
・Replica technique ・High speed I/O circuits
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DRAM Design Overview
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WL
BL
Cwb
BL /BL
WL
Passive element
(No gain, Refresh needed) Gain element in cell
6Tr embedded SRAM 1Tr1C Standard DRAM
SRAM v.s. DRAM
Cs
Cbl
Storage Node
Plate
Access Tr
(Cell Tr,
Transfer Tr)
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Comparison of SRAM and DRAM Cell Size
6Tr SRAM
Plainer
Stack
DRAM
Design Rule [um]
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Cell
Siz
e [
um
2]
0.1
1
10
100
3Tr
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DRAM Design Overview
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32 Mbit array.
0 7
DQ
MW
DECMW
DEC
8 global data buses
MWL
8 global data buses
and 8 amplifiers
0 7 8 15
32 Mbit 32 Mbit
DQ DQ
bank 0 bank 8
7 715 15
64 Mbit Core, a part of 256M DRAM
64 Mbit DRAM consists of two 32 Mbit arrays
bank 0 bank 8
Standard DRAM Array Design Example
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DRAM Design Overview
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256S
/A
4 R
ed-S
/A
4R
**S
/A
Mark
-RA
M(4
S/A
for 6
4K
)
256S
/A
1024S
/A+
4R
**S
/A+
16R
ed-S
/A+
4M
ark-R
AM
(256 C
L)
Sub-W
ord
Deco
der
256K
Cell
Arra
y←
s/a-0
←s/a-1
←s/a-2
←s/a-3
←s/a-4
←s/a-5
←s/a-6
←s/a-7
←s/a-8
←s/a-9
←s/a-10
←s/a-11
←s/a-12
←s/a-26
←s/a-27
←s/a-28
←s/a-29
←s/a-30
←s/a-31
←s/a-R0
←s/a-R1
←s/a-32
64K
4096S
/A+
16R
**S
/A+
64R
ed-S
/A+
16M
ark-R
AM
(64
S/A
)
(1024 CL
)
C-D
EC.
(64CL)C-D
EC.
(64CL) C-D
EC.
(64CL) C-D
EC.
(64CL) C-D
EC.
(64CL) C-D
EC.
(64CL)
C-D
EC.
(64CL)C-D
EC.
(64CL)
Colu
mn D
ecoder &
Driv
er (256C
L)
Mark
& S
pare C
ol.
Address R
AM
EO
R &
etc.
Mark
&A
dd.
RA
M
Driv
er
MarkOu
t
EO
R
Mark
&A
dd R
AM
(for 6
4K
)
1M
BL
OC
K #
1
1M
BL
OC
K #
2
1M
BL
OC
K #
3
1M
BL
OC
K #
4
1M
BL
OC
K #
5
1M
BL
OC
K #
6
1M
BL
OC
K #
7
1M
BL
OC
K #
8
1M
BL
OC
K #
9
1M
BL
OC
K #
10
1M
BL
OC
K #
11
1M
BL
OC
K #
26
1M
BL
OC
K #
27
1M
BL
OC
K #
28
1M
BL
OC
K #
29
1M
BL
OC
K #
30
1M
BL
OC
K #
31
12
8K
Sp
are R
ow
BL
OC
K #
R
1M
BL
OC
K #
0
CO
L. D
EC
OD
ER
Mark
& A
dd
RA
M(fo
rCO
L. )
32
M-C
EL
L B
LO
CK
100%
+0.3
9%
+1.5
6%
+ 1
.56%
=3.5
%
256
MWL
RC
LCL
Main Word Decoder / Driver
DRAM Array Example
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DRAM Design Overview
Junji Ogawa
512K Array Nmat=16 or 12
( 256 WL x 2048 SA)
Interleaved S/A & Hierarchical Row Decoder/Driver
(shared bit lines are not shown)
SA
SA
SA SA
SA
SA
SA SA
SA SA
SA
SA
SA
SA
SA
SASA
SA SA
SA
SA
SA
SA
SA
SA
SA
SA SA
SA
SA
SA SA
PP P P
PP
QQQ
QM
ain R
ow
Dec
PPP
P
1 2 3 Nmat
Clu
mp T
R o
r so
DRAM Array Example (cont’d)
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DRAM Design Overview
Junji Ogawa
<WL Strapping Type>
Reset
Addresses WDi
AL strap line
P1 word line
Contact only (Strapping)
DynamicNAND
VCC
Row Decoder and Driver
Main
Row
Dec
Clu
mp
TR
or s
o
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Junji Ogawa
<Hierarchical WL Type>
Main
Row
Dec
Clu
mp
TR
or s
o
Row Decoder and Driver (cont’d)
P1 sub-word line
AL Main Word Line
VPP
VPP
→ ↓
WDij
↓
WDik
↓
WDil
↓
WDimReset Reset Reset Reset
Sub Word Decoder
PP
Negative Voltage?
Reset
Addresses
DynamicNAND
/rbnk#
Pre-decode
address
MWL
/pre#
# is bank No. MWDEC
level
shifter
VPP
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Sense Amplifier Circuits - Folded Shared Interleaved -
psa
nsa
ldb0z
ldb0x
ldb1z
ldb1x
PSANSA
BLR
/BLR
Local Data Bus
CL
BLL
/BLL
BLTR BLT
R
BS
VPR
t
/RAS
RAS
Add.
WD WL
/BL
BL
BS
PSA
NSA
LE
CL
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DRAM Design Overview
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Nch Pch
Nch Pch Nch
Nch Pch
Sense Amplifier Pitch Matched Layout
Bitlines
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Standard DRAM Design Feature
・Tightly depends on technology
・The row circuits is fully different from SRAM.
・Few product variation in the same technology
・“Trends” is mother , “Cost” is father .
・“Standard” gives us less freedom!
・Almost always analogue circuit design
・Simply forward critical path
・CAD: Spice-like circuits simulator
Fully handcraft layout,
Whole-chip tools must be a dream.
Page 15
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DRAM Design Overview
Junji Ogawa
Embedded DRAM or Merged D&L
・Merged DRAM and Logic
-Technology choice and cost issue
----People have talked too much above.
-Otherwise, that’s a near future evolution.
・Current Technology behind advanced DRAMs’
・Small ASIC seems to be not yet on the business.
・How solve the following technical problem?
memory wall, granularity, I/O power
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Speed Gap between DRAM and CPU - Memory Wall -
1
10
100
1000
80 85 90 95 00Per
form
an
ce(
Sp
eed
Ra
tio)
Year
60%/year
7%/year
Increasing
The Gap
μPU
DRAM
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DRAM Design Overview
Junji Ogawa
The numbers of DRAM on PCs
1Mb 4Mb 16Mb 64Mb 256Mb 1Gb
86 89 93 97 01 05
4MB
8MB
16MB
32MB
64MB
128MB
256MB
Main
Mem
ory
Siz
eDRAM Generation
32 8
16 4
8 2
4 1
8 2
4 1
8 2
Memory/System
growth @25%/year
Memory/DRAM
growth @60%/year
32
16
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Macro Power (MDL v.s. Standard DRAM)
0
1.0
2.0
3.0
32 64 128 256
Pow
er [
W]
I/O width
External
Standard DRAM
16
8
1
0.35um
8M Macro
4.0
2.35W
1.11W
I/O Load
Charging70%
Re-design
Page 17
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DRAM Design Overview
Junji Ogawa
Macro Power (cont’d)
External use of
Standard DRAM
47%
8M
Macro
15%
Load
50pF
Pow
er[W
]2.35W
1.11W
Load 1pF
75%
Macro
Re-design & Shrink
Independen
t
on I/O No.
70%
0.78W
75 % Macro Power depends on
the numbers of I/O
Load 1pF
depend on I/O No.
(Column)
depend on I/O
No.
(Row)
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
M32R/D(Mitsubishi)
・0.45µm DRAM
・32-bit RISC CPU
+ 16Mbit DRAM
・Die Size: 153.7mm2
The First Commercial Product of Embedded DRAM
Page 18
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DRAM Design Overview
Junji Ogawa
0.25um Embedded DRAM Products
DRAM v.s. Logic Size
2 4 816 32 74
DRAM Size (M bits )
50
150
500
1500
5000
Logic
Ga
te (
K g
ate
s )
J (HDD)L
H
F
E’
E (TV)
A
C
G
B
Logic
Rich
DRAM
Rich
Network
Graphics
MCU Core
K
D
E
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Memory Density and Logic Gates
SRAM
1 Gb
Mem
ory
Den
sity
Gates100 K 1 M10 K
10 Mb
100 Mb
1 Mb
DR
AM
Are
a Ratio
=0.9
0.1
Standard DRAM Technology
MDL Technology
10 M
0.05
Pure Logic
Technology
0.35 um
0.25 um
0.18 um
C
D
B
MDL Process
: Affordable DRAM-density & Logic-gates in a 100mm2 Die
A
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DRAM Design Overview
Junji Ogawa
DRAM Macro Size Shrinkー Which could make cost effective ?
10mm
Rule(um)
DR
AM
Macro A
rea(
mm
2)
C
A
E
8Mb
F
D
16Mb
0.50 0.35 0.25 0.18
100
0
:16Mb
: 8Mb
:32Mb
B
32Mb
10mm DRAM
Cost Effective
Region? G
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Application Specific Memory
・Various ASM introduced since ’83
-VRAM: 64K to 4M VRAM
-Field Memory(NEC), Triple Port(FJ)
-mostly for ASICs or conference chips
・Only VRAM got a semi-standardization
・ Longer design TAT
as more complicated spec. and circuits
・Redundancy and Test isuues: big problems
・Never major products
-Brief Introduction-
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DRAM Design Overview
Junji Ogawa
変 換
)
BUS
Para
llel
to S
eria
l
Time Share
CPU efficiency 50%
Standard DRAM
256K Dual Port Video RAM
(a) Conventional 2D Graphic System
(b) 2D Graphic System used VRAM
Conditional Dual Port
1024 bit transfer @100ns
CPU efficiency 95%
BUS
VRAM
RAMSA
M
RAM
Sif
t R
egis
ter
CPU
CPU
CRT
CRT
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
S/A
SAM
RowDec .
Column Dec.
Cell Array
Amp.
Amp.
Sout/Sin
Dout/Sout
(Random Port)
(Serial Port)
・Narrow pitch matched SAM (or Sift Register) design
・No explicit bus for a mass of data transfer at a time
・A hinted solution by utilizing a memory parallelism
256K Dual Port Video RAM (cont’d)
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DRAM Design Overview
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4M bit Cubic Memory (conference ’90)
・16b x 16b x 16b (4Kbit) virtual bit map space
・six different ways of column access on the fly access
Feb. 11th. 1998
DRAM Design Overview
Junji Ogawa
Summary・Passive 1Tr1C cell leads all the features of dynamic
circuits and design complexity.
・The row circuits is fully different from SRAM.
・A Dinosaur, Standard DRAM, become almost dead,
because of both the technology saturation and
the narrow band-width itself.
・ The design technique should be transferred
for the coming embedded era.