DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference...

DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference

Metrology RoadmapMetrology Roadmap4 - 054 - 05

EuropeEurope Rien Stoup (PAN Analytical)Rien Stoup (PAN Analytical)Dick Verkley (FEI- Philips)Dick Verkley (FEI- Philips)

Mauro Vasconi (ST)Mauro Vasconi (ST)

JapanJapan Atsuko Yamaguchi (Hitachi)Atsuko Yamaguchi (Hitachi)

KoreaKorea Chin Soobok (Samsung)Chin Soobok (Samsung)Mann-Ho Cho (KRISS)Mann-Ho Cho (KRISS)

Taiwan Taiwan J.H. Sheih (TSMC)J.H. Sheih (TSMC)

USUS Jack Martinez (NIST)Jack Martinez (NIST)John Allgair (Freescale/SEMATECH)John Allgair (Freescale/SEMATECH)Steve Knight (NIST)*Steve Knight (NIST)*Alain Diebold (Int. SEMATECH)*Alain Diebold (Int. SEMATECH)*


AGENDAAGENDA

• 2005 ITRS Changes and Activities

• Lithography Metrology

• FEP Metrology

• Interconnect Metrology

• Key Challenges


Transistor EvolutionTransistor Evolution

Today90 nm Node

Strain Enhanced Mobility

Tomorrow

New Materials

CMOSpMOS FINFET

Future15 years

Non-classical CMOS

Beyond CMOS

source

Gate

drain

source

Gate

drain

Molecular Switches ? Nanowire Transistor ?


Nanotransistors – The FutureNanotransistors – The Future

Nano TransistorsIdsat ~ W Cox (VG – VT) sat

Long Channel Behavior

Idsat ( 1/Lg ) ( Carrier Mobility ) ( 1/EOT ) ?

= Cload VDD / IdsatC dependenceA = Lg x WDopant Conc.

Short


New BusinessNew Business

• Established link with Emerging Research Materials group of ERD– ERM to report requirements– Metrology Reports Methods and Discussion– Provided update on aberration corrected TEM

and 3D TEM developments

• Awaiting changes in Process Tolerance for Gate CD

2005 ITRS Changes2005 ITRS Changes2005 2007 2010 2013 2016 2018 2020

Technology Node 80 nm 65 nm 45 nm 32 nm 22 nm 18nm 14 nmDriver

MPU ½ Pitch (nm) 85 67 48 34 24 19 15MPU Printed Gate Length (nm) 54 42 30 21 15 12 9MPU Physical Gate Length (nm) 32 25 18 13 9 7 6

80 65 45 32 22 18 14Lithography MetrologyPrinted Gate CD Control (nm)Allowed Litho Variance = 3/4 Total Variance of physical gate length

2.8 2.2 1.6 1.1 0.8 0.6 0.5 MPU

Wafer CD Tool 3 Precision P/T=0.2 for Printed and Physical Isolated Lines

0.6 0.4 0.3 0.2 0.2 0.1 0.1 MPU

Line Width Roughness (nm) <8% of CD 2.6 2.0 1.4 1.0 0.7 0.6 0.5 MPU

Precision for LWR 0.5 0.4 0.3 0.2 0.1 0.1 0.1

Front End Processes Metrology

High Performance Logic EOTequivalent oxide thickness (EOT) nm

1.2 0.9 0.8 0.6 0.5 0.4 MPU

Logic Dielectric EOT Precision 3 (nm) 0.0048 0.0036 0.0032 0.0024 0.002 0.0016 MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

15 10 7 5 4 MPU

Interconnect MetrologyBarrier layer thick (nm) 10 7 5 3.5 2.5 2 MPU

Void Size for 1% Voiding in Cu Lines 8.5 6.7 4.8 3.4 2.4 1.9 MPU

Detection of Killer Pores at (nm) size 8.5 6.7 4.8 3.4 2.4 1.9 MPU


Changes to Litho CD MetrologyChanges to Litho CD Metrology

45 nm contact Holes16 nm Lines -176 nm Pitch

ITRS July Presentation by Dan Wack – KLA-TencorScatterometry to at least the 45 nm NodeBryan Rice (Intel), SPIE, 2004CD-SEM and Scatterometry can reach 32 nm Node w/improvement – impact of SOI not tested


0

2

4

6

8

10

12

14

16

10 100 1000 10000

Experiments

Simulation

2m

LWR increase becomes negligible at L=2m

Experiments & Simulation Confirmed by ...

3 (

nm)

Inspection-area height L (nm)

CD variation

Average LWR

Japan ITRS TWG Input LWR as a Function of L Japan ITRS TWG Input LWR as a Function of L L above 2 L above 2 m is really CD variation

L value works for many resists as well as ADI, resist trim, and after etchL value works for many resists as well as ADI, resist trim, and after etch


0

1

2

3

4

5

0 100 200 300 400 500

Wire width(nm)

Res

isti

vity

(μΩ

cm)

p=0(complete diffuse scattering)

p=0.5

Measured Cu resistivitywithout Barrier Metal

ρ(Al):2.74μΩcm

p=0.3

Updated(May2004)

Trend: Sidewall Control will become more Trend: Sidewall Control will become more ImportantImportantLine Edge Roughness impacts Interconnect Resistance and Line Width Line Edge Roughness impacts Interconnect Resistance and Line Width Roughness impacts Transistor Leakage CurrentRoughness impacts Transistor Leakage Current


• Measure LER and LWR = for reliability all spatial wavelengths between 1 micron to 20 nm taken over a 2 micron length with a spacing of 10 nm.

• LER: For monitoring Interconnect specular scattering – measure from 34 nm to twice the smallest interval using the smallest possible interval. Measure sidewall after barrier metal dep.

LER and LWRLER and LWRreported as RMS values integrated over the frequency range reported as RMS values integrated over the frequency range specified belowspecified below


Overlay MetrologyOverlay Metrology

• Issues are with the Overlay TargetsIssues are with the Overlay Targets• Need better correlation between overlay target Need better correlation between overlay target

and device performanceand device performance– Current roadmap suggests that overlay is in good shape Current roadmap suggests that overlay is in good shape

because precision for box – in – box targets meets ITRS because precision for box – in – box targets meets ITRS guidelinesguidelines

– Step and Scan Litho Exposure tools contribute errors Step and Scan Litho Exposure tools contribute errors not measured by scribe line targetsnot measured by scribe line targets

– Across die overlay issues are not captured by box –in – Across die overlay issues are not captured by box –in – box target data analysisbox target data analysis

• 2005 rewrite will capture these issues2005 rewrite will capture these issues


FEP Metrology:FEP Metrology:Increasing Emphasis on Areas beyond High kIncreasing Emphasis on Areas beyond High k

• Increase in Mobility by using local stressing of transistors –

Call for stress metrology by FEP

• Metal Gates increasingly important

• New transistor designs are already past R and into D.

Example: FIN-FETs require metrology

• Strained SOI, GeOI considered longer term substrates

• Crystal Defect mapping including on patterned wafers

metrology requirement for new substrates

• Mobility measurements are key


Stress Measurement from Stress Measurement from transistor to wafertransistor to wafer

Wafer Bow

Die Level Stress

Transistor Level Stress

Micro-Area Level Stress

Nano-Raman and CBED

Micro-Raman, XRD

Die level flatness Laser InterferometryNew Interferometry Method

Laser Interferometry, New Interferometry

Trend : Use Modeling to connect what you can Trend : Use Modeling to connect what you can measure with what you need to know measure with what you need to know Example: Metrology of Strained Channel DevicesExample: Metrology of Strained Channel Devices

MD Giles, et. al., VLSI Symposium 2004


2005 Interconnect Activities2005 Interconnect Activities

• Porous low k is being overshadowed by the need to lower k value of barrier layer and etch stops for 45/32 nm node.

• Long term solution for interconnect is ambiguous.


New Comments on New Comments on Interconnect Metrology Interconnect Metrology

• 3D CD especially Sidewall Roughness for trench/via

are critical needs

• In Process Development, LER is an important figure of merit for sidewall and AFM can give sidewall/via roughness vs depth as well as trench CD and profiles which provide important control for etch processes

• Need metrology for thickness and uniformity for hard mask above low after CMP – how is erosion pattern dependent


ERD and ERMERD and ERMPremise: Aberration corrected TEM/STEM Premise: Aberration corrected TEM/STEM needed for nano-electronicsneeded for nano-electronics

• Latest TEM and STEM results show improved imaging for sub 0.1 nm beams.

• We have not reached the limit where improving beam diameter does not improve imaging

• Nanowires and nanotubes serve as ideal systems to test theoretical and experimental understanding of beam propagation and image formation. - reduced stresses and amorphous films on the surface


Concept Proven : Aberration CorrectionConcept Proven : Aberration Correction

Before After

STEM – Batson, Dellby, and Krivanek, Nature 418, 617

(2002) Si(110)

HR-TEM – Jai, Lentzen, and Urban, Microsc. Microanal.

10, 174, 2004. SrTiO3


ConclusionsConclusions

• CD Measurement improvements show a path to the 32 nm Node

• Propose definition for LWR and including LER

• Transistor channel engineering requires Stress and Mobility Measurement

• Interconnect requires Sidewall Measurements for barrier/seed and low trench


AcknowledgementsAcknowledgements

• David Bell and his 2003 M&M paper on nanowire TEM

• Christian Kiselowski

• Dave Muller

• Steve Pennycook

• Suzanne Stemmer


Change in Transistor BehaviorChange in Transistor Behavior

1.E+00

1.E+02

1.E+04

1.E+06

1 100 10000

L (nm)

Idsa

t, I0

(u

A/u

m)

I0 (long chan)

I0 (velocity saturation) chan)

Actual Idsat (uA/um)


Why measure CD for NanoTransistorsWhy measure CD for NanoTransistors

= Cload VDD / Idsat

1. CD impacts Capacitance C

A = Lg x WDopant Conc.2. CD impacts Threshold Voltage

Likharev has shown that below 10 nm CD, Threshold Voltage is very

sensitive to CDAt CD = 5 nm

Process range is 0.2 nm ~ 1 atom


Red moves back in? for Litho Red moves back in? for Litho Metrology Technology RequirementsMetrology Technology Requirements

2005 2007 2010 2013 2016 2018 2020

Technology Node 80 nm 65 nm 45 nm 32 nm 22 nm 18nm 14 nm


80 65 45 32 22 18 14Lithography MetrologyPrinted Gate CD Control (nm)Allowed Litho Variance = 3/4 Total Variance of physical gate length

2.8 2.2 1.6 1.1 0.8 0.6 0.5

Wafer CD Tool 3 Precision P/T=0.2 for Printed and Physical Isolated Lines

0.6 0.4 0.3 0.2 0.2 0.1 0.1

Wafer CD metrology tool precision (nm) * ( P/T=.2 for dense lines**)

2.0 1.6 1.1 0.8 0.5 0.4 0.3

Line Width Roughness (nm) <8% of CD 2.6 2.0 1.4 1.0 0.7 0.6 0.5

Precision for LWR 0.5 0.4 0.3 0.2 0.1 0.1 0.1

Overlay Control (nm) (mean +3 ) 32.0 23 16 11 7Overlay Metrology Precision (nm) P/T=0.1 3.2 2.3 1.6 1.1 0.7 0


2005 Potential Solution Assessments2005 Potential Solution Assessments• Conflicting Reports on high keV CD-

SEM Damage• Impact of Metal Gate on CD-SEM and

Scatterometry – Metal Dependent• Impact of Gate thickness on CD

Measurement for end of roadmap• New Method identified as potential

solution – CD-SAXS (NIST Wen-li Wu)


FEP : Non-Classical CMOS MetrologyFEP : Non-Classical CMOS Metrology2005 2007 2010 2013 2016 2018 2020

Technology Node 80 nm 65 nm 45 nm 32 nm 22 nm 18nm 14 nmDriver


80 65 45 32 22 18 14

Front End Processes Metrology MPU

High Performance Logic EOTequivalent oxide thickness (EOT) nm

1.2 0.9 0.8 0.6 0.5 0.4 MPU

Logic Dielectric EOT Precision 3 (nm) 0.0048 0.0036 0.0032 0.0024 0.002 0.0016

Starting silicon layer thickness(Fully Depleted) (tolerance ± 5%, 3s) (nm)

21–39 18–33 15–19 14–16 13–14 12–14 MPU

SOI Si Thickness Precision (3s in nm) 0.105 0.09 0.075 0.07 0.065 0.06

Buried oxide (BOX) thickness(Fully Depleted) (tolerance ± 5%, 3s) (nm)

56–94 38–64 26–44 18–32 14–22 10–18 MPU

SOI BOX Thickness Precision (3s in nm) 0.28 0.19 0.13 0.09 0.07 0.05 MPU

Gate electrode thickness (nm) 37–34 25–50 18–36 13–26 9–18 7–14

Electrode Thickness Precision (nm)assume 5% 3s process range

0.185 0.125 0.09 0.065 0.045 0.035 MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

15 10 7 5 4 MPU


FEP Metrology QuestionsFEP Metrology Questions• FINFET Metrology needs?

– Doping– corner rounding makes FIN fully depleted with thicker FIN– Gate Dielectric Thickness– Timing schedule is ?? 2005 – FIB cross-section accuracy issues.

• Particles on 450 mm wafer • 1mm edge exclusion• Local Strain• High k Gate stack (EOT, k, thickness)• SOI/BOX• Gate workfunction


High Volume ICs use CMOS High Volume ICs use CMOS

w/ Locally Strained Siw/ Locally Strained Si Strained Si substrates not usedStrained Si substrates not used

PMOS Compressive Strain

increased hole mobility

45 nm NMOS Tensile Stress SiN Layer

increased electron mobility

From T. Ghani, et. al., IEDM 2003, p 978. Courtesy Intel


Gaps in Interconnect Metrology

• VOID Detection in Copper vias & lines now based on 1/10 via diameter

• Quality of Barrier/Seed on sidewalls

• Killer Pore Detection in Low

• Non destructive metrology for adhesion and (eff) (at operating freq.) for patterned wafers

Technology Node 80 nm 65 nm 45 nm 32 nm 22 nm 18nm 14 nm


80 65 45 32 22 18 14

Interconnect Metrology

Barrier layer thick (nm) 10 7 5 3.5 2.5 2

Void Size for 1% Voiding in Cu Lines 8.5 6.7 4.8 3.4 2.4 1.9

Detection of Killer Pores at (nm) size 8.5 6.7 4.8 3.4 2.4 1.9

DRAFT – Work In Progress - NOT FOR PUBLICATION 12-13 April 2005 – ITRS Public Conference...

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