DPWM

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 5, MAY 2012 2515

Synchronous FPGA-Based High-ResolutionImplementations of Digital Pulse-Width Modulators

Denis Navarro, Oscar Lucıa, Member, IEEE, Luis Angel Barragan, Jose Ignacio Artigas, Isidro Urriza,and Oscar Jimenez, Student Member, IEEE

Abstract—Advantages of digital control in power electronicshave led to an increasing use of digital pulse-width modulators(DPWM). However, the clock frequency requirements may exceedthe operational limits when the power converter switching fre-quency is increased, while using classical DPWM architectures.In this paper, we present two synchronous designs to increase theresolution of the DPWM implemented on field programmable gatearrays (FPGA). The proposed circuits are based on the on-chip dig-ital clock manager block present in the low-cost Spartan-3 FPGAseries and on the I/O delay element (IODELAYE1) available in thehigh-end Virtex-6 FPGA series. These solutions have been imple-mented, tested, and compared to verify the performance of thesearchitectures.

Index Terms—Field programmable gate arrays (FPGA), powerconversion, pulse-width modulated power converters.

I. INTRODUCTION

D IGITAL pulse-width modulators (DPWMs) have becomea basic building block in digital control architectures

of any power converter [1]–[7]. The DPWM frequency ismainly determined by the power converter operating condi-tions, whereas the DPWM resolution determines the accuracyin the output voltage/current control. As a consequence, theDPWM resolution has a direct impact in the power converterperformance.

Traditional DPWM implementations are based on countersand comparators, which generate the power converter gatingsignals according to several predefined thresholds [8]–[14]. Forthese designs, the minimum on-time step is equal to the coun-terclock period. Its equivalent number of bits nDPWM is

nDPWM = log2

(fCLK

fSW

)(1)

where fSW is the DPWM frequency and fCLK is the counterclockfrequency. Nowadays, power converters are evolving toward de-signs with higher switching frequencies in order to reduce the

Manuscript received February 8, 2011; revised July 13, 2011 and Au-gust 29, 2011; accepted October 20, 2011. Date of current version February27, 2012. This research was supported in part by the Spanish MICINN un-der Project TEC2010-19207, Project CSD2009-00046, Project IPT-2011-1158-920000, and the FPU grant AP2010-5267, and by the Bosch and Siemens HomeAppliances Group. Recommended for publication by Associate Editor L. M.Tolbert.

The authors are with the Department of Electronic Engineering andCommunications, University of Zaragoza, Zaragoza 50018, Spain (e-mail:[email protected]; [email protected]; [email protected]; [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2173702

size of inductors and capacitors. Besides, for the digital imple-mentation, the number of bits nDPWM has to be higher than theA/D converter resolution to avoid limit cycling [15]–[17]. Asa consequence, an unfeasibly high clock frequency can result,increasing the complexity and the cost of the final implementa-tion [18].

Moreover, recent developments in semiconductor technol-ogy enable the use of higher switching frequencies throughSiC [19] and GaN [20] power devices. This allows the designof power converters with reduced size and cost, and improveddynamic behavior and power density, as shown in [21] and [22].However, these designs require high-frequency high-resolutionPWMs (HRPWMs) in order to take the most of the powerconverter.

Another field of application for HRPWMs is the dc–dc con-verters, where either the output voltage [voltage regulator mod-ules (VRMs)], the duty cycle for output-power control [23], orthe switching delay mismatch between power devices [24], [25]need to be accurately tuned. As a conclusion, the evolution ofboth power electronics and digital control techniques makes thedevelopment of higher resolution DPWMs [26] necessary.

To overcome this problem, different solutions have been pro-posed depending on whether the digital controller is imple-mented on a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field programmable gatearray (FPGA).

In the case of DSPs, some of them include HRPWM periph-erals [27]. The HRPWM module extends the time resolutioncapabilities of the conventional PWM allowing a minimum timestep that is a fraction of the system clock.

Besides, several architectures have been proposed for IC im-plementation [28]–[30]. They are usually based on a tappeddelay line in combination with a multiplexer [28] or a hybridcounter/delay line [30].

Several FPGA-based solutions have also been proposed inthe literature [31]–[38]. One common solution is to use a coarseresolution counter-based stage plus one or several on-chip digitalclock manager (DCM) blocks. The PWM signal is set at thebeginning of the counter period, and it is reset after a givennumber of clock cycles plus a certain fraction of the clockperiod established by the DCM.

Apart from [35] and [38], the circuits previously publishedfor delaying the reset signal are not fully synchronous. Asyn-chronous circuits make harder to perform static timing analysisand can result in glitching since controlling the logic and routingdelays in an FPGA is more difficult than in ASIC implementa-tions. A synchronous design, therefore, improves the reliability

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2516 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 5, MAY 2012

TABLE IHRPWM ARCHITECTURE COMPARISON

of the circuit and eases the design process. Besides, it makes thedesign more independent of the technology, easing the designportability.

In Table I, a brief comparison of the FPGA-based architec-tures classified according to the coarse counter frequency, theachieved resolution, and the number of paths to manually equi-librate is given. The higher the number of paths to equilibrateis, the harder the design of a monotonic DPWM is. Besides,it is pointed out if they are fully synchronous and glitch-freedesigns, due to the combinational circuit usage.

The aim of this paper is to propose two fully synchronoushigh-resolution DPWM architectures in order to avoid the needof using unfeasible high clock frequencies, providing a moreconvenient final implementation. Both of them are based onthe resources available in modern FPGAs. The first proposedarchitecture, presented in [39], is a generalization of the DCM-based circuit in [35], and it allows operating the circuit at higherclock frequencies [39]. The second proposal is based on theI/O delay element (IODELAYE1) available in the Virtex-6 FP-GAs, and it provides higher resolution with a straightforwardimplementation.

This paper is organized as follows. The proposed high-resolution DPWM architectures using DCM blocks andIODELAYE1 blocks are explained in Sections II and III, respec-tively. The experimental results for the proposed architecturesare shown in Section IV. Section V includes further discussionand some guidelines for the architecture selection. Finally, theconclusions of this study are drawn in Section VI.

II. HIGH-RESOLUTION DPWM ARCHITECTURE USING DCMBLOCKS

The key of this architecture is the on-chip DCM block pro-vided in almost every state of the art FPGA (see Fig. 1). Thefollowing DCM clock management features [40] will be used.

1) Phase shifting: The DCM provides four phase-shiftedclock signals derived from the source clock CLKIN. Inaddition to CLK0 for zero-phase alignment to the CLKINsignal, the DCM also provides the CLK90, CLK180, andCLK270 outputs for 90◦, 180◦, and 270◦ phase-shiftedsignals, respectively. Besides, all the outputs of the DCMcan be phase shifted with finer resolution.

2) Frequency synthesis: The DCM can generate a wide rangeof output clock frequencies (CLKFX output port), per-forming clock frequency division and multiplication.

Besides phase shifting, the DCM is able to condition the clockinput CLKIN in order to obtain clock outputs with 50% duty

Fig. 1 Simplified pinout description of the DCM block.

Fig. 2. Fixed fine phase shifting effect.

cycle. The clock feedback signal CLKFB is used to compareand lock the output signals with the input CLKIN signal.

The fine phase shifting can be fixed (specified at design timeand set during the FPGA configuration process) or variable. It isset by means of the DCM attribute PHASE_SHIFT, an integerin the range [−255, +255]. Fig. 2 shows the fine phase shifteffects in the fixed mode of operation. A phase-shifted outputwith a resolution of (1/256)th of the input clock period can beobtained.

The variable phase-shifting feature has been used in [33].However, this operating mode requires several clock cycles tochange the duty cycle, degrading the dynamic performance.Besides, an asynchronous circuit is used to divide the clockcycle into four quadrants. In this paper, a fully synchronousdesign with fixed phase shifting is proposed.

A. First Approach

In order to introduce the proposed DCM-based high-resolution DPWM architecture, let us consider a first versionto obtain a 2-bit resolution increase (see Fig. 3). This architec-ture is basically the one presented in [35].

NAVARRO et al.: SYNCHRONOUS FPGA-BASED HIGH-RESOLUTION IMPLEMENTATIONS OF DIGITAL PULSE-WIDTH MODULATORS 2517

Fig. 3. DCM-based HRPWM first approach.

In this first version, the quadrant phase-shifted outputs of asingle DCM are used. The duty cycle command dc(m:0) hasm+1 bits, ranging from m to 0, and the counter “CNT” hasm−1 bits. “CLRD” signal is set when the m−1 most-significantbits (MSBs), dc(m:2), are equal to CNT; and SETD signal is setwhen CNT is equal to zero and dc(m:2) is different from zero.

Fig. 4 shows how the circuit works with m = 4, and dc= “10010”. Basically, when the counter CNT is equal to them−1 MSBs of the duty command dc, signal CLRD activates.The resulting pulse is captured in the next clock cycle by FF0,and phase shifted 90◦, 180◦, and 270◦ by flip-flops FF1, FF2,and FF3, respectively. These four FFs implement a multiphasesynchronous circuit [41]. The two least-significant bits (LSBs)of the duty command are used by the multiplexer to select thephase-shifted signal that clears the SR latch.

The advantage of this proposal in relation to others is thatthe digital circuit that generates the reset of the SR latch issynchronous. The use of asynchronous circuits to reset the latchmakes harder to calculate timing using static timing analysis andcan result in glitching since controlling the logic and routing de-lays in an FPGA is more difficult than in ASIC implementations.The next section presents an improved and scalable architecturein order to improve the HRPWM resolution.

B. Generalization of the DCM-Based Architecture

The previous architecture can be scaled to enhance theHRPWM resolution. Let n = m + k be the bits of the dutycycle command dc, with k≥ 2. Basically, the proposed circuitis made up of a synchronous m-bit counter, r DCMs, p = 4×redge-triggered flip-flops, a p-to-1 multiplexer, and an SR latchwhose output is the PWM signal. The modulus of the counter isconfigurable.

The CLRD signal is set when the counter is equal to them MSBs of dc. The SETD signal is set when the counteris zero and dc is different from zero. These signals are usedto generate the SET and RESET signals that control the SRlatch.

The counter and all DCMs are clocked by the same input clocksignal “CK.” Quadrant phase-shifted outputs CLK0, CLK90,CLK180, and CLK270 of DCMs are used to generate a set of pphase-shifted clocks {CKi} with 0 ≤ i < p. All clock signalsCKi have the same period TCK with 50% duty cycle. CKi isphase-shifted TCK /p time with respect to CKi−1 [see Fig. 5(a)].The fine phase shifting in the fixed mode shifts the phase ofall DCM output signals by a fixed fraction of the input clockperiod. Being the minimum phase shift 1/256 of TCK (k ≤ 8),


Fig. 4. DCM-based HRPWM operation with dc = “10010.”

Fig. 5. (a) Phased clock signals. (b) Multiphase synchronous circuit.

the phase-shift value for DCMj must be set to j×64/r with 0 ≤j < r.

The p flip-flops [see Fig. 5(b)] implement a multiphase syn-chronous circuit. FFi is triggered by the rising edge of CKi .A p-to-1 multiplexer uses the k LSBs of dc to select the CLRi

signal that clears the SR latch. CLRi is delayed by a fraction1/p of TCK with respect to CLRi−1 . In order to improve speed,

the circuit is designed, such as the minimum allowable delay forpaths, in which the source and destination clocks are different,is TCK /2, regardless the phase number. By doing so, the max-imum clock frequency is not limited by the multiphase circuitbut for the DCM, and it can be easily scaled to the required pnumber. In the circuit shown in Fig. 5(b), the period constraintis less restrictive than in the previous design, and a higher clockfrequency can be achieved:

tp max (FFi) + tp max (net) + tSU(FFp/2+i

)

<TCKi

2− δmax

(CKi ,CKp/2+i

)(2)

where tp max (FFi) and tSU(FFp/2+i

)are the maximum clock-

to-output propagation time and the setup time of a flip-flop,respectively; tpmax (net) is the routing delay, TCK0 /2 is the nom-inal time difference between rising edges of CK0 and CK2, andδmax (CK0, CK2) is the maximum difference in the arrival timeof the rising edges of CK0 and CK2 in relation to its nominalvalue.

For a particular FPGA series, the value of p is constrainedby the number of DCM blocks available, the number of globalclock lines that each DCM block can drive up, and the need toensure that the routing delay of the multiplexer inputs is lessthan TCK /p for a monotonic behavior.

C. Implementation

This section describes an implementation example carried outto show the feasibility of the DCM-based HRPWM architectureproposed in this study. As the implementation depends on theFPGA, let assume that the high-resolution DPWM is imple-mented in the Xilinx XC3S500E Spartan-3E FPGA of the S-3EStarter Kit board by Digilent. This board includes a 50-MHzclock oscillator that is used as the input clock.

As the FPGA has four DCMs, the parameter k can be up to 4.As an example, Fig. 6 shows an implementation with m = 8,


Fig. 6. Implemented high-resolution DPWM with m = 8 and k = 3.

and k = 3. It has been described in VHDL. DCMx4 multipliesits input clock frequency by 4. The CLKFX output of DCMx4 isconnected to the input clock of the counter, DCM0 and DCM1 .

The binary counter has 8 bits, and SETD and CLRD signalsare generated from the counter output and the eight MSBs of dcas explained earlier. FFa and FFb store these signals. Negative-edge-triggered flip-flops FFc and FFd avoid malfunctions due tothe phase offset between CK and CK0 (±200 ps max. accordingto the data sheet).

DCM0 and DCM1 generate eight phased clocks {CK0 ,. . .,CK7}. PHASE-SHIFT attribute of DCM0 is set to 0. DCM0generates clocks CK0 , CK2 , CK4 , and CK6 . PHASE-SHIFT at-tribute of DCM1 is set to 32, and its outputs are shifted 32/256of TCK . DCM1 generates clocks CK1 , CK3 , CK5 , and CK7 . Inthe implementation step of the design flow, DCM0 and DCM1are manually placed at DCM_X0Y0 and DCM_X1Y0, respec-tively, in order to be close to each other and reduce routing de-lays. These two DCMs can drive up to four global clock lines.Then, the circuit must work with the rising and falling edges ofonly four phased clocks {CK0 , CK1 , CK2 , CK3}, and FF4, FF5,FF6, and FF7 must be negative-edge triggered. This introducesnonlinearity in the on-time step due to duty-cycle variation but

this effect cannot be solved due to the routing architecture ofthis FPGA.

For this implementation, the maximum clock frequency islimited to 200 MHz, which is the maximum operating frequencyfor the CLK90 and CLK270 DCM outputs according to theFPGA datasheet. However, it is important to note that if therewere paths in the implementation in which the difference be-tween active clock edges of source and destination flip-flopswere lower than the one present in this design (TCK /2), the tim-ing constraint would be more restrictive than the one expressedin (2) and the maximum clock frequency would be reduced. Forinstance, a clock difference of TCK /4, as it occurs in Fig. 3,would lead to the 168-MHz maximum operating frequency. Inthis case, the multiphase circuit would limit the operation in-stead of making the most of the FPGA DCM resources.

The proposed architecture can also be implemented usingthe high-end Virtex-6 FPGA series. In these FPGAs, the DCMblock has been replaced by the mixed-mode clock manager(MMCM), which provides improved functionalities and jitterperformance. The MMCM provides output signals with a 45◦

phase shift. The DCM0 and DCM1 can therefore be replacedby a single MMCM, and a higher resolution can be achieved


Fig. 7. Simplified pinout description of (a) I/O delay element IODELAYE1and (b) IDELAYCTRL block.

using this architecture, as it is shown in the experimental results.In spite of this, Virtex-6 FPGAs provides additional resources,which allow obtaining better HRPWM resolution. In the nextsection, we present the proposed architecture to implement theHRPWM based on the IODELAYE1 block.

III. HIGH-RESOLUTION DPWM ARCHITECTURE USING

IODELAYE1 BLOCKS

The second approach uses the I/O delay element(IODELAYE1) [42] present in Virtex-6 series FPGAs. TheIODELAYE1 block allows generating a signal (DATAOUT)delayed by a certain number of tap delays with respect to theinput (DATAIN). The IODELAYE1 tap resolution is given byttap = 1/(32 · 2 · fCK REF), providing a fine delay-time td ad-justment. The reference frequency fCK REF is set through theblock attribute REFCLK, and it can be either 200 ± 10 or300 ± 10 MHz. Besides, it provides additional ports to config-ure the increment/decrement mode (CE), increment/decrementdelay (INC), and reset (RST), which allows controlling the de-sired delay. These signals are synchronized with the clock sig-nal C. When using the IODELAYE1 block, the IDELAYCTRLblock must be also instantiated. This block continuously cali-brates the delay elements in order to reduce the influence of pro-cess, voltage, and temperature variations by using the suppliedREFCLK. Fig. 7 shows the pinout description of the IODE-LAYE1 and IDELAYCTRL blocks.

The IODELAYE1 block offers three different operationalmodes when operating in the unidirectional input delay config-uration, depending on the mechanism used to select the numberof delay taps.

1) Fixed: The number of delay taps is predefined through theblock attributes and it cannot be changed during operation.

2) Variable: The number of delay taps can be dynamicallychanged after configuration through the control signalsCE and INC. When the enable increment/decrement sig-nal (CE) is activated, the number of delay taps increasesor decreases depending on whether the INC signal is acti-vated or not. If the reset signal RST is activated, the delayvalue is reset to a predefined value.

3) Loadable variable: This mode has the same functionalityas the variable mode. In addition to this, it allows loadingthe delay value through the 5-bit input CNTVALUEIN.

When in this mode, the IODELAYE1 reset signal resetsthe delay value to a value set by the CNTVALUEIN, asshown in Fig. 8. The delay time is, therefore, calculated astd = ttap · CNTVALUEIN, and the current delay valuecan be read in the CNTVALUEOUT signal.

A. Proposed Architecture

Fig. 9 shows the proposed implementation for an m+1-bitHRPWM. Basically, the proposed circuit is made up of a syn-chronous m−4 bit counter, an IODELAYE1 block, two edge-triggered flip-flops, an MMCM, and an SR latch whose output isthe PWM signal. The main difference with the previous proposalis that the multiphase synchronous circuit used to generate thesignal RESET is replaced by the IODELAYE1 block, makingthe implementation easier.

Signals SETD and CLRD are generated as previously ex-plained by comparing the counter output CNT with the mostm−5 significant bits of the duty command dc(m:5). FFa andFFb are placed in order to avoid the glitches that may be presentin the output of the comparator.

For this implementation, the loadable variable mode forthe IODELAYE1 block is used. The IODELAYE1 block al-lows, therefore, delaying the input signal through a 5-bit valueCNTVALUEIN updated when the NVALUE signal is activated,which has to be synchronized with the C clock. Considering thatthe maximum 32-tap delay covers half a period of CK_REF,a clock that doubles the CK_REF frequency is required toclock the counter. These clock signals are generated throughthe MMCM using as a reference the board base clock CK. Theoutput frequency for the MMCM output i is set through its at-tributes M, D, and Oi as fCKOi

= M/(D · Oi). In addition tothis, the IDELAYCTRL is instantiated in order to autocalibratethe delay tap as previously explained.

Fig. 10 shows the basic operation of the proposedIODELAYE1-based HRPWM architecture with dc =“10010011.” The CLRD signal is activated when dc(7:5) =CNT(7:5) = “100” = 4. The resulting pulse is captured in thenext clock cycle by FFb, which generates the input signal for theIODELAYE1 block DATAIN. The IODELAYE1 block gener-ates the RESET signal by delaying the CLR signal a number oftap cycles given by dc(4:0) = “10011” = 19. This signal clearsthe SR latch to generate the desired PWM signal.

B. Implementation

The proposed IODELAYE1-based HRPWM architecturehas been implemented in a Xilinx Virtex-6 XC6VLX240T-1FFG1156 in the ML605 Evaluation Kit featuring a 200-MHzoscillator that is used as the input clock.

The REF_CK clock frequency for the IODELAYE1 blockhas been set to 200 MHz, achieving a resolution ttap = Δton =(1/ (32 · 2 · fCK REF)) = 78 ps. Therefore, the CK2 clock fre-quency for the counter and the flip-flops is 400 MHz. Theseclock signals are generated through the MMCM configured withM = 8,D = 2, O1 = 2, and O2 = 4. The proposed design canoperate correctly with 32-bit counters, allowing generating upto 10-s-width pulses with 78-ps resolution. If required by the


Fig. 8. IODELAYE1 operation in the loadable variable mode.

Fig. 9. Implemented high-resolution DPWM with the IODELAYE1 block.

Fig. 10. IODELAYE1-based HRPWM operation with dc = “10010011.”

application, the tap resolution could be improved up to 56 ps byselecting a 300-MHz clock for the IODELAYE1 block.

IV. EXPERIMENTAL RESULTS

This section presents the main experimental results for theproposed DCM-based and IODELAYE1-based HRPWM archi-tectures. The DPWM output has been assigned to the SMAconnector of the development boards, and connected through acoaxial cable to a Tektronix DPO7354 oscilloscope (3.5-GHzbandwidth) as can be seen in Fig. 11. The DPWM signal fre-quency and duty cycle have been selected for test purposes; so,the complete pulse and minimum Δton can be captured andmeasured in a single oscilloscope screen.

Fig. 12 shows the pulse width and pulse-width increment forthe DCM-based HRPWM architecture. The values have been

measured with the oscilloscope for nine consecutive duty com-mands differing in one LSB from each other. This way, thedifferent values of the three LSBs of the duty cycle are tested.The monotonic behavior can be noticed. The expected on-timestep Δton was 625 ps. There is an offset due to the fact that theRESET signal goes through a multiplexer and the SET signaldoes not (as seen in Fig. 6). It could have been reduced as in [35]or by triggering FFe with the rising edge of CK2, but normallythe offset will be compensated by the digital controller. Fig. 13shows the traces of the DCM-based DPWM pulses correspond-ing to the duty commands shown in Fig. 12 from the maximumduty (top) to the minimum (bottom).

As has been explained in Section II, the DCM-based archi-tecture can also be implemented by using the MMCM blockspresent in Virtex-6 FPGAs. This approach has been tested usinga 400-MHz clock for the MMCMs, which leads to a 312-ps


Fig. 11. Experimental setup for measurements: S-3E Starter Kit board with (a)Xilinx XC3S500E and (b) ML605 Evaluation Kit with Xilinx XC6VLX240T.

Fig. 12. DCM-based HRPWM architecture performance for duty commandsfrom “10000” to “11000.” (a) Pulse width. (b) Pulse-width increment.

resolution. The experimental results including the pulse widthand pulse-width increment for the MMCM-based architectureare shown in Fig. 14. These results show a lower deviation thanthe DCM-based architecture, mainly due to the improvement ofclocking jitter in Virtex-6 FPGAs.

The experimental results for the IODELAYE1-basedHRPWM architecture are shown in Fig. 15(a) and (b), wherethe pulse width and pulse-width increment are shown, respec-tively. These measurements have been also performed for 32consecutive values of the duty command. Each duty commanddiffers in one LSB from each other, which correspond to onetap delay of the IODELAYE1 block. The expected on-time stepΔton for this architecture is 78 ps. The results show a mono-tonic behavior and a more stable value of the on-time step than

Fig. 13. Measured DPWM pulses with horizontal scale 2.5 ns/div, from (a)duty command “11000” to “10100”, and (b) “10100” to “10000” for the DCM-based architecture.

in the previous implementation. The nonmonotonic behavior ofthe last point “100000” is due to the jitter in the delay chaininside the IODELAYE1 block. The datasheet for the Virtex-6FPGAS specifies a ±5-ps-per-tap jitter; so, the obtained resultsare within the device specifications. This may be solved by us-ing only 30 taps, instead of the 31, and using the appropriatescale factor as explained in [27]. Fig. 16 shows the traces of theIODELAYE1-based DPWM pulses for a four-tap increment.

V. DISCUSSION

This paper details two HRPWM implementations based onthe DCM and the IODELAYE1 blocks available in modernFPGAs. The designer should select the most suitable one ac-cording the specifications of resolution, cost, and number ofPWM outputs. Some guidelines are given in the following.

In Table II, we summarize the characteristics of the proposedHRPWM architectures. Compared to the previous implementa-tions (see Table I), the proposed architectures achieves higherresolution, while keeping a fully synchronous design. Besides,these are glitch-free designs, which improve the circuit reliabil-ity, and the number of paths to equilibrate in order to achieve amonotonic behavior is minimized.

The DCM-based architecture uses the DCM blocks presentin almost every modern FPGA. Unlike other high-resolutionarchitectures proposed in the literature, the maximum clock


Fig. 14. MMCM-based HRPWM architecture performance for duty com-mands from “10000” to “11000.” (a) Pulse width. (b) Pulse-width increment.

frequency is determined by the DCMs instead of the multiphasecircuit. This allows an efficient HRPWM implementation forlow-cost systems. As the number of DCM blocks is limited, thisarchitecture is recommended for systems requiring a few PWMoutputs.

In contrast, the IODELAYE1-based architecture achieves ahigher resolution by using the resources present in the high-endVirtex-6 FPGA series. This architecture features a straightfor-ward implementation as it uses a single block instead of themultiphase circuit. The architecture is simplified and there isno need to equilibrate the propagation paths. One of the mainadvantages of this proposal compared to the previous one isthat it allows generating as many PWMs as needed, as each I/Otile in Virtex-6 FPGAs contains two IODELAYE1 blocks. Thisarchitecture is, therefore, recommended for systems requiringhigher resolution or a high number of PWM outputs.

The DCM-based architecture can also be implemented in theVirtex-6 FPGA series using the MMCM blocks available. How-ever, the increased cost compared to the Spartan-based solutiondoes not justify it, as the IODELAYE1 block achieves betterperformance.

If we consider the ratio η = 1/f clk,max · Δton,min asa measure of the architecture efficiency, the DCM andIODELAYE1-based proposals can be compared. The DCM-based architecture obtains ηDCM = 1/(200MHz · 625 ps) = 8,whereas the IODELAYE1-based architecture obtains ηDCM =

Fig. 15. IODELAYE1-based HRPWM architecture performance for dutycommands from “000000” to “100000.” (a) Pulse width. (b) Pulse-widthincrement.

Fig. 16. Measured DPWM pulses for a four-tap increment with horizontalscale 2.5 ns/div, from (a) duty command dc (5:0) “100000” to “010000”, and(b) “001100” to “000000” for the IODELAYE1-based architecture.


TABLE IIPROPOSED HRPWM ARCHITECTURES COMPARISON

1/(400MHz · 78 ps) = 32. The IODELAYE1-based architec-ture presents a four times better efficiency that leads to a morepower-efficient architecture.

VI. CONCLUSION

Advances in power electronics and digital control have madenecessary the development of high-resolution DPWMs to takethe most of either high-frequency or high-precision powerconverters. In this paper, we have proposed two novel fully-synchronous HRPWM implementations using different FPGAresources: the DCM and the I/O delay element (IODELAYE1).The DCM-based architecture can be implemented using the re-sources present in low-cost FPGAs, and the maximum clockfrequency is determined by the DCMs instead of the multiphasecircuit. On the contrary, the IODELAYE1-based architectureoffers a higher resolution and number of PWM outputs witha straightforward implementation using the high-end Virtex-6FPGAs. Both solutions are complementary and cover a widespectrum of cost/performance applications.

The proposed DCM-based and IODELAYE1-based syn-chronous architectures have been implemented on a XilinxSpartan-3E and Virtex-6 FPGA, respectively. The experimentalresults show a resolution of 625 ps for the DCM-based architec-ture, and 78 ps for the IODELAYE1-based architecture, showingthe feasibility of the proposals.

REFERENCES

[1] O. Lucıa, L. A. Barragan, J. M. Burdıo, O. Jimenez, D. Navarro, andI. Urriza, “A versatile power electronics test-bench architecture applied todomestic induction heating,” IEEE Trans. Ind. Electron., vol. 58, no. 3,pp. 998–1007, Mar. 2011.

[2] O. Lucıa, J. M. Burdıo, L. A. Barragan, J. Acero, and I. Millan, “Series-resonant multiinverter for multiple induction heaters,” IEEE Trans. PowerElectron., vol. 24, no. 11, pp. 2860–2868, Nov. 2010.

[3] F. Wang, S. Wei, D. Boroyevich, S. Ragon, V. Stefanovic, and M.Arpilliere, “Voltage source inverter,” IEEE Ind. Appl. Mag., vol. 15,no. 2, pp. 24–33, Mar./Apr. 2009.

[4] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse widthmodulator architectures,” in Proc. IEEE 35th Annu. Power Electron. Spec.Conf., Jun. 2004, vol. 6, pp. 4689–4695.

[5] S. K. Mazumder and T. Sarkar, “Optically-activated gate control for powerelectronics,” IEEE Trans. Power Electron., vol. 10, no. 26, pp. 2863–2886,2011.

[6] H. Sarnago, A. Mediano, and O. Lucıa, “High efficiency ac–ac powerelectronic converter applied to domestic induction heating,” IEEE Trans.Power Electron., 2012, to be published.

[7] O. Lucıa, J. M. Burdıo, I. Millan, J. Acero, and L. A. Barragan, “Efficiencyoriented design of ZVS half-bridge series resonant inverter with variablefrequency duty cycle control,” IEEE Trans. Power Electron., vol. 25,no. 7, pp. 1671–1674, Jul. 2010.

[8] E. Ormaetxea, J. Andreu, I. Kortabarria, U. Bidarte, I. Martınez de Alegrıa,E. Ibarra, and E. Olaguenaga, “Matrix converter protection and compu-tational capabilities based on a system on chip design with an FPGA,”IEEE Trans. Power Electron., vol. 26, no. 1, pp. 272–287, Jan. 2011.

[9] B. Cougo, T. Meynard, and G. Gateau, “Parallel three-phase inverters:Optimal PWM method for flux reduction in Intercell transformers,” IEEETrans. Power Electron., vol. 26, no. 8, pp. 2184–2191, 2011.

[10] R. K. Pongiannan, S. Paramasivam, and N. Yadaiah, “Dynamically recon-figurable PWM controller for three phase voltage source inverters,” IEEETrans. Power Electron., vol. 26, no. 6, pp. 1790–1799, 2011.

[11] L. Faa-Jeng, H. Jonq-Chin, C. Po-Huan, and H. Ying-Chih, “FPGA-basedintelligent-complementary sliding-mode control for PMLSM servo-drivesystem,” IEEE Trans. Power Electron., vol. 25, no. 10, pp. 2573–2587,Oct. 2010.

[12] O. Lucıa, I. Urriza, L. A. Barragan, D. Navarro, O. Jimenez, and J.M. Burdıo, “Real-time FPGA-based hardware-in-the-loop simulation test-bench applied to multiple output power converters,” IEEE Trans. Ind.Appl., vol. 47, no. 2, pp. 853–860, Mar./Apr. 2011.

[13] O. Lucıa, J. M. Burdıo, I. Millan, J. Acero, and D. Puyal, “Load-adaptivecontrol algorithm of half-bridge series resonant inverter for domestic in-duction heating,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 3106–3116, Aug. 2009.

[14] O. Lucıa, J. M. Burdıo, L. A. Barragan, J. Acero, and C. Carretero,“Series resonant multi-inverter with discontinuous-mode control for im-proved light-load operation,” IEEE Trans. Ind. Electron., vol. 58, no. 11,pp. 5163–5171, Nov. 2011.

[15] A. Mohammed, “Digital control of power converters,” IEEE AppliedPower Electronics Conference and Exposition, Professional EducationSeminars Workbook, Austin, TX, 2008.

[16] A. Prodic, D. Maksimovic, and R. W. Erickson, “Design and implemen-tation of digital PWM controller for a high-frequency switching dc–dcpower converter,” in Proc. IEEE Annu. Conf. Ind. Electron. Soc., 2001,pp. 893–898.

[17] A. V. Peterchev and S. R. Sanders, “Quantization resolution and limitcycling in digitally controlled PWM converters,” IEEE Trans. PowerElectron., vol. 18, no. 1, pp. 301–308, Jan. 2003.

[18] L. Corradini, A. Bjeletic, R. Zane, and D. Maksimovic, “Fully digitalhysteretic modulator for dc–dc switching converters,” IEEE Trans. PowerElectron., vol. 26, no. 10, pp. 2969–2979, 2011.

[19] J. Biela, M. Schweizer, S. Waffler, and J. W. Kolar, “SiC versus Si-evaluation of potentials for performance improvement of inverter anddc–dc converter systems by SiC power semiconductors,” IEEE Trans.Ind. Electron., vol. 58, no. 7, pp. 2872–2882, Jul. 2011.

[20] T. Nomura, M. Masuda, N. Ikeda, and S. Yoshida, “Switching charac-teristics of GaN HFETs in a half bridge package for high temperatureapplications,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 692–697,Mar. 2008.

[21] S. Ajram and G. Salmer, “Ultrahigh frequency dc-to-dc converters usingGaAs power switches,” IEEE Trans. Power Electron., vol. 16, no. 5,pp. 594–602, May 2001.

[22] A. Simon-Muela, Y. Elbasri, C. Alonso, V. Boitier, and J. L. Chaptal,“Modeling digital control laws for high-frequency VRM applications,” inProc. IEEE Power Electron. Spec. Conf., 2008, pp. 1560–1565.

[23] W. Yu, J. S. Lai, H. Ma, and C. Zheng, “High efficiency dc–dc converterwith twin-bus for dimmable LED lighting,” IEEE Trans. Power Electron.,vol. 26, no. 8, pp. 2095–2100, Jul. 2011.

[24] A. V. Peterchev, X. Jinwen, and S. R. Sanders, “Architecture and IC im-plementation of a digital VRM controller,” IEEE Trans. Power Electron.,vol. 18, no. 1, pp. 356–364, Jan. 2003.

[25] C. Carretero, O. Lucıa, J. Acero, and J. M. Burdıo, “Phase-shift con-trol of dual half-bridge inverter feeding coupled loads for inductionheating purposes,” Electron. Lett., vol. 47, no. 11, pp. 670–671, May2011.

[26] B. J. Patella, A. Prodic, A. Zirger, and D. Maksimovic, “High-frequencydigital PWM controller IC for dc–dc converters,” IEEE Trans. PowerElectron., vol. 18, no. 1, pp. 438–446, Jan. 2003.

[27] TMS320x28xx, “High-resolution pulse width modulator (HRPWM),”Reference Guide, Texas Instruments SPRU924C, Dallas, TX, 2007.


[28] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse widthmodulator architectures,” in Proc. IEEE Power Electron. Spec. Conf., Jun.2004, vol. 6, pp. 4689–4695.

[29] K. Wang, N. Rahman, Z. Lukic, and A. Prodic, “All-digital DPWM/DPFMcontroller for low-power dc–dc converters,” in Proc. IEEE Appl. PowerElectron. Conf. Expo., 2006, pp. 719–723.

[30] Z. Lukic, C. Blake, S. C. Huerta, and A. Prodic, “Universal and fault-tolerant multiphase digital PWM controller IC for high-frequency dc–dcconverters,” in Proc. IEEE Appl. Power Electron. Conf., Feb./Mar. 2007,pp. 42–47.

[31] S. C. Huerta, A. de Castro, O. Garcia, and J. A. Cobos, “FPGA-baseddigital pulse-width modulator with time resolution under 2 ns,” IEEETrans. Power Electron., vol. 23, no. 6, pp. 3135–3141, Nov. 2008.

[32] M. G. Batarseh, W. Al-hoor, L. Huang, C. Iannello, and I. Batarseh, “Seg-mented digital clock manager FPGA based digital pulse width modulatortechnique,” in Proc. Power Electron. Spec. Conf., 2008, pp. 3036–3042.

[33] A. de Castro and E. Todorovich, “DPWM based on FPGA clock phaseshifting with time resolution under 100 ps,” in Proc. IEEE Power Electron.Spec. Conf., 2008, pp. 3054–3059.

[34] J. Quintero, M. Sanz, A. Barrado, and A. Lazaro, “FPGA based digitalcontrol with high-resolution synchronous DPWM and high-speed embed-ded A/D converter,” in Proc. IEEE Appl. Power Electron. Conf. Expo.,2009, pp. 1360–1366.

[35] M. Scharrer, M. Halton, and T. Scanlan, “FPGA-based digital pulse widthmodulator with optimized linearity,” in Proc. IEEE Appl. Power Electron.Conf. Expo., 2009, pp. 1220–1225.

[36] A. de Castro and E. Todorovich, “High resolution FPGA DPWM basedon variable clock phase shifting,” IEEE Trans. Power Electron., vol. 25,no. 5, pp. 1115–1119, May 2010.

[37] M. G. Batarseh, W. Al-Hoor, L. Huang, C. Iannello, and I. Batarseh,“Window-masked segmented digital clock manager-FPGA-based digitalpulse-width modulator technique,” IEEE Trans. Power Electron., vol. 24,no. 11, pp. 2649–2660, Nov. 2009.

[38] M. Scharrer, M. Halton, T. Scanlan, and K. Rinne, “FPGA-based multi-phase digital pulse width modulator with dual-edge modulation,” in Proc.IEEE Appl. Power Electron. Conf. Expo., 2010, pp. 1075–1080.

[39] D. Navarro, L. A. Barragan, J. I. Artigas, I. Urriza, O. Lucıa, andO. Jimenez, “FPGA-based high-resolution synchronous digital pulsewidth modulator,” IEEE Int. Symp. Ind. Electron., pp. 2771–2776, 2010.

[40] Spartan-3 Generation FPGA User Guide, UG331 (v 1.5), Xilinx, SanJose, CA, 2009, ch. 3.

[41] R. Andrew and S. Poriazis, “Design of synchronous circuits with multipleclocks,” in Proc. IEEE Int. Symp. Circuits Syst., 1995, vol. 2, pp. 933–936.

[42] Virtex-6 FPGA SelectIO Resources User Guide, UG361 (v 1.3), Xilinx,San Jose, CA. 2009, ch. 2.

Denis Navarro received the M.Sc. degree in mi-croelectronics from the University of Montpellier,France, and the Ph.D. degree from the Universityof Zaragoza, Zaragoza, Spain, in 1987 and 1992,respectively.

Since September 1988, he has been an Asso-ciate Professor with the Department of ElectronicEngineering and Communications, University ofZaragoza. He is involved in the implementation ofnew applications of ICs. In 1993, he designed thefirst SPARC microprocessor in Europe. His current

research interests include computer-aided designs for very large scale integra-tion, low power application-specified IC design, and modulation techniques forpower converters.

Dr. Navarro is a member of the Aragon Institute for Engineering Research.

Oscar Lucıa (S’04–M’11) received the M.Sc. andPh.D. degrees in electrical engineering from the Uni-versity of Zaragoza, Zaragoza, Spain, in 2006 and2010, respectively.

He is currently an Assistant Professor with theDepartment of Electronic Engineering and Com-munications, University of Zaragoza. His main re-search interests include induction-heating applica-tions, multiple-output power converters, resonant in-verters, and digital control and modulation strategiesapplied to power converters.

Dr. Lucıa is a member of the Aragon Institute for Engineering Research.

Luis Angel Barragan received the M.Sc. and thePh.D. degrees in physics from the University ofZaragoza, Zaragoza, Spain, in 1988 and 1993, re-spectively.

He is currently an Associate Professor with the De-partment of Electronic Engineering and Communica-tions, University of Zaragoza. He has been involvedin different research and development projects on in-duction heating systems for home appliances. Hisresearch interests include digital circuits design anddigital control of inverters for induction heating ap-

plications.Dr. Barragan is a member of the Aragon Institute for Engineering Research.

Jose Ignacio Artigas received the M.Sc. and Ph.D.degrees in electrical engineering from the Univer-sity of Zaragoza, Zaragoza, Spain, in 1989 and 1996,respectively.

He is currently an Associate Professor with the De-partment of Electronic Engineering and Communica-tions, University of Zaragoza. He has been involvedin different research and development projects. Hismain research interests include digital control ofswitching converters for induction heating and theuse of information and communications technologies

to improve the quality of life.

Isidro Urriza received the M.Sc. and Ph.D. de-grees in electrical engineering from the Universityof Zaragoza, Zaragoza, Spain in 1991 and 1998,respectively.

He is currently an Associate Professor with the De-partment of Electronic Engineering and Communica-tions, University of Zaragoza. He has been involvedin different research and development projects. Hismain research interests include digital implementa-tion of modulation techniques for power converters.

Dr. Urriza is a member of the Aragon Institute forEngineering Research.

Oscar Jimenez (S’10) received the M.Sc. degree intelecommunications engineering from the Universityof Zaragoza, Zaragoza, Spain, in 2009. He is currentlyworking toward the Ph.D. degree at Department ofElectronic Engineering and Communications, Uni-versity of Zaragoza.

His research interests include the field of domes-tic induction-heating, resonant inverters, and digitalcontrol applied to power converters.

Mr. Jimenez is a member of the Aragon Institutefor Engineering Research.

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