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Minimisation of Power Dissipation During TestApplication in Full Scan Sequential Circuits Using
Primary Input Freezing
NicolaNicolici, BashirM. Al-Hashimi,andAlan C. WilliamsElectronicSystemsDesignGroup
Departmentof ElectronicsandComputerScienceUniversityof Southampton,U.K.
Abstract
This paperdescribesa new techniquefor minimisingpower dis-sipationin full scansequentialcircuits during testapplication. Thetechniqueincreasesthecorrelationbetweensuccessive statesduringshiftingin testvectorsandshiftingouttestresponsesby reducingspu-rioustransitionsduringtestapplication.Thereductionis achievedbyfreezingthe primary input part of the test vector until the smallesttransitioncount is obtainedwhich leadsto lower power dissipation.This paperpresentsa new algorithmwhich determinesthe primaryinput changetime suchthat maximumsaving in transitioncount isachieved with respectto a given testvectorandscanlatch order. Itis shown how combiningthe proposedtechniquewith the recentlyreportedscanlatchandtestvectororderingyieldsfurther reductionsin powerdissipationduringtestapplication.Exhaustiveexperimentalresultsusingcompactandnoncompacttestsetsdemonstratesubstan-tial savings in power dissipationusinga simulatedannealing-baseddesignspaceexploration. As an examplesaving of 34% in powerdissipationfor benchmarkcircuit s713 is achieved.
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1 Introduction
Performance,costandtestabilityarethemainparameterstargetedduringthesynthesisandop-
timisationphaseof integratedcircuits.Recentlytheissueof low powerdissipationhasemerged
asan importantparameterin thedesignflow [1] andhasbeeninvestigatedat differentdesign
hierarchylevels. High level power minimisationtechniques[2, 3, 4] trade-off throughput,area
andpower dissipationduring scheduling,allocationandbinding. At the logic level, two suc-
cessfulpowermanagementtechniques,basedon precomputation[5, 6] andguardedevaluation
[7] havebeenpresented.While theaboveresearchhasoutlinedsolutionsfor minimisingpower
dissipationduring the normal (functional) modeof operation,it is essentialto examinethe
powerdissipationduringthetestmodeof operation.It wasoutlinedin [8] thatpowerdissipated
duringtestapplicationis substantiallyhigherthanpowerdissipatedduringfunctionaloperation,
whichcanleadto lossof yield anddecreasethereliability of thecircuit undertest.High power
dissipationduringtestapplicationis dueto thefollowing two problems:
� correlationbetweenconsecutive testvectorsgeneratedby anautomatictestpatterngen-
erator(ATPG)is very low sincea testvectoris generatedfor a giventargetfault without
any considerationof theprevioustestvectorin thetestsequence.
� useof scandesignfor testability(DFT) techniquedestroys thecorrelationthat typically
exists betweensuccessive statesof the sequentialcircuit by allowing the applicationof
any desiredvaluesto thestatelatches.
Toovercometheproblemof highpowerdissipationduringtestapplication,apower-constrained
test schedulingalgorithm hasbeenproposedfor high performancememoriesand multichip
modules[9]. Thealgorithmis basedon a resourcegraphformulationfor thetestproblemand
testsarescheduledconcurrentlywithout exceedingtheir power ratingsduringtestapplication.
A new ATPGtool [10] wasproposedto overcomethelow correlationbetweenconsecutive test
vectorsduringtestapplication.Despiteachieving theobjectivesof safeandinexpensivetesting
of low power circuits theapproachin [10] increasedthetestapplicationtime. Furthermore,in
thecaseof sequentialcircuits,only thecombinationalpartassumingparallelscanis considered
to contribute to power dissipation. However, recentlyDabholkaret al. [11] showed that the
power dissipationin full scansequentialcircuits dependsnot only on the combinationalpart
but alsoon thesequentialpartof thecircuit. Herethe two above mentionedproblemsassoci-
atedwith low power testingaresolvedasfollows. Testvectororderingwasusedto solve the
low correlationbetweenconsecutive testvectors,while scanlatch orderingwasemployed to
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introducecorrelationbetweenconsecutive statesduringtestapplication.Furtherbenefitof the
techniqueproposedin [11] is thatminimisationof powerdissipationduringtestapplicationhas
beenachievedwithout any increasein testapplicationtime unlike [9, 10]. The techniquesin
[11] did not considertheeffect of thetiming of theprimary input partof thetestvectoron the
powerdissipationduringtestapplication.
The aim of this paperis to analyseandexploit the influenceof primary input freezingon
minimisationof powerdissipationduringtestapplication.Furthermore,theeffectof combining
theprimaryinputfreezingwith testvectorandscanlatchorderingonpowerdissipationis inves-
tigated.In section2, thepowerdissipationmodelandtheparameterswhichareaccountablefor
power dissipationin full scancircuitsduringtestapplicationaredescribed.Section3 outlines
that primary input freezinghasprofoundimpacton reducingspurioustransitionsduring test
application.New algorithmsfor exploiting all theparameterswhich leadto substantialsavings
areintroducedin section4. Experimentalresultsandconclusionsarepresentedin sections5
and6 respectively.
2 Power Dissipation During Test Application
Power dissipationin CMOS circuits canbe divided into static,shortcircuit, leakageanddy-
namicpower dissipation.Thestaticpower dissipationis negligible for correctlydesignedcir-
cuit, shortcircuit powerdissipationcausedby shortcircuit currentduringswitchingandpower
dissipatedby leakagecurrentscontributeup to 20%of thetotal powerdissipation.Theremain-
ing 80%is attributedto dynamicpowerdissipationcausedby switchingof thegateoutputs[12].
If thegateis partof a synchronousdigital circuit controlledby globalclock, it follows thatthe
dynamicpower Pd requiredto chargeanddischarge theoutputcapacitanceloadof every gate
is:
Pd� 0 � 5 � Cload
��� V 2DD � Tcyc � � NG (1)
whereCload is the loadcapacitance,VDD is thesupplyvoltage,Tcyc is theglobalclock period,
and NG is the total numberof gateoutput transitions(0 � 1 or 1 � 0). The vast majority
of power reductiontechniquesconcentrateon minimising the dynamicpower dissipationby
reducingoneor morevariablesof Pd . The supplyvoltageVDD is usuallynot underdesigner
control andglobal clock periodTcyc, or moregenerally, the systemthroughputis a constraint
ratherthanadesignvariable.Thus,node transition count
NTC � ∑f or all gates G
NG� Cload (2)
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is usedasquantitativemeasurefor powerdissipationthroughoutthepaper. It hasbeenassumed
thatloadcapacitancefor eachgateis equalto thenumberof fan-outs.Thenodetransitioncount
in scanlatchesNSL is consideredasin [11], whereit wasshown that for input changes0 � 0
and1 � 1, NSLmin� 2, whilst for inputchanges0 � 1 and1 � 0, NSLmax
� 6. Previousresearch
hasestablishedthatnodetransitioncountdependson two factors,testvectororderingandscan
latchordering,whencircuit is in thetestmode[11].
To illustratethe factorsaccountablefor power dissipationconsiderthe s27 circuit (Figure
1) from thecommonlyacceptedISCAS89benchmarkset[13]. The x0 x1 x2 x3 � areprimary
inputs, S0 S1 S2 � arethescanlatches, y0 y1 y2 � arethepresentstatelines,and z0 � is the
circuit output. The transitionson circuit data lines are describedlater in the paper. Using
theGATEST[14] ATPGtool, it hasbeenshown that5 testvectorsareneededto achieve100%
faultcoverage.Thetestvectorsare 1101011 0000000 0010010 0111111 1100010� . Foreasy
referencethey arelabelledas V0 V1 V2 V3 V4 � . Eachtestvectorconsistsof primaryinputsand
pseudoinputs(presentstatelines)in thefollowing orderx0x1x2x3y0y1y2. Assumeinitially all the
primaryandpseudoinputsaresetto 0 andusingEqn. 2 thenodetransitioncountis calculated
as NTC � 372. A detaileddescriptionfor calculatingNTC over the entire test application
period is outlined in section3. By reorderingthe test vectorsas such V0 V2 V4 V3 V1 � a
new lower valuefor nodetransitioncountis obtainedNTC � 352. This shows thatreordering
of testvectorsreducespower dissipationduring testapplicationby increasingthe correlation
betweenconsecutivetestvectors.Notethatnodetransitioncountis computedfor theentiretest
applicationperiodof n ��� m 1� m clockcycles,wheren is thenumberof testvectorsandm is
thenumberof scanlatches.Now theeffectof scanlatchorderingonpowersavingsis examined.
Considerthe reorderedtest vector set V0 V2 V4 V3 V1 � and reorderingscanlatcesas such
S0 S2 S1 � thevalueof nodetransitioncountis reducedfurtherto NTC � 328.This reduction
is dueto highercorrelationbetweensuccesivestatesduringshifting in testvectorsandshifting
out test responses.If test vector orderingand scanlatch orderingare donesimultaneously
furtherreductionin nodetransitioncountis achievedNTC � 296,for thefollowing testvector
order V0 V2 V3 V4 V1 � andscanlatchorder S2 S1 S0 � . Thisshowsthatthesetwo parameters
(scanlatchorderingandtestvectorordering)areinterrelatedwhich leadsto higherreductions
thanwheneachparameteris consideredseparetely.
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3 New Technique for Minimisation of Power Dissipation Dur-ing Test Application Using Primary Input Freezing
In this sectionthe motivation for the researchis outlined and key ideasare presented.The
influenceof primary input freezingon thereductionof spurioustransitionsandhencesavings
in thetotal numberof transitionsis demonstratedthroughdetailedexamples.
For afull scansequentialcircuit with m scanlatchesthepseudoinputpartof thetestvectoris
scannedin m clockcyclest0 to tm � 1. In thenext clockcycletm theentiretestvectoris appliedto
thecombinationallogic andthetestresponseis loadedin scanlatches.During thenext m clock
cycle thetestresponseis scannedout simultaneouslywith scanningin thenext testvector. So
far we have assumedthat thechangingof theprimary inputsx0x1x2x3 occursat time t0 which
is the beginning of scanningout the responseof the previous testvectorandscanningin the
pseudoinputsof the new test vector. From now onwardsthe testapplicationstrategy where
primary inputschangeat t0 is calledas soon as possible (ASAP). For the particularexample
in Figure1, wherethe numberof scanlatchesis 3, at timest0, t1, andt2 the scanlatchesare
in theshift modeandthevalueson the input linesof thecombinationalpartof thecircuit are
irrelevant. The valueof primary inputs is importantonly at t3 when the entire testvector is
appliedto the combinationalpart of the circuit. Thereforethe primary inputscanbe frozen
(keepthevalueof theprevioustestvector)duringt0 to t2 without affectingthetestingprocess.
To illustrate the importanceof primary input freezingconsiderthe applicationof test vector
0000000� followedby testvector 1101011� . Thecircuit datalinesaredescribedin termsof
threevalues.For examplein Figure1(a),in thecaseof primaryinputx0 thevalue0� 1� 1denotes
value0 at t3 whenapplying 0000000� andvalue1 at t0 andt1 whenshifting in thesecondtest
vector 1101011� . When primary inputs x0x1x2x3 changeat t0 as shown in Figure1(a) the
two markedboxesillustratespurioustransitions0� 1� 0 and1� 0� 1 at theoutputof themarked
NOR and NOT gaterespectively. A spurioustransitionduring test applicationin full scan
sequentialcircuitsis a transitionwhichoccursin thecombinationalpartof thecircuit undertest
while shifting out thetestresponseandshifting in thepseudoinputpartof thenext testvector.
Spurioustransitionsdonothaveany influenceontestefficiency sincethevalueat theinputand
outputof thecombinationalpartof thecircuit is not usefultestdata.Furthermore,thevalueof
primaryinputsis irrelevantduringshiftingout thetestresponse.Thereforeif theprimaryinputs
arefrozenuntil t1 thecontrollingvalue1 at the input of themarkedNOR gateis preservedat
t1 andno spurioustransitionsat the outputof the markedNOR andNOT gateswill occur, as
shown in Figure1(b). The primary inputscanbe frozenuntil t3 whentestvector 1101011�is appliedto thecombinationalpartof thecircuit. Thetestapplicationstrategy whereprimary
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inputschangeat time tm is calledas late as possible (ALAP). However freezingthe primary
inputsuntil tm will not yield theminimal numberof nodetransitioncountasdemonstratedin
Figures1(c)and1(d)usingthesametestvectors.In Figure1(c), in thecaseof primaryinputx0
thevalue0� 0� 1 denotesvalue0 at t1 andt2 whenshifting in 1101011� andvalue1 at t3 when
applying 1101011� . Whenprimaryinputsx0x1x2x3 arefrozenuntil t3 asshown in Figure1(c)
themarked box illustratesa spurioustransition0� 1� 0 at theoutputof themarked AND gate.
However if the primary inputsarechangedearlierat t2 the controlling value0 at the input of
themarkedAND gateis preservedat t2 andno spurioustransitionsat theoutputof themarked
AND gatewill occurasshown in Figure1(d). So far it wasshown thatbothASAP or ALAP
testapplicationstrategiesleadto spurioustransitionsduringshifting in testvectorsandshifting
out testresponses.Now the questionis whenshouldthe primary inputschangesuchthat the
smallestnumberof spurioustransitionsoccurwhich leadsto lowerpowerdissipation?Thebest
primary input changetime is the time whentheprimary inputsof theprevious testvectorare
unfrozenandchangedto the valuesof the actualtestvector, leadingto the smallestvaluein
nodetransitioncountNTC. Thus,finding theoptimalprimary input changetime will leadto
highercorrelationbetweenconsecutive valueson the input lines of the combinationalpart of
thecircuit andhenceto lowerpowerdissipationduringtestapplication.
Figures1(a) to 1(d) have illustratedthereductionof spurioustransitionsover a threeclock
cyclesperiod. To give insight of the proposedtechniquefor power dissipationminimisation
during the entire testapplicationperiod,Tables1(a) and1(b) show the flow of testdatafor
the benchmarkcircuit s27 of Figure 1 for ASAP and the proposedtest applicationstrategy
respectively. In Table 1(a) considerthe scanlatch order S2 S1 S0 � and test vector order
V0 V2 V3 V4 V1 � after simultaneoustestvectororderingandscanlatch orderingwascarried
outasshown in section2. Thefirst columnshowstheclockcycle index andthesecondcolumn
outlinesthetestvectorwhich is scannedin duringt0, t1, t2 andappliedat t3. Theoperationtype
(Scanor Load)is shown in column3. In thecaseof a Scanoperationthefourth columngives
the ScanIn value. Columns5-8 show the valuesof primary inputsx0x1x2x3 andthe columns
9-11 show the next statevaluesy �2y �1y �0. The last columnshows the valueof nodetransition
countNTC for eachclock cycle. The nodetransitioncountis calculatedasfollows. In clock
cycle i thenumberof transitionsin combinationalpart is computedby consideringtheprimary
inputsof clockcycle i andthenext statevaluesof clockcycle (i � 1). Thenodetransitioncount
in sequentialpart is the sumof nodetransitioncountof eachscanlatch by scanning/loading
the next statevaluesy �2y �1y �0 in clock cycle i, usingthe valuesof NSLmin andNSLmax outlinedin
section2. Initially all the primary andscaninputsareset to 0 andthe nodetransitioncount
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over theentiretestapplicationperiodundertheASAP testapplicationstrategy is NTC � 296.
This valuecanbereducedif spurioustransitionsduringshifting in testvectorsandshifting out
responsesareavoidedby primaryinput freezing.Testapplicationstrategy whereprimaryinput
changetime is determinedsuchthatmaximumsaving in transitioncountis achievedis refered
to asbest primary input change (BPIC) testapplicationstrategy. Thechangeof primary input
part of testvectorVi at time t j is indicatedby tVi� t j. If the primary input changetimesare
setto tV0� t2, tV2
� t0, tV3� t0, tV4
� t3, andtV1� t1 asshown in the marked boxesof Table
1(b), thenodetransitioncountreducesto NTC � 266. Thereasonfor reducingthenumberof
transitionsis theincreasedcorrelationbetweenconsecutivevaluesof primaryandpseudoinput
inputsduringt0, t1, t2, whentestvectorsarescannedin andtestresponsesarescannedout. For
exampleby freezingtV4 until t3 theNTC in clock cycles12 and14 reducesfrom 16 and24 re-
spectively in thecaseof ASAP(Table1(a))to 10and14respectively in thecaseof BPIC(Table
1(b)). Notethatin clock cycleswhentestresponsesareloadedin scanlatches(L in column3),
thecorrecttestresponsevaluesfrom Table1(a)arepreserved. Whencombiningprimaryinput
freezingwith simultaneousscanlatchorderingandtestvectororderingfurther improvements
areachieved.For testvectororder V1 V0 V4 V3 V2 � , scanlatchorder S1 S2 S0 � andprimary
input changetimessetat tV1� t0, tV0
� t0, tV4� t1, tV3
� t1, andtV2� t3, it is shown that the
new valueof nodetransitioncountis reducedfurther to NTC � 251 (Table1(c)). This high-
lights the importanceof combiningprimary input freezingwith simultaneousscanlatch and
testvectororderingfor NTC reductionandhencesavings in power dissipation.Note that the
proposedBPICtestapplicationstrategy dependsonly oncontrollingprimaryinputchangetime,
andhencedoesnot requireextra designfor testhardware. This meansthatpower dissipation
is minimizedwithout an increasein gatecountor performance.Furthermore,sinceno extra
testdatais necessaryandthecompletetestvectorcomputedby theATPGtool is appliedto the
circuit undertest irrespective of the primary input changetime, the proposedtestapplication
strategy doesnot decreasetestefficiency andno penaltyin testapplicationtime or volumeof
testdatais added.
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4 Proposed Algorithms for Minimising Power Dissipation Dur-ing Test Application
In section4.1 a new algorithmwhich computesbestprimary input changetime for eachtest
vector with respectto a given test vector and scanlatch order is given. Section4.2 shows
how combiningtheproposedtechniquewith therecentlyintroducedscanlatchandtestvector
orderingusingasimulatedannealing-baseddesignspaceexplorationleadsto furtherreductions
in powerdissipationduringtestapplication.
4.1 Best Primary Input Change (BPIC) Algorithm
Spurioustransitionsinducedby fixedprimaryinput changesasoutlinedin section3 aresolved
by freezingthe primary inputs for eachtest vectoruntil the minimum numberof transitions
is achieved. For a given scanlatch order with m scanlatches,the total numberof primary
input changetimesis (m 1). Consideringn testvectors,in a giventestvectororder, thetotal
numberof configurationsof primary input changingfor all the testvectorsis � m 1� n. Best
PrimaryInput Change(BPIC) algorithmcomputesthebestprimaryinput changetime for each
testvectorfor agivenscanlatchorderandtestvectororder. Figure2 illustratesthepseudocode
of theproposed(BPIC) algorithm.Thefunctionacceptsasinput,atestsetS andacircuit C. The
outerloop representsthetraversalof all the testvectorsfrom testsetS. All them 1 primary
input changetimesfor testvectorVi arethenconsideredin the inner loop. For eachprimary
input changetime t j, circuit C is simulatedandthenodetransitioncountNTCi � j is registered.
After thecompletionof theinnerloop thebestprimaryinputchangetime t ji, for which NTCi � jiis minimum,is retainedandtheouterloop continuesuntil theentiretestsetis examined.The
algorithmcomputesthebestsolutionin acomputationaltimewhichis polynomialin thenumber
of testvectorsn, thenumberof scanlatchesm, andthecircuit size �C � . Despitethereductions
whichareachievedby theBPIC algorithmasshown in section5, all thefactorsaccountablefor
powerdissipationduringtestapplicationmustbecombinedfor achieving bestresults,which is
describednext.
4.2 Simulated Annealing Design Space Exploration for Simultaneous TestVector Ordering, Scan Latch Ordering and Primary Input Freezing
High power dissipationproblemscausedby an inadequatetestvectororderingandscanlatch
orderingaresolvedby ansimulatedannealingalgorithmwhichcanescapelocalminima.For a
testtestwhichconsistsof n testvectorstherearen! testvectororderings.Furthermorefor each
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testvectororderingtherearem! scanlatchorderings,wherem is thenumberof scanlatches.
Finding theoptimal testvectorandscanlatchorderis NP-hard[11]. The total complexity of
thedesignspaceis n! � m! which evenfor small designproblemswith 15 testvectorsand15
scanlatchesis computationallyexpensive. We needto useefficient designspaceexploration
techniqueswhich shouldtake accountof the discrete,degenerateandhighly irregular design
space.
Figure3 illustratesthebasicstepsof simulatedannealing-basedoptimisation.Theoptimi-
sationfunctionacceptsasinput a testsetS andacircuit C whicharesetto initial configuration
SINIT andCINIT respectively. Thecalculationof theinitial controlparametervalue[15] is based
on the assumptionthat a sufficiently large numberof generatedsolutions(for example95%)
shouldbeacceptedat thebeginningof theannealingprocess.Theouterloopmodifiesthecon-
trol parameterof thesimulatedannealingalgorithmwhichis graduallyloweredastheannealing
processproceeds.Within theinnerloop a new sequenceof solutionsis generatedat a constant
controlparametervalue.Thelengthof a sequenceof solutionsis setto 20. Thecontrolparam-
eteris decreasedin sucha way that thestationarydistributionsat theendof thesequencesof
solutionsarecloseto eachother. By evaluatinginformationaboutthecostdistribution within
eachsequenceof solutions,a fastdecreaseof the control parameteris givenaccordingto the
coolingschedulefrom [15]. Eachnew solutionis generatedusingoneof thefollowing:
� randomlychoosetwoscanlatchesSi andS j from theactualscanlatchorder S0 ����� Si ����� S j ����� Sm � 1 � andexchangetheirpositiongeneratinganew scanlatchorder S0 ����� S j ����� Si ����� Sm � 1 � , wherem is thenumberof scanlatchesin thecircuit.
� randomlychoosetwo testvectorsVa andVb fromtheactualtestvectororder V0 ����� Va ����� Vb ����� Vn � 1 � andexchangetheirpositiongeneratinganew testvectororder V0 ����� Vb ����� Va ����� Vn � 1 � , wheren is thenumberof testvectorsin thetestset.
The alternative applicationof exchangesbetweenrandomlychosentestvectorsandscan
latchesproves to be efficient in exploring the discretedesignspace. For eachnew solution
the proposedbestprimary input changealgorithmBPIC(SNEW CNEW ) is called to determine
the bestprimary input changetimesfor all the testvectorsfrom SNEW accordingto the scan
latchorderin CNEW . New solutionsareeitheracceptedor rejecteddependingontheacceptance
criteriondefinedin thesimulatedannealingalgorithm[16]. If thebestsolutionsofar is reached
thenit is savedin SBEST CBEST � which is returnedat theendof theoptimisationprocess.The
optimisationprocessis terminatedafterthevariationin theaveragecostoveraselectednumber
of sequencesof solutionsfalls bellow a given valueasdescribedin [15]. It is importantto
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notethatall the factorsaccountablefor power dissipationduring testapplicationasdescribed
in sections2 and3 areincludedin theoptimisationprocess.This leadsto highsavingsin power
dissipationasoutlinedin theexperimentalresultssection.
5 Experimental Results
Thissectiondemonstratesthroughasetof benchmarkexamplesthattheproposedbestprimary
inputchange(BPIC) algorithmoutlinedin section4.1yieldssavingsin powerdissipationduring
testapplication.FurthermorethesavingscanbesubstantiallyimprovedwhenBPIC is integrated
with testvectororderingandscanlatch orderingasdescribedin the algorithmin section4.2.
Thesealgorithmshave beenimplementedwithin theframework of a low power testingsystem
ona350MHz PentiumII PCwith 64MB RAM runningLinux andusingGNU CCversion2.7.
Table2 shows the resultswhenthe BPIC algorithmis appliedby itself (i.e. without scan
latch andtestvectorordering)for 24 commonlyacceptedISCAS89benchmarkcircuits [13].
The first andsecondcolumnsgive the circuit nameand the numberof scanlatches(SL) re-
spectively. The third columngives the numberof test vectors(TV) generatedby the ATPG
tool ATOM [17]. The averagevalueof nodetransitioncount(NTC), which is the total value
of NTC dividedby thetotal numberof clock cycles,for assoonaspossible(ASAP),aslateas
possible(ALAP), andtheproposedbestprimaryinputchange(BPIC) testapplicationstrategies
outlinedin section3, aregivenin columns4, 5 and6 respectively. Theaveragevalueof NTC is
calculatedundertheassumptionof thezerodelaymodel. Thepower minimisationtechniques
describedin this paperalsoapply to otherdelaymodels,suchasunit delaymodel [18] and
variabledelaymodel [19]. It canbeenclearly seenfrom Table2 that BPIC testapplication
strategy hasthe leastaveragevalueof NTC for all thebenchmarkcircuits whencomparedto
ASAP andALAP testapplicationstrategies. To give an indicationof the reductionsin aver-
agevalueof NTC, columns7 and8 show the percentagereductionof BPIC over ASAP and
ALAP testapplicationstrategies.Thereductionvariesfrom approximately10%asin thecase
of s641 down to under1% asin the caseof s526. Table2 hasshown the reductionsin node
transitioncountusinga non compacttestset. In order to reducetestapplicationtime while
maintainingthe sametestquality, compacttestsetsareused. Compacttestsetsmay leadto
higherpower dissipationbecauseof an increasednumberof sensitisedpathsby eachtestvec-
tor. However, usingtheproposedBPIC algorithmsimilar averagevaluesof NTC areachieved
for all thebenchmarkcircuitswhencomparingcompacttestsetsto noncompacttestsets.Table
3 shows experimentalresultsfor compacttestsetgeneratedby MINTEST [20] whenapplying
theproposedBPIC algorithmwithout scanlatchandtestvectorordering.For example,in the
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caseof s298 theaveragevalueof NTC for noncompacttestsetis 114.73(Table2), whereasfor
compacttestsettheaveragevalueof NTC is 107.85(Table3) despitea considerablereduction
in thenumberof testvectorsfrom 52asin thecaseof noncompacttestsetto 23asin thecaseof
thecompacttestset.Thesimilarvaluesof NTC aredueto findingthebestprimaryinputchange
time for reducingspurioustransitionsduringshifting in testvectorsandshifting out responses.
This clearlyshows thatusingcompacttestsetsandhencedecreasingthe testapplicationtime
will not increasethepowerdissipationduringtestapplicationin full scansequentialcircuits.
While theapplicationof theBPIC algorithmreducesaveragevalueof NTC whencompared
to ASAPandALAP testapplicationstrategies,asshown in Tables2 and3 for noncompactand
compacttestsetsrespectively, further savings canbe achieved whenBPIC is combinedwith
testvectororderingandscanlatchordering.Theresultsof theproposedsimulatedannealing-
baseddesignspaceexploration(section4.2)for solvingsimultaneoustestvectorordering,scan
latch orderingand primary input freezingfor non compacttest set is shown in Table 4. In
orderto assestheimpactof all thefactorsaccountablefor powerdissipationthefollowing three
experimentswerecarriedout. In the first experimentthe averagevalueof NTC is computed
usingscanlatchandtestvectororderingunderASAP testapplicationstrategy. Theresultsare
given in columns2 and3. The reductionin column3 is computedover the nodetransition
countof the initial scanlatch and test vector. In the secondexperimentthe test application
strategy hasbeenchangedto ALAP, andtheresultsareshown in columns4 and5. In thethird
experimentthe proposedBPIC testapplicationstrategy is combinedwith scanlatch andtest
vectororderingandtheresultsaregivenin columns6 and7. NotethatBPIC alwaysproduces
betterresultsthanASAPandALAP dueto highercorrelationbetweensuccessivestatesduring
shifting in testvectorsandshifting out test responses.This clearly shows the importanceof
integratingall the factorsaccountablefor power dissipationin the optimisationprocess.The
reductionvaluedependson thetypeof thecircuit andtheaveragevalueof NTC for theinitial
scanlatchandtestvectororder. For examplein thecaseof s713 thereductionis 34%andit goes
down to 4%asin thecaseof s838. However, thisstill presentsanimprovementwhencompared
to ASAP andALAP which yield reductionsonly of 3%. Table5 shows theresultsfor ASAP,
ALAP andBPIC testapplicationstrategieswhenusingcompacttestsets.Again theproposed
BPIC providesbetterresultsthanASAP andALAP, for all the circuits from the benchmark
set.It is interestingto notethatNTC valuesfor BPIC testapplicationstrategy whenusingnon-
compactandcompacttestsetsaresimilar. Thisindicatesthattestsetsizehasnoinfluenceonthe
averagevalueof NTC confirmingthattheonly threeaccountablefactorsfor power dissipation
during test applicationin full scancircuits are test vector ordering,scanlatch orderingand
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primary input freezing. For someof the examplesthe computationaltime for completingthe
optimisationmay increaseover 40,000susinga PentiumII processorat 350 MHz, asshown
in Table4. This is dueto the hugesizeof the designspaceandthe low numberof solutions
with identicalNTC which clearly leadsto longertimesfor explorationandconvergenceof the
simulatedannealingalgorithm. However, whenusingcompacttestsasshown in Table5, due
to smallernumberof testvectorvectorsandconsequentlythe sizedesignspace,lower time
for completionis requiredwhich leadsto the conclusionthat compacttestsetshave benefits
in bothtestapplicationtime aswell asin computationaltime with similar reductionsin power
dissipation.
6 Conclusions
This paperhasproposeda new techniquefor minimising power dissipationin full scanse-
quentialcircuits during testapplication. The techniqueis basedon increasingthe correlation
betweensuccessivestatesduringshifting in testvectorsandshiftingout testresponsesby freez-
ing the primary inputsuntil the smallestnumberof transitionsis achieved. A new algorithm
whichcomputesbestprimaryinputchange(BPIC) timefor eachtestvectorhasbeenpresented.
It hasbeenshown thatcombiningthedescribedtechniquewith therecentlyreportedscanlatch
andtestvectororderingusingasimulatedannealing-baseddesignspaceexplorationyieldssub-
stantialreductionsin powerdissipationduringtestapplication.Exhaustiveexperimentalresults
usingbothcompactandnoncompacttestsetshave shown thatcompacttestsetshave similar
powerdissipationduringtestapplicationwith substantialreductionin testapplicationtime and
computationaltimewhencomparedto noncompacttestsets.
While this paperhasshown how BPIC minimisespower dissipationin full scansequential
circuits, current researchunderway by the authorsinvestigatesthe applicability of BPIC to
partialscanandtheidentificationof thebestdesignfor testmethodin termsof powerdissipation
duringtestapplication.
AcknowledgementTheauthorswishto thankDr. PeterKollig of PhilipsSemiconductors,UK, for usefuldiscus-
sionsduringthepreparationof thepaper. Also, theauthorsacknowledgetheCentreof Reliable
andHigh-PerformanceComputingof Universityof Illinois atUrbana-Champaignfor providing
GATEST, ATOM andMINTEST testtools.
12
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14
Tables
Cycle Vector Op SI x0 x1 x2 x3 y �2 y �1 y �0 NTC0 (t0) V0 S 0 1 1 0 1 0 0 0 141 (t1) V0 S 1 1 1 0 1 1 0 0 102 (t2) V0 S 1 1 1 0 1 1 1 0 193 (t3) V0 L - 1 1 0 1 0 0 1 184 (t0) V2 S 0 0 0 1 0 0 0 0 155 (t1) V2 S 1 0 0 1 0 1 0 0 106 (t2) V2 S 0 0 0 1 0 0 1 0 147 (t3) V2 L - 0 0 1 0 1 1 0 198 (t0) V3 S 1 0 1 1 1 1 1 1 119 (t1) V3 S 1 0 1 1 1 1 1 1 10
10(t2) V3 S 1 0 1 1 1 1 1 1 611(t3) V3 L - 0 1 1 1 0 0 0 1812(t0) V4 S 0 1 1 0 0 0 0 0 1613(t1) V4 S 1 1 1 0 0 1 0 0 1014(t2) V4 S 0 1 1 0 0 0 1 0 2415(t3) V4 L - 1 1 0 0 0 1 0 1616(t0) V1 S 0 0 0 0 0 0 0 1 1817(t1) V1 S 0 0 0 0 0 0 0 0 1818(t2) V1 S 0 0 0 0 0 0 0 0 619(t3) V1 L - 0 0 0 0 0 0 0 620(t0) - S 0 0 0 0 0 0 0 0 621(t1) - S 0 0 0 0 0 0 0 0 622(t2) - S 0 0 0 0 0 0 0 0 6
TOTAL 296
(a)As SoonAs Possible(ASAP) testapplicationstrategy
Table1: Theflow of testdatafor thecircuit in Figure1 duringtheentiretestapplicationperiod
15
Cycle Vector Op SI x0 x1 x2 x3 y �2 y �1 y �0 NTC0 (t0) V0 S 0 0 0 0 0 0 0 0 61 (t1) V0 S 1 0 0 0 0 1 0 0 102 (t2) V0 S 1 1 1 0 1 1 1 0 173 (t3) V0 L - 1 1 0 1 0 0 1 184 (t0) V2 S 0 0 0 1 0 0 0 0 155 (t1) V2 S 1 0 0 1 0 1 0 0 106 (t2) V2 S 0 0 0 1 0 0 1 0 147 (t3) V2 L - 0 0 1 0 1 1 0 198 (t0) V3 S 1 0 1 1 1 1 1 1 119 (t1) V3 S 1 0 1 1 1 1 1 1 10
10(t2) V3 S 1 0 1 1 1 1 1 1 611(t3) V3 L - 0 1 1 1 0 0 0 1812(t0) V4 S 0 0 1 1 1 0 0 0 1013(t1) V4 S 1 0 1 1 1 1 0 0 1014(t2) V4 S 0 0 1 1 1 0 1 0 1415(t3) V4 L - 1 1 0 0 0 1 0 1616(t0) V1 S 0 1 1 0 0 0 0 1 1417(t1) V1 S 0 0 0 0 0 0 0 0 1818(t2) V1 S 0 0 0 0 0 0 0 0 619(t3) V1 L - 0 0 0 0 0 0 0 620(t0) - S 0 0 0 0 0 0 0 0 621(t1) - S 0 0 0 0 0 0 0 0 622(t2) - S 0 0 0 0 0 0 0 0 6
TOTAL 266
(b) ProposedBestPrimaryInputChange(BPIC) testapplicationstrat-egy
Table1: Theflow of testdatafor thecircuit in Figure1 duringtheentiretestapplicationperiod
16
Cycle Vector Op SI x0 x1 x2 x3 y �1 y �2 y �0 NTC0 (t0) V1 S 0 0 0 0 0 0 0 0 61 (t1) V1 S 0 0 0 0 0 0 0 0 62 (t2) V1 S 0 0 0 0 0 0 0 0 63 (t3) V1 L - 0 0 0 0 0 0 0 64 (t0) V0 S 0 1 1 0 1 0 0 0 145 (t1) V0 S 1 1 1 0 1 1 0 0 106 (t2) V0 S 1 1 1 0 1 1 1 0 107 (t3) V0 L - 1 1 0 1 0 0 1 278 (t0) V4 S 0 1 1 0 1 0 0 0 149 (t1) V4 S 0 1 1 0 0 0 0 0 11
10(t2) V4 S 1 1 1 0 0 1 0 0 1011(t3) V4 L - 1 1 0 0 1 0 0 612(t0) V3 S 1 1 1 0 0 1 1 0 1013(t1) V3 S 1 0 1 1 1 1 1 1 1614(t2) V3 S 1 0 1 1 1 1 1 1 1015(t3) V3 L - 0 1 1 1 0 0 0 1816(t0) V2 S 0 0 1 1 1 0 0 0 1017(t1) V2 S 0 0 1 1 1 0 0 0 618(t2) V2 S 1 0 1 1 1 1 0 0 1019(t3) V2 L - 0 0 1 0 1 1 0 1920(t0) - S 1 0 0 1 0 1 1 1 1021(t1) - S 1 0 0 1 0 1 1 1 1022(t2) - S 1 0 0 1 0 1 1 1 6
TOTAL 251
(c) ProposedBestPrimaryInputChange(BPIC) testapplicationstrat-egy combinedwith simultaneousscanlatchandtestvectorordering
Table1: Theflow of testdatafor thecircuit in Figure1 duringtheentiretestapplicationperiod
17
proposed CPUcircuit SL TV
ASAP ALAPBPIC
%reduction %reductiontimeNTC NTC
NTCover ASAP over ALAP
(s)
s208 8 65 55.39 55.73 53.48 3.45 4.03 0.17s298 14 52 115.39 115.59 114.73 0.56 0.74 0.28s344 15 62 131.43 131.45 130.54 0.67 0.69 0.48s349 15 65 132.46 132.45 131.47 0.75 0.74 0.50s382 21 72 145.12 145.54 143.91 0.83 1.12 0.80s386 6 109 86.61 86.20 84.22 2.76 2.29 0.38s400 21 71 146.32 146.35 144.78 1.05 1.07 0.81s420 16 98 107.19 107.17 104.46 2.53 2.52 1.00s444 21 77 149.08 149.93 148.05 0.69 1.25 0.97s510 6 90 115.50 115.04 114.13 1.17 0.79 0.40s526 21 107 185.83 186.17 184.79 0.55 0.73 1.45s641 19 99 186.74 184.03 168.71 9.65 8.32 2.19s713 19 100 198.88 196.83 180.42 9.28 8.33 2.29s820 5 190 139.22 138.89 136.79 1.74 1.51 1.02s832 5 200 138.46 137.96 136.05 1.73 1.37 1.07s838 32 183 199.81 199.84 195.00 2.40 2.42 14.72s953 29 138 169.93 169.66 167.20 1.60 1.44 4.71s1196 18 227 105.18 105.35 100.43 4.51 4.67 6.38s1238 18 240 106.85 107.43 102.06 4.48 5.00 6.69s1423 74 135 508.09 509.91 502.78 1.04 1.39 56.48s1488 6 196 346.62 346.92 342.76 1.11 1.19 2.68s1494 6 191 351.92 352.85 348.54 0.95 1.22 2.62s5378 179 358 1786.44 1786.58 1774.36 0.67 0.68 3113.87s9234 211 660 3123.16 3123.33 3098.91 0.77 0.78 16395.37
Table2: Experimentalresultsfor noncompacttestsetgeneratedby ATOM [17] whenapplyingtheproposedBPIC algorithmwithout scanlatchandtestvectorordering
18
proposed CPUcircuit SL TV
ASAP ALAPBPIC
%reduction %reductiontimeNTC NTC
NTCover ASAP over ALAP
(s)
s208 8 27 54.80 54.72 52.42 4.35 4.20 0.07s298 14 23 108.25 108.57 107.85 0.36 0.66 0.12s344 15 13 124.36 124.21 123.48 0.70 0.58 0.10s349 15 13 128.35 128.33 127.62 0.57 0.55 0.10s382 21 25 147.91 148.14 146.75 0.78 0.93 0.28s386 6 63 85.77 85.26 83.38 2.78 2.19 0.21s400 21 24 154.04 154.44 152.76 0.83 1.08 0.28s420 16 43 100.73 100.46 98.12 2.59 2.33 0.48s444 21 24 155.46 156.30 154.19 0.81 1.35 0.32s510 6 54 114.03 113.75 112.53 1.31 1.06 0.24s526 21 49 182.74 182.98 182.17 0.31 0.44 0.68s641 19 21 172.88 176.55 161.08 6.82 8.75 0.47s713 19 21 195.45 192.38 181.10 7.34 5.86 0.49s820 5 93 138.03 137.65 135.55 1.79 1.51 0.51s832 5 94 138.83 138.37 136.33 1.79 1.47 0.50s838 32 75 187.95 187.56 185.14 1.49 1.29 6.35s953 29 76 169.64 169.02 166.64 1.76 1.40 2.66s1196 18 113 105.67 105.42 100.43 4.95 4.73 3.39s1238 18 121 103.92 103.83 98.91 4.82 4.74 3.40s1423 74 20 506.10 506.89 501.14 0.98 1.13 8.73s1488 6 101 365.47 365.66 361.40 1.11 1.16 1.45s1494 6 100 369.59 370.63 365.89 1.00 1.28 1.40s5378 179 97 1808.88 1809.32 1791.68 0.95 0.97 826.89s9234 211 105 3045.30 3045.51 3014.90 0.99 1.01 2637.05
Table3: Experimentalresultsfor compacttestsetgeneratedby MINTEST [20] whenapplyingtheproposedBPIC algorithmwithout scanlatchandtestvectorordering
19
Test application strategy targeted during optimisation CPUcircuit ASAP
%reductionALAP
%reductionBPIC
%reductiontime
NTC NTC NTC (s)
s208 48.39 12.64 49.19 11.19 45.35 18.13 24390s298 97.97 15.09 92.49 19.84 92.09 20.19 33960s344 115.55 12.08 119.68 8.93 114.85 12.61 34270s349 118.62 10.45 121.01 8.64 117.87 11.01 35040s382 125.93 13.22 125.98 13.18 124.47 14.23 40430s386 70.50 18.60 71.86 17.03 69.74 19.48 41550s400 128.97 11.85 132.12 9.70 125.30 14.36 34550s420 93.94 12.35 94.51 11.82 92.41 13.78 43410s444 130.27 12.61 134.33 9.89 129.27 13.28 42940s510 98.91 14.35 101.60 12.02 97.98 15.16 36920s526 162.13 12.75 160.96 13.37 160.52 13.61 37340s641 142.19 23.85 141.44 24.25 132.42 29.08 42470s713 146.91 26.13 144.98 27.09 130.34 34.46 44630s820 111.71 19.75 112.10 19.47 110.83 20.39 43710s832 115.19 16.80 114.07 17.61 113.19 18.24 36520s838 193.50 3.16 193.80 3.01 190.29 4.76 45970s953 128.24 24.53 128.61 24.31 127.26 25.10 46470
Table4: Experimentalresultsfor noncompacttestsetgeneratedby ATOM [17] whenapplyingtheproposedBPIC algorithmintegratedwith testvectororderingandscanlatchordering
20
Test application strategy targeted during optimisation CPUcircuit ASAP
%reductionALAP
%reductionBPIC
%reductiontime
NTC NTC NTC (s)
s208 47.85 12.68 47.90 12.59 44.02 19.67 8399s298 91.48 15.49 96.22 11.11 91.13 15.81 12980s344 94.92 23.66 100.27 19.37 94.02 24.39 15550s349 104.62 18.48 110.23 14.11 104.14 18.85 13560s382 120.37 18.61 124.09 16.10 118.49 19.88 29020s386 70.33 18.00 69.72 18.71 68.54 20.09 24500s400 120.51 21.76 123.36 19.92 119.51 22.41 29380s420 90.97 9.69 87.61 13.02 83.13 17.47 28940s444 129.44 16.73 132.04 15.06 120.07 22.76 29040s510 95.79 15.99 97.68 14.33 94.80 16.86 22940s526 151.31 17.19 158.35 13.34 150.87 17.44 29310s641 143.36 17.07 130.56 24.48 120.16 30.49 29210s713 152.77 21.83 144.71 25.96 133.49 31.69 24920s820 110.61 19.86 111.23 19.41 109.71 20.51 28870s832 112.39 19.04 112.30 19.10 111.40 19.75 28950s838 170.01 9.54 170.75 9.15 168.36 10.42 30220s953 128.15 24.45 128.70 24.13 127.06 25.09 30040
Table5: Experimentalresultsfor compacttestsetgeneratedby MINTEST [20] whenapplyingtheproposedBPIC algorithmintegratedwith testvectororderingandscanlatchordering
21
Figures
y1
y2
y0
Scan Out
Scan In
0/0/0
0/0/00/1/1
0/1/1
0/1/1
1/0/0
1/1/1
1/0/1
0/0/11/0/0
0/0/0
0/1/1
1/1/1
0/0/0
0/0/0
0/0/0
0/0/1
0/1/0
x
x
x
x
0
1
2
3
z
S
S
S
1
2
0
0
(a) Primaryinputschangeassoonaspossible(ASAP) at t0
Figure1: Examplecircuit (s27 from [13]) illustratingfactorswhich leadto spurioustransitionsduringtestapplication
Scan Out
Scan In
0/0/0
0/0/0
1/1/1
0/0/1
0/0/0
1/1/1
0/0/0
0/0/0
0/0/0
0/0/1
0/0/1
0/0/1
0/0/1
1/1/0
0/0/1
1/1/0
0/0/0
0/0/0
x
x
x
x
y
y
y
z
S
S
S
0
1
2
3
0
0
1
2
0
1
2
(b) Primaryinputschangeat t1
Figure1: Examplecircuit (s27 from [13]) illustratingfactorswhich leadto spurioustransitionsduringtestapplication
22
y0
y1
y2
Scan Out
Scan In
0/0/0
0/0/1
0/0/0
0/1/1
0/0/0
0/0/1
0/0/1
0/0/1
1/1/0
1/1/0
1/1/0
1/0/1 0/0/0
1/1/1
0/0/1
1/1/0
0/1/1
0/1/0x
xxxx
x
x
x
z
0
1
2
3
0
S
S
S
0
1
2
Scan Out
(c) Primaryinputschangeaslateaspossible(ALAP) at t3
Figure1: Examplecircuit (s27 from [13]) illustratingfactorswhich leadto spurioustransitionsduringtestapplication
Scan Out
Scan In
0/0/0
0/1/1
0/1/1
0/1/1
1/0/00/0/1
0/0/0
0/1/1
0/0/0
1/1/0
1/0/1 0/0/0
1/1/1
1/1/0
0/0/1
0/1/1
1/1/0
0/0/0x
x
x
x
y
y
y
z
SS
S
S
0
1
2
3
0
0
1
2
0
1
2
(d) Primaryinputschangeat t2
Figure1: Examplecircuit (s27 from [13]) illustratingfactorswhich leadto spurioustransitionsduringtestapplication
23
function BPIC(Test Set S, Circuit C)
for everyVi from S with i � 0 ����� n � 1for every tVi
� t j with j � 0 ����� mcomputeNTCi � j by simulatingC
gett ji suchthatNTCi � ji is minimumreturn t j0 t j1 ����� t jn � 1 �
�
Figure2: Proposedalgorithmfor determiningtheBestPrimaryInputChangetime for eachtestvector
function OPTIMISE(Test Set S, Circuit C)
SINIT is setto SCINIT is setto Crepeat
repeatGenerateanew solution SNEW CNEW � asdescribedin section4.2Computethenumberof transitionsusingBPIC(SNEW CNEW )
asdescribedin section4.1Acceptor rejectthenew solutionaccording
to theSA acceptancecriterion[16]if thebestsolutionsofar is reached
SBEST is setto SNEW
CBEST is setto CNEW
until thenumberof solutionsequalsthesolutionsequencelengthdecreasethecontrolparametervalue
until thesystemis frozenreturn SBEST CBEST �
�
Figure3: Proposedsimulatedannealing-baseddesignspaceexplorationfor simultaneoustestvectorordering,scanlatchorderingandprimaryinput freezing
24