Domino Circuit Design - University of Texas at...

The University of Texas at AustinEE 382M Class Notes Page # 1

Domino Circuit Design

Mark McDermott Kevin Nowka, IBM

EE-382M

VLSI–II


Outline• Derivation of Domino

– Motivation for domino circuits– Tradeoffs compared to static circuits

• Textbook vs Industry Domino– Use of static logic gates– Keepers– Footless gates and delayed clocks– Domino timing constraints– Set Dominant Latches (SDLs)

• Summary

2


Motivation for Domino - SPEED• Performance of CMOS gates

– Delay varies directly with output load– Delay varies inversely with device size– Sizing up: Current stage gets faster, previous stage gets

slower

• Higher gain gates have a speed advantage– Gain = Cout/Cin for a particular delay or drive strength


Basic precharge/discharge structures

Fully CMOS logic gates:Two logic blocks (N & P).Both up and down transitions could be critical.The input capacitance is that of both an N and a P device.The Pfets generally wider than NFETS (a.k.a. Beta ratio). Especially problematic when high stacks are present (then the area/speed/Cin penalty is big).

So, let’s get rid of the p-logic block !☺ A single logic block remains.☺ A single transition should be optimized for the logic

function evaluation!☺ The input capacitance is only that of the N device!

n-logic

p-logic

in f

n-logicin

fφ


Anatomy of a Domino Gate

In 2 2

Clk 1

2

In 1 1

3

3

Static CMOS NOR

Out

Out

Domino NOR

• Features of a simple domino gate

• Single clocked P-FET

• Clocked “foot” N-FET device

• Only presents N device load to its inputs

• N network is identical to static gate except for foot

• For the same pull-down strength, the domino gate gives approximately 2x the gain (in this case)

•Trip point of the gate is now just Vtn instead of based on P/N ratio


Static CMOS Path vs Domino Path

Domino performs the same logic as static CMOS with significantly less delay.

In 2 2

2 2

1

1

2

8

4A B COut

1

Clk

1

2 2

In 1 1

3

3 1.5 1.5

1.5

1.5

2

1

8

4

A

B COut


Domino timing

Domino Precharge

Clk

EvaluatePrecharge

In 2 2

2 2

1

1

2

8

4A B COut

1

Clk

1

2 2


Domino timing

Domino Precharge

In 2 2

2 2

1

1

2

8

4A B COut

1

Clk

1

2 2

Clk

EvaluatePrecharge


Domino timing

Domino Evaluate

In 2 2

2 2

1

1

2

8

4A B COut

1

Clk

1

2 2

Clk

EvaluatePrecharge


Domino Timing Notes• During evaluate domino is sensitive to “up glitches”

– No recovery from incorrect discharge– “Hard” setup requirement for falling input edges

• Hopefully, the falling edge is not critical

– “Soft” setup requirement for rising input edges• Rising edges may be late provided they still trip the gate

• Domino chains must follow strict domino-static structure– Every even stage must be static.– Can’t have an odd number of stages to a domino input.

• Why not?


The Problem of Inverting Logic

A

B

B

Sa Sb

Sb

SaSa*(AB) + Sb*(AB)#

Static CMOS Path

A

B

Sa Sb

Broken Domino PathClk

Domino logic can not implement an odd

number of inversions.

Sa*(AB) + Sb

(AB)#

AB

AB

(AB)#


Dual Rail Domino

A

B

Sa Sb

Clk

With complementary logic to produce needed inverted signals,

domino can implement any function.

Sa*(AB) + Sb*(AB)#

A# B#

(AB)#

AB


Tradeoffs of Domino

19

• Increased Area– Dual rail domino can double the number of gates

• Increased Power– Precharging increases activity factors– Increased clock load

• Increased Noise Sensitivity– High gain means low noise immunity– Charge sharing in complex gates

• Increased Design Time– Added timing checks– CAD tools less automatedDomino typically only used in the most timing critical paths.

• Faster Gates– Allows more logic per cycle with less delay– Allows for more complex gates (no dual P network)


Textbook vs Industry Domino


Textbook Domino Cycle

In two phase domino design half of logic precharges while other half evaluates.

In

OutB

Clk

Clk#

OutA


Addition #1: Static Gates Used for Logic (a.k.a. Compound Domino)

Any inverting static gate may be used between domino gates.

In

OutB

Clk

Clk#

OutA


Addition #2: Add Half Latches(domino no longer dynamic)

P-keepers hold domino nodes high during stop clock and improve noise margins.

In

OutB

Clk

Clk#

OutA


Sizing Keepers

24

Clk Wp

Wn Wn Wn Wn Wn Wn

Wkpr

NumN*Wn/20 < Wkpr

Min keeper size set by noise requirements

Wkpr < Wn/2Max keeper size set by

delay degradationNumN = 6

NumN*Wn/20 < Wkpr < Wn/2

NumN < 10

Maximum noise sensitivity and delay limit number of parallel stacks.


Addition #3: Add Footless Domino Gates(a.k.a. unfooted delayed reset)

Footless domino gates improve speed and allow more logic per gate.

In

OutB

Clk

Clk#

OutA


Power Races

Negative Evaluate Gap:• More Power

• Evaluate Delay Push Out

Negative Precharge Gap:• More Power

• Precharge Delay Push Out

Data

ClkOut

In footless domino gates Clk must be high when Data is high.

Data

Clk

Evaluate Gap Precharge Gap


Domino max timing constraints with static latches

.

In

Clk Clk#

Static &D1/D2 gates

D1 Static latch

Latch setup + clock skew/jitter

Evaluateforwarddelay


Addition #4: Remove Static Latches

Removal of latches allows transparency from one phase to the next.

In

OutB

Clk

Clk#

OutA


Addition #5: Add Set Dominant Latches (SDLs)

SDLs convert domino signals into more static-like behavior

In

OutB

Clk

Clk#

OutA


SDL Timing

Overlap of Clk# and OutA is now frequency dependent.

With SDLs precharge transition is delayed until start of next evaluate.

Tskew

Clk

Clk#

OutA


Textbook vs Industry Domino

In

Clk

In

Clk

OutA

OutA


Domino Circuit Summary

32

• Domino reduces delay by favoring one transition and making the other non-critical by construction

• The price of this speed is generally:– Greater Noise Sensitivity– More Power– More Design Time

• Industry domino circuits make use of:– Different static logic gates– Keepers– Footless domino gates– Transparency– SDLs


Noise: Leakage and Charge Sharing

CLK

C

B

A

CLKn1

In the evaluate phase, if A=1, AND B=1 AND C=0, charge is redistributed from n1 to the two parasitic capacitors.

The purpose of the p-keeper is to supply current and maintain the voltage on n1 so that the inverter does not flip erroneously. Domino is unforgiving unlike static CMOS that permits spurious transitions.

CLK or CLK

Minimize charge transfer byprecharging internal nodes


Noise Optimization – layout considerations

CLK

CLK

Cc

Bt

At

CLK

Et

Dc

Keep these wires short (Gate cap ok, wire BAD)

Minimize internal node cap – single leg/no contacts where possible

Only short wires here

Don’t let this wire get too long

Due to the dynamic (undriven or weakly driven) nodes,domino is sensitive to noisecoupled to inputs and internalnodes – requires more carefullayout design.


Internal pre-charge scheme - I

An internal precharge can mitigate the charge-sharing problem. This also slows down the circuit a bit because now the additional charge has to flow to ground when A=B=C=1.

F = ABC

CLK

C

B

A

CLK

CLK or CLK


CLK

C

F= ABC

B

A

CLK

B C

Internal pre-charge scheme - II

Relieve clock loading with alternate precharge schemes for internal nodes.


Internal pre-charge scheme - III

Split the tree into two parts. This slows the charge-sharing by making the transistors smaller.

This scheme also evens out the delay between all three inputs.

F= ABC

CLK

CLK

C

B

A

CLK

A

B

C

CLK


Noise-II: victim & aggressor

CLK

CLK

CLK=0


D1 & D2 (footed & footless)

CMOSD1

CLK

C

B

A

CLK

E

D

CLK

D2 CMOS

F


Single Rail Domino: 2-input XOR

CLK

F

B

A

CLK

A

B


Dual rail domino:2-input XOR

CLK

B

A

CLK

A

B

A

F F

Make use of intermediate nodes to form dual rail domino.

Be careful of “sneak paths”.


Dual Rail Domino: 3-input AND

F = ABCCLK

CLK

C

B

A

F = ABCCLK

A B C

Can’t always make use of intermediate nodes.

In dual rail, one rail can be faster than the other.


Complex function: AND-OR

F= ABC + DEF

CLK

CLK

C

B

A

F

E

D

Complex gates can be formed just by adding N-channel transistors.


C

B

A

CLK

A

B

A

B

C

F F

Complex function: 3-input XOR

In complex gates, make use of intermediate nodes. Again, be careful of “sneak paths”.


cin

p0

g1

g0c1

CLK

sneak path example: carry chain

g = ab p = a + b

c1 = g0 + p0cin

c2 = g1 + p1c1 = g1 + p1g0 + p1p0cin

So what happens when a1=b1=1 and a0=b0=0? Well, c2=1 and c1=?

p1

CLKc2

g0


8:1 Mux

CLK

S0

D0

S1

D1. . .

S7

D7

Although this looks OK, the dynamic node is heavily loaded with all of the parasitic diode capacitance.

The heavily loaded dynamic node is good for noise immunity; lousy for performance.

Select signals are nearest the dynamic node for charge-sharing reasons. Only one (few?) select line should ever be high.


. . .

Compound Domino

CLK

S0

D0

S1

D1

S4

D4

S5

D5. . .

When the dynamic node is heavily loaded sometimes it’s best to split it.

This circuit is like two 4:1 muxes melded together.


BC

ABC

Multiple output domino

Sometimes you can make use of intermediate nodes to form new outputs.

The extra circuitry does slow down the 3-input AND function.

CLK

C

B

A


Sizing-I

“equivalent inverter”

1.3/0.65 for beta ratio=2, fanout=3(wp+wn=2)

4/2

4/21.3/0.65*3 ->1.3/1.95 for beta ratio =2, 1.2/2.4 for beta ratio =1.5

1.2/0.8 for beta ratio=1.5


Sizing-II• Start with the output load, and size the inverter(ratio 4:1 or 5:1)

for a fanout of three.• Size the NMOS tree for a fanout of three and taper.• Make the p-keeper big enough to overcome leakage and the

PMOS precharge device equal to fanout of five or six.• Increase the size the p-keeper for worst case charge sharing,

and/or add internal precharge FETs if necessary.


Sizing-III

C

B

A

CLK

5/1

4/2

4/2

4/2

Wn=2.4

Wn=1.92

Wn=1.54

Wp=0.6 Wp=0.5

CLK

Wp=0.5

5/1

“equivalent inverter”

1.2/0.8


Circuit Elements

Clk

DataOut

Data

Clk

Out

Clk

DataOut

Data

ClkOut

Data

Clk

Out

CMOS

D1

Clk

D1K

Clk

D2

Clk

SDL

Clk

PLATCH

Clk


Bibliography


Domino References

K. Bernstein, et al., High Speed CMOS Design Styles, Kluwer Academic Publishers, 1998.

A good modern survey of different circuit styles.

R. Gu, et al., High-Performance Digital VLSI Circuit Design, Kluwer Academic Publishers, 1996.

Discusses many different types of digital logic including several flavors of domino.

D. Harris and M. Horowitz, "Skew-Tolerant Domino Circuits", IEEE Journal of Solid State Circuits, pp. 1702-1711, 1997.

Describes removing static latches between domino phases in order toallow time borrowing.

D. Harris, Skew-Tolerant Circuit Design, Morgan Kaufmann Publishers, 2001.

Harris has expanded his JSSC paper into a very good very accessible textbook on time borrowing for both static and domino circuits.


Dynamic Circuits: Beyond basic domino

Kevin Nowka, IBM

EE-382M

VLSI–II


Agenda

• Review of domino

• Performance Enhancements

• Robustness Enhancements

• Power Enhancements

• Technology and dynamic logic

• Summary


Review of Domino Gate

Ft= AtBt(Cc+Dc) + Et

CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Logic PulldownNetwork


Review of Domino Timing

OtFc

CLK

FtOc

GtGc

ItIcLtch Ltch

eval pre eval preCLK

Ft/Fc

Gt/Gc

Ot/Oc

Dom Dom Dom


Performance – where does the time go?


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Precharge:- Collision (bad)- Charging dynamic node-Charging parasitic caps-Driving output node low

Evaluate:-Collision (bad)-Discharging parasitic caps-Pulling down dynamic node- Driving output node high


Performance Enhancements

• No foot

• Beta skew

• Predischarge

• Reset assist

• Tapering

• MODL (already covered)


Performance Optimization -- unfooted


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Foot device:+ prevents precharge-eval collision-- additional device in pulldown

-- delay (5-15%)-- clock load (>2X)-- input cap increased

To eliminate footer -- must explicitly manage precharge,

eval intervals ->delayed reset domino-- at least 1 input in stack must be off

during precharge


Footed vs. Unfooted Domino

Carry Merge Foot vs. Unfooted Delay

Source: Nowka, Galambos ICCD’98


Performance Optimization – beta ratio

Ft= AtBt(Cc+Dc) + EtCLK

At Et

PrechargeKeeper

Output Inv

Output Inverter PFET:-- pulls up output during evaluate: critical-- disables keeper

Output Inverter NFET-- pulls down output during precharge-- holds output low during standby-- enables keeper during standby

Skew beta ratio of inverter in favor of PFET-- faster-- reduced noise margin-- slow reset of output

-- can be mitigated with additional reset assist device

Wn

Wp


Performance vs. Beta

Carry merge circuit delay vs. Beta



Performance Enhancement – high beta w/ reset assist


At Et

PrechargeKeeper

Output Inv

Wn

Wp

Reset assist device

PC_h

PC_l


Performance Enhancement -- predischarge


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Predischarge Device:- drives parasitic node to gnd- forces charge sharing

-- faster (a couple %)-- keeper, dynamic node, beta

sufficient to overcome this!

CLK_b


Performance Enhancement – tapering up


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Tapering up (taper factor k)-more device width low in the stack-bottom fets need to sink charge from

-Dynamic node-All internal nodes above them-Gate leakage current

W ->W

W ->kW

W ->k2W

W ->k3W


Performance vs. Tapering UP

0.18um bulk CMOS process


Performance Optimization – topology changes

Topology change:+ latest arriving signal nearest dynamic node+ decrease dynamic node cap+ increase charge sharing!

A_late

B C

B

A_late C

C


Robustness Enhancements

• Keepers

• Anti-Q-sharing devices

• Beta ratios

• Topology changes

• Layout considerations


Robustness Optimization -- keeper


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Keeper device:+ Holds dynamic node high in standby+ sources current to overcome leakage

- junction leakage- subthreshold noise

+ sources current to mitigate Q sharing-slows down evaluate by a couple %

Can dynamic node be floating at a lowvoltage?


Robustness Enhancement – anti-Q-share


CLK

CLK

Cc

Bt

At

CLK

Et

Dc

PrechargeKeeper

Foot

Anti-Q-share

Output Inv

Anti-Q sharing:- Internal nodes capacitance from

-S/D parasitic-Contacts/Vias/Wires

- Precharge to Vdd with PFET, or-Vdd-Vtn with NFET, or..What needs to be precharged:- multiple fets at a point?- multi-fingered fets?- long wire runs?-Extract, analyze, and simulate!!


Robustness Optimization – Beta redux

Ft= AtBt(Cc+Dc) + EtCLK

At Et

PrechargeKeeper

Output Inv

No free lunch –Big Beta => Lower Noise Margin

Wn

Wp


DC, AC Noise margin vs. Beta



Robustness Optimization -- topology

Topology changes:+ to decrease leakage paths+ to decrease charge sharing+ to increase dynamic node cap+ to change noise margin of output stage



Topology change:+ to decrease leakage paths+ decreases charge sharing+ increases dynamic node cap

A

B CW

2W 2W

B

A CW

2W

C W



Topology changes:+ Decrease charge sharing

- or does it?+ Minimize leakage paths

- or does it?

S0

D0

S2

D2

S1

D1

S3

D3

S4

D4

S5

D5

S0

D0

S2

D2

S1

D1S3

D3

S4

D4

S5

D5



Topology changes:+ Decrease charge sharingX

At

Y

Ac

X Y

At Ac


Robustness Optimization – layout considerations

CLK

CLK

Cc

Bt

At

CLK

Et

Dc

Keep these wires short (Gate cap ok, wire BAD)

Min internal node cap – single finger, uncontacted, taper?

Nfet-Pfet spacing may make this a long wire! Use Nfet?

Only short wires here


Power (Energy!) Enhancements

• Strobing

• Latched output

• No foot

• No tapering

• Gated precharge

• MODL (already covered)


Power Optimization - Strobing

F = ABCCLK

CLK

C

B

A

F = ABCCLK

A B CDual rail => large

capacitance for two pulldown networks, 2output wires

Strobing – use a pulse to invert function

Don’t strobe too early!

Generally slower than DR

Do this where timing well controlled – memories, PLAs, latches

CLK

F = ABCCLK

F = ABCCLK

A B C

Strobe


Power Optimization – Latched output

Use a strobe to avoid 2 pulses on a 1-1 transition

Strobe can be CLK or chopped CLK

Don’t latch a precharge

CLK

CLK

A B C

Strobe

Ft

F_latched

1-1 transition wastes power

F_latched


Power Optimizations – foot and tapering BACK

CLK

CLK

Cc

Bt

At Et

Dc

W -> X

Output Inv

Eliminating footer decreases Cgate _pulldown by 39%

Tapering back (taper factor k=1.5)-tapering back decreases Cgate_pulldown by 31%

No foot+taper decreases Cgate by 60%

W ->0.33W

W ->0.5W

W ->0.75W

W/3 ->0.17W

Tapering BACK (taper factor k)

-less device width high in the stack

-top fets need to sink less charge


Performance vs. Tapering BACK

0.13um bulk CMOS process


Power Optimization – Gated precharge

Lots of added devices for very little savings

Only useful in limited situations

May need to buffer output F before the NAND

CLK

A B C

CLK

Dyn

Precharge with dynamic node hi wastes power

F

F

CLK


Effects of technology on dynamic circuits

• Leakage and noise trends

– Subthreshold

– SOI and bipolar leakage

– Gate leakage

• Low k inter and intra layer dielectrics, dual gate, active-well,

hi-Vts and lo-Vts,


Subthreshold leakage

• Subthreshold trends

– Vt decreasing, but not

according to scaling theory

– Vdd decreasing

– Traditional 5-order

magnitude Ion:Ioff

degrading to 3-4 O.M.

– Subthreshold really an issue

for low-Vts and SOI

At Et

PrechargeKeeper

Isub


Low-Vt leakage

• Low-Vt transistors have

– ~70 to 180mV lower Vt

– 5-15% faster

– 5x-100X more

leakage!

– Use sparingly

At Et

PrechargeKeeper

IsubloVt


Partially depleted SOI and leakage

• Floating body collects

charge due to impact

ionization at drain.

• Voltage on body is potential

on base terminal of bipolar

• Voltage on body also lowers

(or raises) Vt of MOSFET

• Increased leakage!!

At

PrechargeKeeper

Isub

BOX

S DGate oxGate

Floatingbody

Body

Parasitic bipolar


Effects of floating body on 2-and-4-or gate

1. X1..X4 high, Y1..Y4 low

2. Bodies of Tx1 to Tx4 float

high

• MOS Vt falls

3. X1..X4 low, Y1..Y4 high

• Bipolar current flows

4. Noise on X1..X4

• MOS subthreshold

leakage

Increase keepers, change

topologies, predischarge

intermediate nodes…

PrechargeKeeper

Body

Parasitic bipolar

X1

Isub

Y1

Ic

X4

Y4


Waveform of this scenerio

1.429e+08 5.022e+08 8.614e+08 1.221e+09 1.580e+091.000e-09

PC

-0.004

2.173

INTOP

-0.108

2.173

INBOT

-0.013

2.168

TOPBODY

0.421

2.022

Id_TOP

-0.203

0.006

DYN

1.345

2.235

OUT

-0.009

0.309

1.580e+09

2.089

0.000

0.006

0.000

0.006

0.000

0.624

0.000

0.001

0.000

2.221

0.000

0.001

0.000

1.580e+09

2.089

0.006

0.006

0.624

0.001

2.221

0.001

dt= 0.000e+00

Runs: soi.grf1 soi.grf1 soi.grf1 soi.grf1 soi.grf1 soi.grf1 soi.grf1 soi.grf1 soi.grf18 soi.grf19 soi.grf1 soi.

Source: CRC Computer Engr. Handbook, Ed. Oklobdzija 2002


Gate leakage

• Below 2.2 nm gate oxides

gate oxide tunneling

becomes a MAJOR issue.

• Unlike subthreshold, bipolar

leakage, not much we can

do:

– Keep Tox thicker

– High k oxide materials

– Lower voltage

• This is especially a thorn for

dynamic circuits

At Et

PrechargeKeeper

Ig


Other technology trends

• Low k dielectrics in wiring => decrease in coupled noise at

inputs and dynamic nodes

• Body biases, well biases, dual gate => can be used for increased

performance or to lower leakage

• Multiple Vts => more options in performance vs.

power/noise/leakage


Domino logic: Summary

1. Numerous ways to improve the performance of dynamic

2. Numerous ways to improve the robustness of dynamic

3. Numerous ways to improve the power consumption of dynamic

4. 1-3 not easily mutually satisfied….

5. HIGH PERFORMANCE domino is hand-crafted to avoid noise and power problems as well as get performance

6. Dynamic logic which is not high-performance doesn’t have a significant advantage over simpler static design.

7. Thus, today domino is largely full-custom, but many are trying to automate the design process.

8. Technology trends are a little disturbing – even more challenging

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