DMAPS (Depleted CMOS Pixels) developments at Bonn University · 2018. 11. 19. · DMAPS (Depleted...
Transcript of DMAPS (Depleted CMOS Pixels) developments at Bonn University · 2018. 11. 19. · DMAPS (Depleted...
DMAPS (Depleted CMOS Pixels) developments at Bonn University Collaboration w/ CPPM, IRFU, KIT, Prague, Strasbourg, SLAC on design, CERN, CPPM, Glasgow, Oxford, Göttingen, Ljubiljana on measurements
WP6 Session
Norbert Wermes
[email protected] AIDA-2020 - Ann-Mtg-Desy - 15.06.2016
The interest for the LHC HL-Upgrade
ATLAS Phase II Letter of Intent
Oc
cu
pa
nc
y [
%]
outer
Inner
Inner layers (10 MHz, 1 Grad, 1016/cm2)
1. Low power2. Low material3. Occupancy4. Resolution (5-10 µm)
hybrid pixels (65nm? + sensor?)
1. Low cost2. Low power3. Low material4. Resolution (10-20 µm)
low cost (monolithic) CMOS pixels
Outer layers (1 MHz, 50 Mrad, 1015/cm2)
goal: some (40 – 80 µm) depletion depth for … fast charge collection (< 25ns “in-time” efficient) a reasonably large signal ~4000 e- not too large a travel distance to avoid trapping (rad hardness) 2
Key points for DMAPS design
Technology key points for CMOS Pixels at LHC
HV add-ons
HR wafers
Multiple wells (≥4)
(back side processing)
Design key points
optimize cell geometry for speed and radiation tolerance
- reasonably large signal at low noise, sufficiently fast time stamping, homogeneous response
cope with additional inter-well capacitances
cope with cross talk (from digital activity) into sensor
Module key points
can one exploit the CMOS technology on module level to gain in physics performance?
e.g. can cooling be applied more directly and efficiently (thus saving material)?
can the module assembly be made less involved (less process steps, less human labour)?-> better overall yield?
can the overall material budget be reduced?
from: www.xfab.com
[email protected] AIDA-2020 - Ann-Mtg-Desy - 15.06.2016
Bulk process options (simple options, n-on-p)
Electronics inside charge collection well
Collection node with large fill factor rad. hard
Large sensor capacitance (deep nw/pw junction!) x-talk, noise & speed (power) penalties
Full CMOS through isolation between n-well and deep n-well
Electronics outside charge collection well
Very small sensor capacitance low power
Potentially less rad. hard (longer drift lengths)
Full CMOS with additional deep-p implant
p-substrate
Deep n-well
P+ p-well
Charge signal
Electronics (full CMOS)
P+nw
p-substrate
n+ p-well
Charge signal
Electronics (full CMOS)
n+nw
deep p-well
- -
larger capacitance makes it more difficult for fast R/O and noise -> more power
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Bonn DMAPS program
1. Prototypes: Characterization of different technology features together with different design approaches by dedicated prototypes (smart sensors) that can be characterized “stand alone” or “bonded to FE-I4”.
1. “Demonstrators”: Larger area (~1cm2) prototypes in few selected technologies.To avoid the (initially believed too challenging) on-chip R/O architecture, these prototypes were requested to be characterizable “stand alone” AND “bonded to FE-I4”.
2. Fully monolithic depleted CMOS pixel chips includingthe R/O architecture on-chip (FE-I3-like or different)
TID/fluence target at first:outer pixel layers (r > 25 cm)100 Mrad / 1015 neq/cm2
CCPD
Investigated Technologies w/ different designs
Technology comments collaborationdesign (D) & measm‘ts
prototype chips demonstratorchip
large fullymonolithic chip
Tower Jazz 180 nm, 1-3 kΩcm, epi
little dedicatedattention so far
Bonn (D), Strasbourg (D)
✓ ? Pegasus_1&2stand alone, monolithic
ESPROS150 nmHR: 2 kΩcm
back contact in process, generic design not for LHC
Bonn (D), Prague (D) ✓ EPCB01, EPCB02stand alone prototypes(not for HL-LHC)
XFAB 130 nm0.1 – 1 kΩSOI
SOI technology
Bonn (D), CERNCPPM, Ljubiljana
✓ XTB01, XTB01 planned ?! planned ?!
Toshiba130 nm3 kΩcm
designs not yetthoroughlytested
Bonn (D) ✓ TSB01
LFoundry130 nm2-3 kΩcm
extensive tests Bonn (D), CPPM (D), IRFU (D), SLAC (D), CERN, Glasgow, Oxford, Ljubiljana
✓ CCPD_LFCCPD_LF + FE-I4
✓ CCPD CPPM, IRFU, Bonn(subm. Feb. 16)
MONOPIX_01(Bonn, CPPM, IRFU)COOL_01 (SLAC) (subm. 6/2016)
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Main challenges @ HL-LHC
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• radiation tolerance (> 1015 neq, > 100 Mrad)
• speed / in-time efficiency(@ C = 200 fF and “low” power)
AIDA-2020 - Ann-Mtg-Desy - 15.06.2016
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ESPROS Photonic CMOS™
Chip size: 1.4×1.4 mm2
OHC15L • 150 nm process (deep N-well/P-well)• Up to 7 metal layers• Resistivity of wafer (n-type): >2000 Ω·cm• Backside processing included in fabrication• 50µm thin• not expected to be high-level radhard
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EPCB01
V1 V2 V3
V6 V5 V4
V2 V3
V5 V4
differentbiasing & feedbackvariants
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EPCB01 Fe55/Laser
Gain: ~ 100 µV/e (200 mV ~ 2 ke)Power: ~5uWPeaking time: <25nsShaping time: ~200ns - 2us (for continous reset)
Fe55 and baseline spectrum (single pixel 40x40um)
Backside laser scans (@~12V)
T. Obermann, Bonn
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Fano noise (signal fluct.) = 13 e-
electronic noise = 41 e-
threshold disp. (after tuning) ~ 40 e-
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ESPROS (initial irradiation results)
• Before irradiation: close to 100% efficient almost everywhere, , depletion depth ~50µm @ 5Vless efficient corners (70-80 %) due to threshold discrimination (binary output)
• After irradiation: ~80% efficient in central region, edge regions drop to low efficiencies (~10 %)
Vbias = +5 V Vbias = +7 V
require exactly one track per event
in-pixel efficiency (after 5 x 1014 neutrons/cm2)
N. Wermes, CERN CLIC Seminar, 01/16
CMOS on SOI
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• FD-SOI• OKI/LAPIS/KEK
Y. Arai et al., e.g. NIM. A636 (2011) 1, S31-S36
• issues- back gate effect- radiation issues due to BOX
• cures invented in recent years• proposed for ILC• but not suited for LHC - pp
• HV-SOI (thick film) Hemperek, Kishishita, Krüger, NW, NIM A796 (2015) 8-12
• a promising alternative• doped, non-depleted P- and N-wells
prevent back gate effect and increase the radiation tolerance
would be niceAIDA-2020 - Ann-Mtg-Desy - 15.06.2016
XFAB XT180
XT180: • XFab 180 nn HV-SOI• Up to 7 metal layers• Resistivity of wafer: 100 Ω·cm
XTB01 and XTB02 prototypes: • Pixel pitch: 15, 50, 100 µm• Chip size: 2.5 mm x 5 mm
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structuresto improveleakage cur.breal down v.
XTB01
XTB02
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XT180 – TID tolerance
NMOS PMOS
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threshold shift versus TID
1 Grad 1 Grad
acceptor removal (likely) sets in => resistivity increases => larger “drift” - volume
irradiated to5 x 1013 neq/cm2
90Sr
SOI - CMOS
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25 x 25 μm2
50 x 50 μm2
100 x 100 μm2
50 x 50 μm2
Test transistors
XTB02
XFAB 180 nm: CMOS electronics outside collection well • Small charge collection well -> small C • HV + medium-R (100 Ωcm), p bulk• 3 T readout only
TID: 700 Mradup to 5x1014 neq/cm2
S. Fernandez-Perez et al., NIM A796 (2015) 13-18
Fe-55 (1630 e-)
120 GeV pions
observation:charge collected fromhigh-field (fast drift) and low field (slow diffusion) regions
unirradiated
90Sr
XTB02
TCT, I. Mandić, B. Hiti et al.,Jožef Stefan Institute, Ljubljana, Slovenia
50 µm
LFoundry LF150
LFA150 process: • L-Foundry 150 nm process (deep N-well/P-well)• 4 well process => full CMOS• up to 7 metal layers• Resistivity of wafer: >2000 Ω·cm• Small implant customization• Backside processing
CCPD-LF prototype chip: 2 versions • Pixel size: 33um x 125 um (6 pix =2 pix of FEI4)• Chip size: 5 mm x 5 mm (24 x 114 pix) • Bondable to FE-I4• 300 µm and 100 µm thick version• Bonn + CPPM + KIT
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CCPD-LF/LF_B01
Process: LFoundry 150nm, 4-6 Aluminum Metal layers, 1.8 VSubstrate: CZ, p-type bulk, >2kOhm-cmPost processing: Thinning 100/300um, p-type implant, annealing, metallization
PW
P
P-substrate
DNWELL
NW
N
P+
GND
+-
N N NP P
NW
PSUB
VDD
PW
NI
NW
NI
P
GND
PWPW
5x5 mm2
24 x 114 pixels
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two versions
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CCPD-LF
Beam spectrum (LF Version A)Sensor reverse current
1013neq/cm2 1015neq/cm2
0neq/cm2
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100 nA
3 kΩcm
depletion depth
bias voltage
T. Hirono, Bonn
i.e. ~166 µmdepl. depth
ke
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CCPD-LF – Radiation damage
Collection with (edge-TCT)
Sepctrum of 55Fe and 241Am after 1015neq/cm2
TCT, I. Mandić, B. Hiti et al.,Jožef Stefan Institute, Ljubljana, Slovenia
T. Hirono, Bonn
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50 µm
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Thinned to 100µm (CCPD): back/front difference?
IV
Fe5
5fr
on
t/b
ack
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0u
mFe
55
fro
nt/
bac
k 1
00
um
T. Hirono, Bonn 25
300 µm
100 µm
Investigated Technologies w/ different designs
Technology comments collaborationdesign (D) & measm‘ts
prototype chips demonstratorchip
large fullymonolithic chip
Tower Jazz 180 nm, 1-3 kΩcm, epi
little dedicatedattention so far
Bonn (D), Strasbourg (D)
✓ ? Pegasus_1&2stand alone, monolithic
ESPROS150 nmHR: 2 kΩcm
back contact in process, generic design not for LHC
Bonn (D), Prague (D) ✓ EPCB01, EPCB02stand alone prototypes(not for HL-LHC)
XFAB 130 nm0.1 – 1 kΩSOI
SOI technology
Bonn (D), CERNCPPM, Ljubiljana
✓ XTB01, XTB01 planned ?! planned ?!
Toshiba130 nm3 kΩcm
designs not yetthoroughlytested
Bonn (D) ✓ TSB01
LFoundry130 nm2-3 kΩcm
extensive tests Bonn (D), CPPM (D), IRFU (D), SLAC (D), CERN, Glasgow, Oxford, Ljubiljana
✓ CCPD_LFCCPD_LF + FI-I4
✓ LFCPIX (CCPD)CPPM, IRFU, Bonn(subm. Feb. 16)
MONOPIX_01(Bonn, CPPM, IRFU)COOL_01 (SLAC) (subm. 6/2016)
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For the very cheap & large area .... passive CMOS pixels
C4 bumps: come with chip fabrication at low cost
• no bumping• do flip-chipping in-house (large pitch)• cheap large feature size technology• large sensors (reticle stitching)• wafer based flip-chipping (8“)• can have in-pixel AC coupling• fancy RDL possibilities by metal layers (watch C !)
• Question: how good are these CMOS sensors?
AC resistive bias
DC punch through
biasT. Hemperek, F. Hügging, H. Krüger, L. Gonella, J. Janssen, D. Pohl (UBonn), NWA. Macchiolo (MPI M) L. Vigani (Oxford)
Some first results
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-170 V• break down at 170 V• leakage 20 µA / cm3 (assuming 220 µm depletion,
estimated from simulation and indep. measurements)• compare: planar sensor ATLAS IBL: 15 µA/cm3
(assuming 200 µm depletion depth)
MPV at 16 600 e-@ 150 V bias
charge (e-)
noise
117 e-
133 e-
DC
AC
Thank you
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[email protected] AIDA-2020 - Ann-Mtg-Desy - 15.06.2016
RD53A – Next Hybrid Pixel Readout Performance
Parameter Value
Pixel size 50x50 or 25x100 µm2`
Analog power 4-5 µA/pixel -> 160-200 mA/cm2 (40-50 fF)
Digital power 4 µA/pixel -> 160 mA/cm2
Analog Threshold 500 e-
Charge Resolution 4-5 bits
Timing Resolution 25 ns
Hit Rate 3-4 Ghits/cm2
Trigger Rate 1-2 MHz
Trigger Latency 12.5 µs
Output Data Rata 5 Gbit/s
Powering schema serial
Size 400x400 pixels (2x2 cm2)
Analog power scales with input capacitanceDigital power scales with rate
...it is not linear
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