Digitales Lec8 ASM Givone SI
33
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 8-1 PowerPoint Slides to accompany Digital Principles and Design Donald D. Givone Chapter 8 Algorithmic State Machines
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Transcript of Digitales Lec8 ASM Givone SI
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
8-1
PowerPoint Slidesto accompany
Digital Principles and Design
Donald D. Givone
Chapter 8Algorithmic State Machines
Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Partitioning of a digital system.Figure 8.1
8-2
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8-3
Model of an algorithmic state machine.Figure 8.2
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8-4
Timing of an algorithmic state machine.Figure 8.3
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8-5
The state box.Figure 8.4
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8-6
The decision box. (a) Symbol. (b) Alternate symbol.Figure 8.5
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8-7
The conditional output box.Figure 8.6
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8-8
Example of an ASM block and its link paths.Figure 8.7
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8-9
Two equivalent ASM blocks.Figure 8.8
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8-10
Two equivalent ASM blocks. (a) Using a single decision box. (b) Using several decision boxes.Figure 8.9
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8-11
Two equivalent ASM books blocks. (a) Parallel decision boxes. (b) Serial decision boxes.Figure 8.10
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8-12
Invalid ASM block having nonunique next states.Figure 8.11
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8-13
Looping. (a) Incorrect. (b) Correct. Figure 8.12
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8-14
ASM chart for a mod-8 binary counter.Figure 8.13
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8-15
ASM chart for a mod-8 binary up-down counter.Figure 8.14
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8-16
Moore sequential network. (a) State diagram. (b) ASM chart.Figure 8.15
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8-17
Mealy sequential network. (a) State diagram. (b) ASM chart.Figure 8.16
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8-18
ASM chart to recognize the sequence x1x2 = 01,01,11,00.Figure 8.17
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8-19
Binary multiplication. (a) Pencil-and-paper approach. (b) Add-shift approach.Figure 8.18
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8-20
Architecture for a binary multiplier.Figure 8.19
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8-21
ASM chart for a binary multiplier.Figure 8.20
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8-22
An ASM chart.Figure 8.21
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8-23
A minimum state locus assignment for the ASM chart of Fig. 8.21. (a) State-assignment map. (b) State locus.Figure 8.22
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8-24
Karnaugh map for simplifying the function of Table 8.1b.Figure 8.23
1Q
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8-25
Discrete-gate realization with clocked D flip-flops for the ASM chart of Fig. 8.21.Figure 8.24
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8-26
Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked D flip-flops for the ASM chart of Fig. 8.21.Figure 8.25
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8-27
Using variable-entered Karnaugh maps to obtain a discrete-gate realization with clocked JK flip-flops for the ASM chart of Fig. 8.21.Figure 8.26
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8-28
Assignment of inputs to a multiplexer for each excitation and output function.Figure 8.27
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8-29
Multiplexer realization with clocked D flip-flops for the ASM chart of Fig. 8.21.Figure 8.28
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8-30
Structure of a PLA realization for an ASM.Figure 8.29
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8-31
PLA realization with clocked D flip-flops for the ASM chart of Fig. 8.21.Figure 8.30
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8-32
Fragments of ASM charts illustrating problems associated with asynchronous inputs. (a) Transition race. (b) Output race.Figure 8.31
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8-33
Using a clocked D flip-flop to synchronize an asynchronous input.Figure 8.32
