DIGITAL VLSI DESIGN (ECE419T)Continuous assessment test 1

Set A

1. Design a Moore Network for Binary Adder.(8)2. Design a Mealy Network for recognizing sequence 0110/1001. (8)3. Assume an application running with a 33-MHz write clock, an 8-MHz read clock, a 9-

ns maximum propagation delay time for the IR path, and a 5-ns setup time for IR to the next device, find the MTBF. (4)

All the Best

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DIGITAL VLSI DESIGN (ECE419T)Continuous assessment test 1

Set B

1. Design a Moore Network having a single input and single output. The output of the network, initially 0, is to change on the next input immediately following each even occurrence of input = 1. (8)

2. Design a Mealy Network for recognizing sequence 0110/1001. (8)3. With a 50-MHz write clock, a 12-MHz read clock, a 9-ns maximum delay, and a 5-ns

setup time, what will be the effect on MTBF. (4)All the Best

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