Digital Video Decoder/Encoder Module System:...

APPLICATION NOTE

Digital Video Decoder/Encoder Module System:

ENCMOD03 + I²C InterfacingAN97011

Abstract

Digital Video Decoder/Encoder Module System: ENCMOD03 + I²C Interfacing

Philips Semiconductors

Application NoteAN97011

2

Philips Electronics N.V. 1997

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copy-right owner.

The information presented in this document does not form part of any quotation or contract, is believed to beaccurate and reliable and may be changed without notice. No liability will be accepted by the publisher for anyconsequence of its use. Publication thereof does not convey nor imply any license under patent- or other indus-trial or intellectual property rights.

This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders. It contains a description of various evaluation boards as well as I²C-bus programming of the ICs.

The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video sig-nals to TV receivers or video cassette recorders.

This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analogue and digital signal processing.

Keywords


Author:



3

APPLICATION NOTE

Digital Video Decoder/Encoder Module System:

ENCMOD03 + I²C Interfacing

Thomas GrubeSystems Laboratory Hamburg,

Germany

Digital Video Encoder (DENC)SAA7120/21

Digital Video DecoderSAA7111(A), VIP, EVIP

I²C BusMultiMedia

Date: 7th Febuary 1996

AN97011

Summary




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This application note is intended to provide application support for Philips´ Digital Video Decoders and Encoders in addition to the application note AN96055. It contains a description of evaluation boards as well as I²C-bus pro-gramming of the ICs.

The Digital Video Decoder converts an analog video input signal into a digital output signal. This signal can be processed by a wide range of applications and fed to the Digital Video Encoder, which delivers analog video sig-nals to TV receivers or video cassette recorders.

This note gives a detailed description of the schematics and some hints how to design the PCB (Printed Circuit Board) with mixed analogue and digital signal processing.



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CONTENTS

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2. Digital Video Encoder Module ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. I²C-bus EEPROM on DECMOD01, ENCMOD02 and ENCMOD03 . . . . . . . . . . . . . . . . . . . . 10

4. Module System Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5. I²C-Bus Interface H6ACS38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6. I²C-Bus Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7. Programming tables for SAA7120/21 and SAA7111A . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8. Universal Register Debugger Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9. Tips for a PCB layout with analog and digital signal processing . . . . . . . . . . . . . . . . . . . . . . 15

10. PCB Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11. Appendix: Schematics and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

11.1.1 Top sheet of ENCMOD03. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711.1.2 Digital Video Encoder of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . . . . 1811.1.3 Inputs of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911.1.4 Outputs of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2011.1.5 Power Supply and EEPROM of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . 2111.1.6 I²C Interface H6ACS38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

11.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311.2.1 Top placement of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311.2.2 Routing of top layer of ENCMOD03. . . . . . . . . . . . . . . . . . . . . . . . . . . 2411.2.3 Routing of bottom layer of ENCMOD03. . . . . . . . . . . . . . . . . . . . . . . . . 2511.2.4 Routing of ground plane layer of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . 2611.2.5 Routing of power supply layer of ENCMOD03 . . . . . . . . . . . . . . . . . . . . . 2711.2.6 Routing and Placement of I²C Interface H6ACS38 . . . . . . . . . . . . . . . . . . . 28

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1. IntroductionThe Digital Video Decoder/Encoder Modules provide the basis to evaluate various Philips digital video decoders and encoders and give the opportunity to simply insert the modules into customized applications and systems. This application note is an extension to application AN96055 (Digital Video Decoder/Encoder Module System) and contains additional information about the module ENCMOD03 and I²C-bus interfacing (3V/5V level transla-tion).

On the following pages the schematics of the Digital Video Encoder Module ENCMOD03 are shown. The module can be operated in stand alone operation (colourbar generator) as well as extension to other systems like PCI-bridges, MPEG decoders or Video input/output systems.

The module has a socket for an I²C-bus EEPROM (e.g. PCF8582, PCF8594, PCF8598, X24164) in order to store data for initialization and for simple control functionality operated by a (future) microcontroller module. Soft-ware for IBM compatible personal computers enables access to all features and settings of the devices. It han-dles the I²C-bus via a printer port adaptor.

This modular concept was designed to combine different video decoders with various video encoders. Each module can be configured for several devices and packages without the necessity of having a new PCB. This could be achieved by using multiple footprints for one IC and some configurational parts. For interfacing a 26-pin and a 16-pin flat ribbon cable connector is used. The 26-pin YUV-Feature Connector is used for the signal path while the other one is used for power supply and I²C-bus.

2. Digital Video Encoder Module ENCMOD03The digital encoder module ENCMOD03 contains the encoder SAA7120/21 in QFP44 package. The digital data are accepted in CCIR 656 format (D1). The outputs of the D/A converters are fed through analog postfilters to the connectors.

To allow future ICs to be assembled on this module, some provisions have been done. The filters are assigned to the connectors, so that for each signal type the serial resistor and the filter can be optimized. The signals out of the D/A converters are routed via jumpers to adapt the different output modes of future ICs (JP22, JP23).

RGB signals can be fed to the future encoder via connector J3 . The RGB inputs are connected to the IC via optional resistor dividers to adapt the input voltage range and to terminate the lines.

The clock and synchronization signals can be fed to the encoder via jumper (JP10, JP11, JP15) when operating the slave mode (JP21 open). Using the encoder as clock master (JP21 closed) LLC is supplied by XCLK out of the SAA7120/21. The pins RCV1 and RCV2 can be configured to outputs via I²C-bus setting (see I²C-bus regis-ter 6Bh in datasheets) to provide horizontal and vertical synchronization signals.

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Fig.1 Location of ICs, jumpers and connectors on the ENCMOD03 PCB

QFP44

J5

J6

ENC03.wmf

JP3

JP1

JP2

J3

JP6

JP7

JP5

U1

JP12

U4

U2 U3

JP11

J1T1 T2 T3

JP8

JP9

JP4

JP10

JP15

JP21

DGND

AGND



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Remark:

The parts mentioned in Table 1 are only for evaluation purpose and can be omitted in an application.

TABLE 1 Configuration ENCMOD03Part Value Description

JP12closedopen

slaveaddress 88hslaveaddress 8Ch

JP8, JP9 closed connection of (5V-) I²C-bus to system connector

R55, R56 0R only stuffed, if no 3V to 5V adaption of I²C levels

R53, R54 3k stuffed for 3V to 5V adaption of I²C levels

Q2, Q3 BS170 stuffed for 3V to 5V adaption of I²C levels

R35 0R connection AGND to DGND near encoder

R34 open termination LLC

JP15 closed jumper LLC (clock from/to feature connector)

JP21closedopen

connects the XCLK output with the LLC input

JP11 HS/HREF to/from RCV2

JP10 VS to/from RCV1

J3 RGBinRGB input connector (for future ICs)R15,16,17,18,23,24,26,27 used to adapt input voltage range

T5 RESN testpin (active low reset input)

T7 TTXRQ testpin (output signal for teletext request)

T8 TTX testpin (input signal for teletext data)

R62, R63 0R connection of TTX and TTXRQ to system connector

JP19 to be stuffed for future ICs




R57, R59 0R to be left open for future ICs

R58, R60, R61 open to be stuffed 0R for future ICs

R64, R65, R66 0R to be left open for future ICs

JP2 additional pins for using a 60 pin header for JP1, JP2 and JP3

JP4 additional testpins connected to reserved pins on JP3

JP5JP6JP7

additional pins for using reverse connectors

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3. I²C-bus EEPROM on DECMOD01, ENCMOD02 and ENCMOD03The IC U1 on each module can be assembled with different IC types depending on the desired memory size. Additionally the I²C-bus device address can be adapted by soldering corresponding SMD resistors which is described in the tables below.

Note: The modules will be stuffed by default using the following slaveaddresses (8-bit notation):EEPROM - type:Decoder Modules: Encoder Modules:PCF8582x-2 A6h A8hPCF8594x-2: A4h, A6h, WP=1 A8h, AAh, WP=0PCF8598x-2: A0h, A2h, A4h, A6h, WP=1 A8h, AAh, ACh, AEh, WP=0X24164: 90h, 92h, 94h, 96h, 98h, 9Ah, 9Ch and 9Eh E0h, E2h, E4h, E6h, E8h, EAh, ECh and EEh

TABLE 2 Configuration of I²C-bus EEPROMsIC type Size Pin 1 Pin 2 Pin 3 Pin 7 Address Range

PCF8582x-2 256 bytes

A0:“0”“1”“0”“1”“0”“1”“0”“1”

A1:“0”“0”“1”“1”“0”“0”“1”“1”

A2:“0”“0”“0”“0”“1”“1”“1”“1”

PTC

A0h orA2h orA4h orA6h orA8h orAAh orACh orAEh

PCF8594x-2 512 bytes WP

A1:“0”“1”“0”“1”

A2:“0”“0”“1”“1”

PTCA0h and A2h orA4h and A6h orA8h and AAh orACh and AhE

PCF8598x-2 1024 bytes WP n.c.A2:“0”“1”

PTC A0h, A2h, A4h and A6h orA8h, AAh, ACh and AEh

X24164 2048 bytes

S0:“0”“1”“0”“1”“0”“1”“0”“1”

S1:“1”“1”“0”“0”“1”“1”“0”“0”

S2:“0”“0”“0”“0”“1”“1”“1”“1”

TEST

80h, 82h, 84h, 86h, 88h, 8Ah, 8Ch and 8Eh or90h, 92h, 94h, 96h, 98h, 9Ah, 9Ch and 9Eh orA0h, A2h, A4h, A6h, A8h, AAh, ACh and AEh orB0h, B2h, B4h, B6h, B8h, BAh, BCh and BEh orC0h, C2h, C4h, C6h, C8h, CAh, CCh and CEh orD0h, D2h, D4h, D6h, D8h, DAh, DCh and DEh orE0h, E2h, E4h, E6h, E8h, EAh, ECh and EEh orF0h, F2h, F4h, F6h, F8h, FAh, FCh and FEh

TABLE 3 Board Configuration for I²C-bus EEPROMsPin “0” “1” Remark

PTC or TESTR4: OPENR8: 0R

R4: 0RR8: OPEN

Leave pin PTC open; apply “0” to pin TEST

A2 or S2R5: OPENR9: 0R

R5: 0RR9: OPEN

A1 or S1R6: OPENR10: 0R

R6: 0RR10: OPEN

pin S1 (X24164) is inverted internally

WP, A0 or S0R7: OPENR11: 0R

R7: 0RR11: OPEN

WP: “1” --> write protect of upper 256[512] bytes“0” --> write enabled (only PCF8594[PCF8598])



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4. Module System ConnectorsThe YUV connector (feature connector) provides access to the digital YUV data input coming from a digital video decoder or from an MPEG video source supplied to a video encoder. Two YUV data formats are supported, 16-bit “decoder format” or 8-bit CCIR656 compatible (D1). The control lines are set either as inputs or outputs. The connector has the following pin assignment:

Pin 1, 3, 5, 7, 9, 11, 13, 15 UV0: UV7 digital UV data (not used on ENCMOD03)Pin 2, 4, 6, 8, 10, 12, 14, 16 Y0: Y7 digital CCIR656 dataPin 17 LLC digital clockPin 18 LLC2 (not used on ENCMOD03)Pin 19 CREF, clock reference (not used on ENCMOD03)Pin 20 HREF, optional horizontal reference (blanking)Pin 21 RTC, real time controlPin 22 HS, horizontal synchronisation pulsePin 23 digital groundPin 24 VS, vertical synchronisation pulsePin 25 DIRPin 26 digital ground

The 16-pin header for power supply and I²C-bus has the following pin assignment:

Pin 1 SCLPin 2 SDAPin 3, 9, 15, 16 reserved for future usePin 4 TTXRQ (teletext data request output from encoder)Pin 5, 6 digital power supply (5V)Pin 7, 8 digital groundlPin 10 TTX (teletext data input to encoder)Pin 11, 12 analog power supply (12V)Pin 13, 14 analog ground

On each module in addition (or as alternative) a 4 pin connector can be used for I²C-bus control:

Fig.2 I²C-bus connector pinnings

Note: Always supply the I²C-bus with pull-up resistors, but avoid too high currents (see I²C-bus specification).On each module pull-up resistors can be added (R1 and R2), but preferably only one pull-up should bedone on the I²C-bus master IC.

I2C_CON6.wmf

I2C-NEW

SCLGND

1234 SDA

+5V

using 3 additional pins,one out of the three common used pin configurations can be stuffed

I2C-NEW

SCLGND

1234 SDA

+5V

SDASCLGND+5V

SDA+5V

GNDSCL

1234

I2C-OLD(Europe)

SDA+5V

GNDSCL 1

234

I2C(US)

SDA

+5VGNDSCL

T1

T2T3

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5. I²C-Bus Interface H6ACS38For systems running in a 3.3V environment it is required to use an I²C-bus interface with 3.3V capability. The new Single Master Interface H6ACS38 with the IC 74HC9114D replaces former Single Master Interfaces with the IC 74LS05 (e.g. H3VS15), which is only suited for 5V. The new interface operates on the I²C-bus from 1.8V to 5V.

The 74HC9114 is a nine wide Schmitt-Trigger buffer with open drain inverting outputs, which are not clamped by diodes connected to VCC. This allows the device the operation as level shifter with the output to be pulled between GND and VOmax . There are three options to represent (or to support the internal) pull-up resistors at the input lines of the PC´s parallel port (see also schematics of H6ACS38 in appendix):

1.) the databits at portpins 2 ~ 4 of the LPT connector (D-SUB25) are connected via 10k resistors R1 ~ R3 to pins 11, 12 and 15 (input lines)

2.) if VDD on the I²C-bus connector is high enough, the resistors R7 ~ R9 get the supply via diodes D4 ~ D63.) an external supply can be fed to R7 ~ R9 via diodes D1 ~ D3

The pull-up resistors on the interface to the PC side are supplied by unused databits which should be pro-grammed to “1” by the I²C-bus driver software. Together with the LPT-internal pull-ups this should operate. Due to the various different implementations of parallel port interfaces (LPT) in Personal Computers in a few cases it could be required to add an additional supply voltage of 5V to the interface to meet the correct input levels. Therefor two pads are foreseen on the interface PCB (named “+5V” and “GND”).

If the databits are set to “0”, R1 ~ R3 act as load and decrease the signals. If no external 5V supply is available, it is then possible to remove R1 ~ R3. In that case, the LPT portpins must have their own pull-ups.

The I²C-bus driver ´Í2CDRV.DLL´ (96-03-22 10:46, 52192 byte; supplied with the Universal Register Debugger software) switches the databits to “0” during a start condition, but this does not influence the I²C transmission. The driver ´I2CAPI.DLL version 1.0.0.3´ (supplied with several tools from the Systems Laboratory Hamburg) tests in addition the performance of the LPT-port signals. If the low to high transition is too slow (more than 1µs), the interface detection will fail. This can be caused by too high ohmic pull-up resistors or too much capacitive load due to long interface cables (e.g. 25 pin flat ribbon cable). In some configurations (e.g. PC-Laptop with capacitors at LPT-portpins; Error message: ´No I2C device on parallel port´) two additional pull-up resistors (1...4k7) should be added to the input pins 1 and 3 of the 74HC9114. They can be either connected to VCC or to another unused portpins (like R1~R3 and R7~R9; e.g. use with pins 5~8 of SUB-D 25pin connector).

The DTV (MPC-E) debugger software (versions 1.0x) does not affect the databits, so that they remain in their prior state. This can cause problems when the I²C-bus supply is less than 5V and the bits are “0” (workaround: see above).

The software IICTV (and related DOS based software packages from Philips Semiconductors) set the databits to “1” so that no problems are expected with R1~R3.

The lower the supply voltage of the I²C-bus the lower the pull-up resistors have to be, to ensure a specific current. Additionally noise margins get smaller and voltage drops over serial resistor become more important. These things have to be considered for designs with low voltage I²C-bus.



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6. I²C-Bus Level ShifterOn the Encoder Module ENCMOD03 a circuit was implemented to allow the connection of the internal 3.3V I²C-bus to an external 5V I²C-bus connected via the 16pin system connector (the external I²C-bus has to provide its own pull-up resistors). The circuit also operates with 3.3V levels on the system connector, but if no level conver-sion is necessary, the circuit can be removed (R53, R54, Q2, Q3) and bypassed with resistors R55 and R56.

The N-channel enhancement mode vertical D-MOS transistors Q2 and Q3 allow the bi-directional I²C-bus opera-tion while shifting the levels. If the bus lines are pulled high (e.g. I²C-bus is inactive) the transistor is in high ohmic state (VGS ~ 0V). If the Source is pulled to GND (3.3V side), VGS exceeds VGS(th) and the transistor conducts so that the Drain is also forced to the level of the Source (low). If the Drain is pulled to GND, the parasitic diode con-ducts and the Source is also pulled down.

The lower the voltage on the I²C-bus, the more important is the threshold voltage VGS(th) of the transistor. For 3.3V environment, several types can be used (e.g. BSS123 in SOT123 envelope on ENCMOD03). For lower volt-ages it is recommended to use e.g. BSS138 (SOT123) or BS108 (TO92).

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7. Programming tables for SAA7120/21 and SAA7111A

INITeI2C.wmf7120 07.02.96

SAA7120/21:- init data NTSCSlave: 88hSub DataREG 3a = 13 (93)REG 5a = 77REG 5b = 76REG 5c = a5REG 5d = 2a (aa)REG 5e = 2eREG 5f = 2eREG 60 = 00REG 61 = 15REG 62 = 3f (bf)REG 63 = 1fREG 64 = 7cREG 65 = f0REG 66 = 21REG 67 = 00REG 68 = 00REG 69 = 00REG 6a = 00REG 6b = 20REG 6c = 11REG 6d = 31REG 6e = 80REG 6f = 00REG 70 = 00REG 71 = 00REG 72 = 00REG 73 = 00REG 74 = 00REG 75 = 00REG 76 = 00REG 77 = 00REG 78 = 00REG 79 = 00REG 7a = 00REG 7b = 00REG 7c = 00REG 7d = 00REG 7e = 00REG 7f = 00

I2C1120d.mem

SAA7120/21:- init data PALSlave: 88hSub DataREG 3a = 13 (93)REG 5a = 77REG 5b = 7dREG 5c = afREG 5d = 23 (a3)REG 5e = 35REG 5f = 35REG 60 = 00REG 61 = 06REG 62 = 2f (af)REG 63 = cbREG 64 = 8aREG 65 = 09REG 66 = 2aREG 67 = 00REG 68 = 00REG 69 = 00REG 6a = 00REG 6b = 20REG 6c = 01REG 6d = 30REG 6e = a0REG 6f = 00REG 70 = 00REG 71 = 00REG 72 = 00REG 73 = 00REG 74 = 00REG 75 = 00REG 76 = 00REG 77 = 00REG 78 = 00REG 79 = 00REG 7a = 00REG 7b = 00REG 7c = 00REG 7d = 00REG 7e = 00REG 7f = 00

I2C1120d.mem

SAA7111A:- init data

Slave: 48hSub Data00h 00h01h 00h02h D0h (D5h)03h 00h04h 00h05h 00h06h F9h07h E9h08h A8h (2Eh,6Eh)09h 00h (80h)0Ah 80h0Bh 47h0Ch 40h0Dh 00h0Eh 00h0Fh 00h10h D0h11h 0Ch12h 01h1Fh 87h

I2C1120d.mem

Values in brackets:register 3Ah: Colourbar onregister 5Dh: only use with revision SAA7120/21 V0register 62h: Real Time Control (RTCE) enabled

Values in brackets:register 02h: select S-Video inputregister 08h: H-PLL opened (50Hz/60Hz forced)register 09h: Luma bypass for enhanced S-Video performance

The data tables below show the programming for the SAA7120/21 for operation with SAA7111A (e.g. DECMOD01 connected to ENCMOD03)



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8. Universal Register Debugger SoftwareYou can install the Universal Register Debugger Software by simply running the SETUP.EXE on the floppy disk. Afterwards you should copy the subdirectory \URDDATA from floppy disk to harddisk. The file \URD-DATA\11A20TG1.URD contains startup information (and a few macros) for the SAA7111A (EVIP) and SAA7120 (CONDENC). The I²C-bus Single Master Interface has to be connected to a printer port and to the Decoder/Encoder Modules. After powering up the hardware and calling the software, the CVBS2 input (J3, DECMOD01) accepts PAL-B/G input signals to be encoded on the ENCMOD03. The following macros can be used (Macro / Do Macro):

VIP S-Video in: selects input S-Video (J5) of DECMOD01 (AI12, AI22 of SAA7111A)VIP CVBS2 in: selects input CVBS2 (J3) of DECMOD01 (AI11 of SAA7111A)7120 NTSC: SAA7120 setup for NTSC-M7120 PAL: SAA7120 setup for PAL-B/GCB PAL: enables Colourbar Generator Mode of SAA7120;

opens H-PLL of SAA7111A and forces 50HzNote: only use this macro in conjunction with 7120 PAL macro

CB NTSC: enables Colourbar Generator Mode of SAA7120;opens H-PLL of SAA7111A and forces 60HzNote: only use this macro in conjunction with 7120 NTSC macro

CB off: switches colourbar off; closes H-PLL again

On a slow PC it might take a few seconds to run the macros (~10s for 7120 PAL/NTSC on a 386DX33).

The Universal Register Debugger (URD.EXE dated 96-11-06) is a β-release. After starting the software it might be required to enlarge the window in horizontal direction to view and edit the values of the registers.

The URD-files on the disk do not claim to be perfect. Please check with latest datasheet. The file 11A20TG1.URD contains modified settings for SAA7120V0.

9. Tips for a PCB layout with analog and digital signal processing- use separate ground planes for analog and digital supply in one layer (no overlapping!)

- use separate supply planes for analog and digital with the same shape (or smaller) as ground(no overlap of analog supply with digital ground and vice versa!)

- if there are different (asynchronous) clock domains, use separate ground and supply planes(place the analog areas not in a direct neighbourhood; separate the clock domains)

- always use the inner layers for ground and supply planes (no signal layer in between!)

- try to keep digital signals away from analog areas

- place analog areas close to the border of a PCB

- avoid long tracks for analog signals

- place decoupling capacitors (22nF to 100nF) close to the power pins of the ICs

- prepare several provisions for connecting places for analog and digital ground on the PCB for further optimization on the final board

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10. PCB RevisionsDECMOD01: Version Package Device(s) Remarks

A1: PLCC68 SAA7110(A) PLCC socket stuffed; 26.800 MHz crystal A2: PLCC68 SAA7111 PLCC socket stuffed; 24.576 MHz crystal A3: LQFP64 SAA7111A 24.576 MHz crystal

ENCMOD02: A1: PLCC84 SAA7124/25/82/83 PLCC socket stuffed A2: QFP80 SAA7124 A3: QFP80 SAA7125 A4: LQFP64 SAA7124 A5: LQFP64 SAA7125 A6: PLCC84 SAA7182A/83A PLCC socket stuffed A7: QFP80 SAA7182A A8: QFP80 SAA7183A

ENCMOD03: A1: QFP44 SAA7120 I²C-bus level shifter 3V/5V stuffed A2: QFP44 SAA7120 I²C-bus 3.3V levels

Note:- ENCMOD02 Vers. A1~A8 should be combined with DECMOD01 Vers. A2 (5V I/O)- ENCMOD03 should be combined with DECMOD01 Vers. A3 (3.3V I/O)- ENCMOD03 and DECMOD01 Vers. A3 (3.3V I/O) should be used with I2C Single Master Interface H6ACS38- all Encoder Modules require a 27.000 MHz 3rd overtone crystal (only for master mode)

11. Appendix: Schematics and Layout

The schematics are made in OrCAD and the files can be delivered on request.

For the board layout GERBER files are available.

11.1 Schematics



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11.1.1 Top sheet of ENCMOD03

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eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

OU

TP

UT

S

CV

BS

/Y

CV

BS

/C

CV

BS

/R

Y/G

C/B

VDDa

CS

YN

C

RC

V1

HS

INP

UT

S

VS

HS

HR

EF

SD

A

TT

X

RT

C

SC

L

Y[0

..7]

VDD5Vd

VDD12Va

TT

XR

Q

LLC

PO

WE

R S

UP

PLY

& E

EP

RO

M

SD

A3

SC

L3

VD

Ddig

VD

Da

VD

D12V

a

VD

D5V

d

CO

ND

EN

C

Y[0

..7]

VS

HS

HR

EF

TT

X

RT

C

SD

A

SC

L

VDDa

VDDdig

CV

BS

/Y

CV

BS

/C

CV

BS

/R

Y/G

C/B

CS

YN

C

LLC

TT

XR

Q

SD

A3

SC

L3

RC

V1

Y[0

..7]

Y[0

..7]

18




11.1.2 Digital Video Encoder of ENCMOD03

A A

B B

C C

D D

E E

44

33

22

11

SA

A7

12

0/2

1 Q

FP

44

Mo

du

le

AG

ND

/DG

ND

Tu

esd

ay,

Octo

be

r 0

8,

19

96

EN

C0

3a

.dsn

1.0

CO

ND

EN

C

Ph

ilip

s S

em

ico

nd

ucto

rs S

yste

ms L

ab

ora

tory

Ha

mb

urg

So

ftw

are

an

d M

ultim

ed

iaD

eco

de

r/E

nco

de

r M

od

ule

Syste

mT

.Gru

B

25

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

RC

V2

_T

TX

SE

L_

in

VD

D1

B_

inG

_in

R_

in

_T

TX

RQ

LLC_

XT

AL

VD

DA

1

Y3

Y6

Y7

Y2

Y5

Y[0

..7

]

Y0

Y4

Y1 R

CV

1

SA

XT

AL

I

RE

SN

XC

LK

VD

DA

1

VD

D1

SD

A3

SC

L3

SC

L3

D

D

A

A

A

A

D

D

DA

D

C1

51

0p

C1

81

0p

C2

11

n

C2

0

10

0n

C1

7

10

0n

C2

6

10

0n

C2

5

10

0n

R3

1

47

k

X1

27M

Hz

R3

5

0R

JP

11

JUM

P3

HS

YN

C

R2

30

R

R2

60

R

R2

40

R

R2

70

R

J3

5P

CO

NN

RG

B-C

ON

11

22

33

44

55

R1

51

kR

16

75

R

R1

77

5R

R1

87

5R

C2

4

10

0n

R34OPEN

JP

10

JUM

P2

VS

JP

12

JUM

P2

I2C

_A

DR

JP

15 JU

MP

2LL

C

T7

TS

TP

TT

XR

QT

8T

ST

PT

TX

L1

10

uH

L3

2u

H2

L4

2u

H2

R5

2

10

k

C2

24

u7

+

C1

9

4u

7

+

JP

21

JUM

P2

R5

90

RR

60

OP

EN

R5

70

RR

58

OP

EN

R6

1O

PE

N

T5

TS

TP

RE

SN

C1

6

10

0n

C5

2

10

0n

R5

43

k

R5

5O

PE

N

R5

6

OP

EN

R5

33

k

U4

SA

A7

12

0_

44

p

Con

DE

NC

AP 3SP2

TT

X4

4

MP

79

MP

61

0

MP

31

3

MP

51

1

SA 21

RESN40

CV

BS

30

Y2

7

C2

4

LLC 4SCL

41

SDA42

MP

41

2

MP

21

4

MP

11

5

MP

01

6

RC

V1

7R

CV

28

XT

AL

34

XT

AL

I3

5

VSS.0 5

VDD3.117 VDD3.239

VDD3.06

VSSA.1 32

TT

XR

Q4

3

RT

CI

19

RES.1 1RES.2 20

VDDA3.125 VDDA3.228 VDDA3.331 VDDA3.436

VSS.118

RES.526

RES.3 22

VSS.2 38

RES.4 23

RES.6 29

XC

LK

37

VSSA.2 33

J1

4P

CO

NN

11

22

33

44

T3

TS

TP

SC

L

T1

TS

TP

SD

A

T2

TS

TP

DG

ND

Q3

BS

107

BS

107

BS

P12

6B

ST

76A

BS

170

S

G

D

Q2

BS

107

BS

107

BS

P12

6B

ST

76A

BS

170

S

G

D

P2

AG

ND

GN

D

P1

DG

NDG

ND

Y[0

..7

]

CV

BS

/Y

CS

YN

C

C/B

Y/G

CV

BS

/R

RT

C

VD

Dd

ig

VD

Da

VS

HS

LL

C

HR

EF

CV

BS

/C

Y[0

..7

]

VD

Dd

ig

SC

L

SD

A

SD

A3

SC

L3

TT

XR

Q

TT

X

RC

V1

RC

V2

_T

TX

SE

L_

in

VD

D1

B_

inG

_in

R_

in

_T

TX

RQ

LLC_

XT

AL

VD

DA

1

Y3

Y6

Y7

Y2

Y5

Y0

Y4

Y1 R

CV

1

SA

XT

AL

I

RE

SN

XC

LK

VD

DA

1

VD

D1

SD

A3

SC

L3

SC

L3



19


11.1.3 Inputs of ENCMOD03

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

AA

BB

CC

DD

mal

e co

nnec

tors

fem

ale

conn

ecto

rs(o

ptio

nally

)

SA

A7

12

0/2

1 Q

FP

44

Mo

du

le

Tuesd

ay,

Oct

ober 08, 1

996

EN

C03a.d

sn

1.0

INP

UT

S

Ph

ilip

s S

em

ico

nd

ucto

rs S

yste

ms L

ab

ora

tory

Ha

mb

urg

Softw

are

and M

ultim

edia

Decoder/

Encoder

Module

Syste

mT

.Gru

A

35

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

Y3

UV

7

UV

1

Y5

UV

5

Y7

Y0

UV

0

Y6

Y2

UV

2

UV

4U

V3

Y4

UV

6

Y1

VD

D12V

a

SD

A_ext

SC

L_ext

VD

D12V

a

VD

D5V

d

UV

[0..7]

res1

res3

res5

res2

res4

res6

res1

res2

res3

res4

res5

res6

Y3

Y5

Y7

Y0

Y6

Y2

Y4

Y1 SD

A_ext

VD

D12V

a

VD

D5V

dre

s2

res4

res6N

C0

NC

1N

C2

NC

3N

C4

NC

6N

C7

NC

8

NC

[0..8]

NC

5

NC

[0..8]

NC

0N

C1

NC

2N

C3

NC

4

NC

6N

C7

NC

8

NC

5

VD

D5V

d

SC

LS

DA

TT

Xre

s4

TT

XR

Qre

s2

DD

AA

DD

D

AD

JP

2

HE

AD

ER

9X

2

12

34

56

78

910

11

12

13

14

15

16

17

18

JP

1

HE

AD

ER

13X

2

12

34

56

78

910

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

JP

3

HE

AD

ER

8X

2

12

34

56

78

910

11

12

13

14

15

16

JP

4

HE

AD

ER

6

1 2 3 4 5 6

JP

5

HE

AD

ER

13

1 2 3 4 5 6 7 8 910

11

12

13

JP

6

HE

AD

ER

9

1 2 3 4 5 6 7 8 9

JP

7

HE

AD

ER

8

1 2 3 4 5 6 7 8

R3

0R

JP

9 JUM

P2

SC

LJP

8 JUM

P2

SD

A

T13

TS

TP

DIR

R62

0R

R63

0R

UV

[0..7]

NC

[0..8]

NC

[0..8]

CR

EF

RT

CH

S

VS

Y[0

..7]

LLC

LLC

2

HR

EF

UV

[0..7]

HS

VS

Y[0

..7]

LLC

2

HR

EF

VD

D5V

d

VD

D12V

a

TT

X

TT

XR

Q

SC

L

SD

A

Y3

UV

7

UV

1

Y5

UV

5

Y7

Y0

UV

0

Y6

Y2

UV

2

UV

4U

V3

Y4

UV

6

Y1

VD

D12V

a

SD

A_ext

SC

L_ext

VD

D12V

a

VD

D5V

dre

s1

res3

res5

res2

res4

res6

res1

res2

res3

res4

res5

res6

Y3

Y5

Y7

Y0

Y6

Y2

Y4

Y1 SD

A_ext

VD

D12V

a

VD

D5V

dre

s2

res4

res6N

C0

NC

1N

C2

NC

3N

C4

NC

6N

C7

NC

8

NC

5

NC

0N

C1

NC

2N

C3

NC

4

NC

6N

C7

NC

8

NC

5

VD

D5V

d

SC

LS

DA

TT

Xre

s4

TT

XR

Qre

s2

20




11.1.4 Outputs of ENCMOD03

A A

B B

C C

D D

E E

44

33

22

11

RedG

reen

Syn

c/H

S

SA

A7

12

0/2

1 Q

FP

44

Mo

du

le

Blu

e

VS

Tuesday, O

cto

ber 08, 1996

EN

C0

3a

.dsn

1.0

OU

TP

UT

S

Ph

ilip

s S

em

ico

nd

ucto

rs S

yste

ms L

ab

ora

tory

Ha

mb

urg

So

ftw

are

an

d M

ultim

ed

iaD

eco

de

r/E

nco

de

r M

od

ule

Syste

mT

.Gru

B

45

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

C_

F

Y_

F

CV

BS

1_F

CV

BS

2_F

B_

F

G_

F

R_

F

DA

A

AA

A

A

AA

A

A

A

A

A

A

C3

43

90

pC

35

56

0p

C3

75

60

pC

36

39

0p

C3

93

90

pC

40

56

0p

C4

23

90

p

C4

83

90

p

C4

63

90

p

C3

21

20

p

C4

51

20

p

C4

11

20

p

C3

31

20

p

C4

75

60

p

C4

95

60

p

C4

35

60

p

C4

41

20

p

C3

81

20

p

R4

91

k

C5

01

00

n

R4

5

1k

R4

4

OP

EN

R4

7O

PE

N

R4

2

13

R

R3

8

8R

C3

15

60

pC

30

39

0p

C2

91

20

p

R3

7

27

R

R4

1

27

R

R4

8

OP

EN

R4

3

0R

R4

6

75

R

R5

00

R

R5

10

R

JP

19

JUM

P3

C-H

S JP

20 JU

MP

2

VS

YN

C

J7

DB

15

VG

A

510

49382716

15

14

13

12

11

J6

SV

HS

CO

NY

CY3

C4

GN

D2

GN

D1

L7

2u

H7

L1

5

2u

H7

L1

7

2u

H7

L1

3

2u

H7

L8

2u

H7

L1

2

2u

H7

L1

6

2u

H7

L1

1

2u

H7

L1

8

2u

H7

L1

4

2u

H7

L1

0

2u

H7

L9

2u

H7

L6

2u

H7

J5

CY

NC

H

CV

BS

1

J4

CY

NC

H

CV

BS

2

R3

9

27

R

R4

0

13

R

Q1

BC

850B

L5

2u

H7

R3

6

8R

JP

22

JU

MP

7

JP

23

JU

MP

5

R6

40

R

R6

60

R

R6

50

R

HS

VD

Da

CV

BS

/R

C/B

CS

YN

C

CV

BS

/Y

Y/G

CV

BS

/C

RC

V1

C_

F

Y_

F

CV

BS

1_F

CV

BS

2_F

B_

F

G_

F

R_

F



21


11.1.5 Power Supply and EEPROM of ENCMOD03

A A

B B

C C

D D

E E

44

33

22

11

SA

A7

12

0/2

1 Q

FP

44

Mo

du

le

Tuesday, O

cto

ber

08, 1996

EN

C03a.d

sn

1.0

Pow

er S

uppl

y an

d E

EP

RO

M

Ph

ilip

s S

em

ico

nd

ucto

rs S

yste

ms L

ab

ora

tory

Ha

mb

urg

Softw

are

and M

ultim

edia

Decoder/

Encoder

Module

Syste

mT

.Gru

A

55

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

VD

D12V

a

VD

D5V

d

VD

Ddig S

1

Test

S0

S2

AA

AA

A

D

D

DD

DD

D

D

C8

100n

C10

100n

R13

18R

C6

100n

C4

100n

R10

OP

EN

R8

OP

EN

R4

OP

EN

R5

OP

EN

U1

X24164

S0

1

S1

2

S2

3S

CL

6

TE

ST

7

SD

A5

VD

Ddig

8

GN

D4

R7

OP

EN

R9

OP

EN

R6

OP

EN

R11

OP

EN

C51

100n

C9

10u

+C

7

4u7

+

C5

10u

+C

3

4u7

+

U2

7803

VI

1

GND 2

VO

3

U3

7803

VI

1

GND 2

VO

3V

DD

a

VD

Ddig

SD

A3

SC

L3

VD

D5V

d

VD

D12V

aV

DD

12V

a

VD

D5V

d

VD

Ddig S

1

Test

S0

S2

22




11.1.6 I²C Interface H6ACS38



23


11.2 Layout

11.2.1 Top placement of ENCMOD03

24




11.2.2 Routing of top layer of ENCMOD03



25


11.2.3 Routing of bottom layer of ENCMOD03

26




11.2.4 Routing of ground plane layer of ENCMOD03



27


11.2.5 Routing of power supply layer of ENCMOD03

28




11.2.6 Routing and Placement of I²C Interface H6ACS38

Top routing Bottom routing

Top placement Bottom placement

Digital Video Decoder/Encoder Module System:...

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