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Verilog HDL: A Guide to Digital Design and Synthesis

Digital Systems Design

Shyue-Kung Lu

Department of Electronic Engineering

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Verilog HDL: A Guide to Digital Design and Synthesis

Syllabus

Recommended Texts 1. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL,” Prentice Hall ( 新月圖書 ) References 1. Richard S. Sandige, “Digital Design Essentials,” Prentice Hall ( 開發圖

書 ) 2. John F. Wakerly, “Digital Design: Principle and Practices,” Prentice Hall ( 新月圖書 ) 3. M. Morris Mano, “Digital Design,” Prentice Hall, Third Edition ( 滄海書

局， 04-27088787) 4. M. Morris Mano, :Digital Logic and Computer Design Fundamentals,” Prentice Hall ( 新月圖書 )

Grades 1. 作業 25% 2. 期中考 30 % 3. 期末考 30% 4. Project 15% Project 以歷屆 FPGA 比賽題目為主

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Verilog HDL: A Guide to Digital Design and Synthesis

Digital Systems Design

Course Overview

Review of combinational and sequential logic design Introduction to synthesis with HDLs (Verilog HDL) Programmable logic devices (CPLD and FPGA) State machines, datapath controllers, RISC CPU Architectures and algorithms for computation Synchronization across clock domains Static Timing Analysis Fault simulation and testing, JTAG, BIST

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Verilog HDL: A Guide to Digital Design and Synthesis

Chapter 1-3Review of Digital Systems

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Verilog HDL: A Guide to Digital Design and Synthesis

Logic Level Ranges of Voltage for a Digital Circuit

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Verilog HDL: A Guide to Digital Design and Synthesis

Representations of a Digital Design

+

ba

out

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Z 0 1 0 1 0 1 1 0

A

B

C

D T

2

T 1

Z

Z = A' •B' •(C + D) = (A' •(B' •(C + D)))

True table

Logic expression

Gate netlistTransistor circuit

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Verilog HDL: A Guide to Digital Design and Synthesis

Basic Primitives

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Verilog HDL: A Guide to Digital Design and Synthesis

Some Common IC Gates

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Verilog HDL: A Guide to Digital Design and Synthesis

Typical IC Datasheet

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Verilog HDL: A Guide to Digital Design and Synthesis

Combinational Logic Circuit

Combinational circuit: logic circuit whose outputs at any time are determined directly and only from the present input combination.

A combinational circuit performs a specific information-processing operation fully specified logically by a set of Boolean functions.

Sequential circuit: one that employ memory elements in addition to (combinational) logic gates—their outputs are determined from the present input combination as well as the state of the memory cells.

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Verilog HDL: A Guide to Digital Design and Synthesis

Block Diagram of a Combinational Circuit

Combinational Circuit

n inputs m outputs

Fig. 4-1: Block Diagram of Combinational Circuit

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Verilog HDL: A Guide to Digital Design and Synthesis

Combinational Modules

Ripple Carry Adder Carry Look ahead Adder Binary Adder-Subtractor BCD Adder Magnitude Comparator Binary Multiplier Decoder/Encoder Priority Encoder Multiplexers/Demultiplexers Three-State Gates

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Verilog HDL: A Guide to Digital Design and Synthesis

Sequential Circuits

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Verilog HDL: A Guide to Digital Design and Synthesis

Synchronous Clocked Sequential Circuit

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Verilog HDL: A Guide to Digital Design and Synthesis

Clock Response in Latch and Flip-Flop

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Verilog HDL: A Guide to Digital Design and Synthesis

Setup time and Hold Time

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Verilog HDL: A Guide to Digital Design and Synthesis

DFF

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Verilog HDL: A Guide to Digital Design and Synthesis

JKFF

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Verilog HDL: A Guide to Digital Design and Synthesis

JKFF

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Verilog HDL: A Guide to Digital Design and Synthesis

Characteristic Tables and Equations

J K Q(t+1)

0 0

0 1

1 0

1 1

Q(t)

0

1

Q’(t)

No change

Reset

Set

Complement

D Q(t+1)

0

1

0

1

Reset

Set

T Q(t+1)

0

1

Q(t)

Q’(t)

No change Complement

Q(t + 1) = D (D Flip-Flop) Q(t + 1) = JQ’ + K’Q (JK Flip-Flop) Q(t + 1) = TQ’ + T’Q (T Flip-Flop)

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Verilog HDL: A Guide to Digital Design and Synthesis

DA = A x y

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Verilog HDL: A Guide to Digital Design and Synthesis

Mealy Machine

Outputs dependent on inputs and state variables.

Are inputs synchronized with clock?

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Verilog HDL: A Guide to Digital Design and Synthesis

Moore Machine

Comb.

Circuit

State

Registers

OutputInput

Outputs dependent on state variables only.

Comb.

Circuit

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Verilog HDL: A Guide to Digital Design and Synthesis

4-Bit Register

A register is a group of flip-flops, read/written as a unit.

A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter.

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Verilog HDL: A Guide to Digital Design and Synthesis

Register withParallel Load

1 1

1

1

1

1

0

0

0

0

0

0

0

0

I0

I1

I2

I3

I0

I1

I2

I3

I0

I1

I2

I3

0 0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

I0

I1

I2

I3

I0

I1

I2

I3

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Verilog HDL: A Guide to Digital Design and Synthesis

Shift Register

Edge trigger or level trigger?

1 01

11 01 00

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Verilog HDL: A Guide to Digital Design and Synthesis

Synchronous Counter

No need to go through a sequential logic design process.

The flip-flop in the least significant position is complemented with every pulse. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1.