DIGITAL SYSTEM FUNDAMENTALS

(ECE421)

VERILOG ASSIGNMENT

REPORT

STUDENT’S NAME: 1)

2)

3)

SUBMISSION DATE:

LECTURER’S NAME: MOHD. UZIR KAMALUDDIN

Introduction The objectives of this assignment are the following:

To learn how to draw logic circuits in Logisim 2.7.1 software

To learn how to simulate logic circuits using Logisim 2.7.1 software

To learn how to represent combinational and sequential logic circuits in Verilog HDL

To learn how to compile and simulate Verilog code using Icarus Verilog-v11 software

To learn how to display results of simulation in tabular and graphical form

Verilog is a powerful language, and writing code that produces hardware makes design and

debugging of that hardware much simpler than using a breadboard. As a result, it will be

realized that it is easy to logic design circuits of incredible complexity. Software design of

hardware (i.e., CAD, or computer-aided design) is the only way that modern computer

chips could be built. To try to design and test them by hand would be impossible.

In this assignment, the task is to write Verilog code for the following logic circuits, then to

compile and simulate it:

1. a combinational logic circuit

2. a counter (sequential logic circuit)

Part I: Combinational Logic Circuit

Circuit Design

The task given is to simulate the following logic circuit.

In order to obtain the output expression and the truth table for this circuit, the circuit is

drawn into the Logisim 2.7.1 software. Then the circuit is simulated.

The following are the results:

Truth table Output Expression K Map: SOP expression

Coding In order to write the Verilog code for the logic circuit, some additional information were

added to the circuit: the gates and connecting wires are labelled as shown for easy reference.

The circuit written in Verilog HDL using structural model is as follows and is saved as

verilogreport.v written using Notepad. The testbench code is to provide inputs to the circuit

for the simulation purposes.

module circuit1(x, y, z, f);

input x, y, z;

output f;

wire s1, s2, s3, s4, s5;

not N1(s1, x);

not N2(s2, z);

and A1(s3, s1, z);

and A2(s4, x, s2);

and A3(s5, x, y);

or G1(f, s3, s4, s5);

endmodule

//******************Testbench code*************************

module testcircuit;

reg x, y, z;

wire f;

circuit1 uut(.x(x), .y(y), .z(z), .f(f));

initial begin

$dumpfile("veri1.vcd"); //for GTKwave

$dumpvars(0); //

$monitor(" x=%b, y=%b, z=%b, f=%b", x, y, z, f); //for tabular output

x=0; y=0; z=0;

#1 x=0; y=0; z=1;

#1 x=0; y=1; z=0;

#1 x=0; y=1; z=1;

#1 x=1; y=0; z=0;

#1 x=1; y=0; z=1;

#1 x=1; y=1; z=0;

#1 x=1; y=1; z=1;

#1 $finish;

end

endmodule

Simulation Results The simulation results obtained is as follows:

1. Tabular output

2. Graphical output

Conclusions The combinational logic circuit is successfully simulated using Logisim 2.7.1 and its Verilog

code is written. The compilation and simulation of the Verilog code is done using Icarus

Verilog v11. No compilation error is reported and the output from the simulation is

obtained. It is verified that the results from both simulations are the same.

Part II: Sequential Logic Circuit

Circuit Design The task given is to design and simulate a synchronous counter. The counter is a 2 bit

counter that produces the counting sequence 3-1-2-0. The flip-flop used is the falling edge JK

flip-flop with active high reset.

a) State Diagram

b) State table c) Flip-Flop Excitation Maps

3

1

2

0

Present state Next State

A B A B

0 0 1 1

0 1 1 0

1 0 0 0

1 1 0 1

A 0 1

B 0 α β

1 α β Transition Symbol

Flip-Flop A 0 -> 1 α

1 -> 0 β

A 0 1 0 -> 0 0

B 0 α 0 1 -> 1 1

1 β 1

Flip-Flop B

c) Flip-Flop Excitation Expressions.

Reading rules: For J must read all α (optional read β, 1, x) but cannot read 0 and

for K must read all β (optional read α, 0, x) but cannot read 1.

From Flip-Flop A map: JA = 1 and KA = 1

From Flip-Flop B map: JB = and KB =

d) Circuit

e) Output

Coding The circuit written in Verilog HDL using behavioural and structural models is as follows

and is saved as synctrjkff.v written using Notepad. The testbench code is to provide the clock

and reset signals to the counter for operation.

The circuit is relabelled to facilitate coding.

//**************JK Flip flop********************

module jkff(j, k, clock, reset, q, qb);

input j, k, clock, reset;

output reg q, qb;

always@(negedge clock)

begin

case({reset, j, k})

3'b000 : q = q; //no change

3'b001 : q = 0; //reset

3'b010 : q = 1; //set

3'b011 : q = ~q; //toggle

default : q = 0; //reset

endcase

qb <= ~q;

end

endmodule

//*********************Synchronous Counter***********************

module syncounter(clock, reset, q);

input clock, reset;

output [1:0]q;

wire x1;

jkff FFA(.j(1'b1), .k(1'b1), .clock(clock), .reset(reset), .q(q[1]), .qb(x1));

jkff FFB(.j(x1), .k(x1), .clock(clock), .reset(reset), .q(q[0]), .qb());

endmodule

//************************Testbench*************************

module count_tb;

reg clock, reset;

wire [1:0]q;

syncounter uut(.clock(clock), .reset(reset), .q(q));

initial clock=0;

always #1 clock=~clock; //clock waveform

initial begin

$dumpfile("syncnter.vcd");

$dumpvars(0);

$monitor(" QA=%b QB=%b Count=%d", q[1], q[0], q);

reset=1;

#2 reset=0;

#20 $finish;

end

endmodule

Simulation Results The simulation results obtained is as follows:

1. Tabular output

2. Graphical output

Conclusions The sequential logic circuit (2 bit synchronous counter, counting 3-1-2-0) is designed and

successfully simulated using Logisim 2.7.1 and its Verilog code is written. The compilation

and simulation of the Verilog code is done using Icarus Verilog v11. No compilation error is

reported and the output from the simulation is obtained, both in tabular and graphical form.

It is verified that the results from both simulations are the same.