DIGITAL SIGNAL PROCESSING FOR DEEP SPACE TRANSPONDER

L. Simone (1), S. Cocchi (1), M. D’Attilia (1), M. Delfino (1), A. Delfino (1), G. Boscagli (2)

(1) Alenia SpazioVia Marcellina 11 - 00131 Rome (Italy)

Email: l.simone@roma.alespazio.it

(2) Formerly Alenia Spazio, now ESAEmail: G.Boscagli@esa.int

INTRODUCTION

The progress of Digital Signal Processing techniques and the improvements of the Very Large Scale Integration (VLSI)technologies allow the implementation of digital modem for Deep Space Transponder (DST). Accordingly, a new classof DST based on digital architecture has been developed by Alenia for the ESA next Deep Space Missions (Rosetta,Mars Express). Besides, the digital-based design makes the proposed architecture suitable for a wide range of spaceapplications other than deep space missions.Traditionally, DST provides up-link carrier tracking, command data demodulation, ranging signal turn-around anddown-link carrier generation and modulation. The receiver digital architectures have the following advantages withrespect to a fully analog solution:• Receiver reconfigurability (for carrier loop bandwidth) according to the received signal input power• Easy implementation of narrow loop bandwidths• Inclusion of data demodulation capability• Data rate flexibility with matched filtering implementation• Interface optimization based on the extensive use of command and telemetry housekeeping in digital format• Design flexibility with receiver tuning based on software constants• On-board regenerative ranging.Besides the frequency synthesis and the modulation process based on Numerically Controlled Oscillator (NCO) offer agreat flexibility in terms of channel selection, data rate, modulation format and spectral shaping.This paper is presented in three sections. The first section provides an architectural overview of a digital DST. Thesecond part offers in-depth description of the implemented algorithms and functions. Finally, the third part deals withthe employed technology.

DEEP SPACE TRANSPONDER ARCHITECTURE

Fig.1 shows the Alenia DST architecture developed for Rosetta and Mars Express missions. It is composed by treemain blocks: the receiver section (with S-band and X-band front-end), the 5 W S-band transmitter and the low power (7dBm) X-band transmitter [1]. The receiver section is based on a digital architecture as will be detailed in the following.The transmitter sections perform the function of transmitting and modulating the down-link signal in order to providethe ground stations with the telemetry signal and the ranging signal demodulated by the receiver. The DST frequencyplan is based on the Sampled Phase Locked Loop (SPLL) approach and on the use of the Direct Digital FrequencySynthesis (DDFS). This architectural solution is very attractive , both in terms of size and output spectral purity, whenhigh multiplication factors are required. Besides the Numerically Controlled Oscillator (NCO), based on the CoordinateRotation Digital Computer (CORDIC) algorithm, allows great design flexibility with wide range tracking capability. Incoherent mode, the down-link frequencies include the up-link Doppler contribution dF evaluated by the

microprocessor and scaled by the relevant turn-around ratio. In non-coherent mode the down-link frequencies are fixed.In general future deep space missions require transponders capable of up-link in X-band and down-link both in X and K band (X/X/K DST). Indeed the selection of X and K bands offer better link performance, in particular when accurateradio science experiment are required [2]. Alenia DST design allows to replace the S-band with the K-band transmitterleaving almost unchanged all the other functions included the digital signal processing.

DIGITAL SIGNAL PROCESSING FUNCTIONS

The receiver analog section performs the signal down-conversion, filtering and amplification in order to provide theproper level to the Analog-to-Digital Converter (ADC) input. An analog wide-band Automatic Gain Control (AGC) isrequired to keep constant the signal-plus-noise power at the ADC input.The carrier loop closure at Intermediate Frequency (IF) allows the application of the coherent sampling: the signal issampled at the fixed intermediate frequency 1F with a clock frequency 14F and the IF-to-baseband conversion iseliminated. The proposed sampling scheme produces alternatively in-phase and quadrature baseband samples, allowingthe receiver digital signal processing section to perform the complex carrier demodulation without the use of amultiplier. With this approach, only one ADC is required and the phase and amplitude imbalances are avoided, beingthe mixing accomplished in the digital domain. The IF digitized samples are passed to the receiver digital sectionimplementing signal tracking and data demodulation functions. The digital receiver section is based on a ReceiverApplication Specific Integrated Circuit (Rx ASIC), which mainly performs the high speed processing tasks, and on aMicroprocessor, which allocates the low rate processing tasks (Fig.2).

Fig. 1 Deep Space Transponder: architectural block diagram

Fig. 2 Digital receiver: functional block diagram

Quadra tu reC h a n n e l

∑

A D C

4 F 1

I n -p h a s eChannel

E v e n / O d dDec imat ion

∑

CostasL o o p

Detector

∑

∑

Sub-Carr ierLoopF i l t e r

Sub-Carr ierNCO

CarrierL o o pFilter

CarrierLock

Detector

Rx NCO Base

2 nd L OGeneration

1 3F 1 + Fd 2 nd I F strip

14F

1 + F

d

D T T L&

Matched Fil ter

Carr ierNCO

F 1

F1

Rx ASIC

Microprocessor

I/D T o R a n g i n g D A C

S-TxS P L L L

S-TxN C O

X - T xSPLL

X - T xN C O

2 4 0F 1 +R s Fd

880 F1 +Rx F d

K s

K x

S - T x N C OBase

X - T x N C O Base

Ran

ging

Cha

nnel

Sub-carrierL o c k

D e t e c t o r

C l o c k

Recovered Da ta

F1

2 /3 F 1 + Fd/ 3

2 /3 F1 + R xF d/ 6

2/3 F 1 + R sF d/ 3

221 F1 + F d

2 nd IF

4 F 1

ASICµ P Memor ies

D A C

PhaseModulator

2 nd L O Generat ion

1 st IF A D C

AGC

S - R xFront- End

X - R xFront- End

749 F1 + F d

1s t L O Generat ion

1s t L O Generat ion

To Decoder

Tel

emet

ry

Tele

com

man

d

RxN C O

S-TxNCO

X-TxN C O

S-Tx Frequency Generat ionPower

Amplifier240 F1 + R sFd

Tele

met

ry

Ran

ging

PhaseModu la to r X-Tx Frequency Generat ionX2

880 F1 + R x Fd

D A C D A C

Tele

met

ry

Ran

ging

D A C

Ranging Video Fil ter

To S-TxPhase Modulator

T o X - T xPhase Modulator

2/3

F 1 + F

d/34 F1

2/3

F 1 + R

sFd/3

2/3

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4 F1

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(USO/In te rna l TCXO)

4 F1 ÷ 2

2 F1

1 3 F1 + Fd

14 F

1 +

Fd

F1

The chosen Hardware/Software partitioning allows a great flexibility in terms of functions, algorithms and designparameters. As an example, the tracking loops constants can be easily optimized during the receiver tuning phase toobtain the best performance. The following sections are devoted to Digital Signal Processing functions andmanagement.

Digital Receiver Algorithms

Signal ModelThe command signal at the ADC input can be expressed as:

( ) ( ) ( )[ ]cscsctFtDtFCts φφπθπ ++⋅⋅+= 2sen2sen2 1 (1)

where C is the total transmitted power, 1F is the carrier frequency (∼9.5702 MHz), cφ is the carrier phase, scF is the

sub-carrier frequency, scφ is the sub-carrier phase, θ is the carrier modulation index and D(t) is the command non-

return-to-zero (NRZ) data.The digital samples s(k) at the ADC output can be derived from (1) setting 14Fkt = being k an integer value, i.e.:

)(2

cos2)(2

sen24

)(1

kQkCkIkCFk

sks cc ⋅

⋅+⋅

⋅=

=

ππ (2)

in which:

( ) ( ) ( ) ( ) ( ) ( )

+⋅⋅⋅−⋅= scscccc F

kFkDJJkI φπφθφθ

110 4

2sensencos (3)

( ) ( ) ( ) ( ) ( ) ( )

+⋅⋅⋅+⋅= scscccc F

kFkDJJkQ φπφθφθ

110 4

2sencossen (4)

are the in-phase and quadrature residual carrier baseband components, derived using the Anger-Jacobi expansion andneglecting the higher order terms being filtered out by the decimator stages.

Carrier DemodulationAs suggested by (2), the in-phase )(kIc and quadrature )(kQc baseband components can be recovered demultiplexing

the sampled signal s(k) into even and odd samples and then multiplying alternatively by +1 and –1.

Carrier Tracking LoopEquation (4) shows that the carrier loop error term cφ can be obtained from the quadrature samples, after digital mixing

with quadrature reference signal. The carrier quadrature samples are accumulated to reduce the sampling rate, thusenabling the software implementation of the loop filter. The digital loop filter includes a perfect integrator, making thecarrier recovery loop capable of tracking a frequency offset without steady state phase error.The filter outputs a frequency error estimate at the loop update rate adjusting the nominal frequency of the NCO thatfeeds the Digital-to-Analog Converter (DAC). The DAC output is mixed with the SPLL output frequency allowing theanalog closure of the carrier loop at IF.The difference between the absolute value of the in-phase and quadrature baseband samples is used to implement thecarrier lock detector.

Sub-Carrier Tracking LoopIn case of perfect carrier tracking 0=cφ and )(kQc becomes proportional to the modulated sub-carrier. Hence, the

sub-carrier tracking loop input is given by the quadrature baseband component of the residual carrier. The sub-carriertracking loop is implemented as a second-order order Costas loop with hard-limited in-phase channel and squarewavereference. This solution has been analyzed in detail in [3]. During the sub-carrier acquisition phase, the Costas loopdetector is configured as a frequency detector thus speeding the frequency acquisition process. Once the sub-carrier

frequency has been acquired, the Costas loop detector is configured as a phase detector in order to perform sub-carriertracking. The in-phase signal of the sub-carrier is proportional to the modulating NRZ sequence.The difference between the absolute value of the in-phase and quadrature sub-carrier samples is used to implement thesub-carrier lock detector.

Symbol SynchronizationThe in-phase signal of the sub-carrier is applied to the Digital Data Transition Tracking Loop (DTTL) performingsymbol synchronization and matched filtering. The base-band input signal is passed through two parallel channels: thein-phase channel monitors the polarity of the actual transitions and the quadrature channel measures the timing erroraccumulating over the estimated symbol transition. The quadrature channel output is delayed by one-half symbol periodand then multiplied by the in-phase channel output. The multiplication results is the loop error signal, that isproportional to the estimate of the timing error. Subsequently, the loop error signal is filtered by the loop filter with theresulting output being used to control the timing generator. The DTTL is implemented as a digital first-order loop and itshows a steady-state error in presence of Doppler or frequency instability. However, at low symbol rates, the DTTLNCO is clocked by the estimated sub-carrier frequency and only the phase must be recovered.

Transponder CoherenceThe DST frequency plan must guarantee the coherent turn-around ratio between the transmitted and the received signalin order to enable two-way ranging. The DST architecture is based on DDFS that intrinsically does not allow thecoherent turn-around function due to frequency control quantization. To avoid a frequency error due to the NCO controlword quantization, the dithering of the base frequency is performed at carrier loop sampling time. Besides, a dedicatedsignal processing is implemented to compensate the deviation of the down-link signal phase from its desired value.

Digital Automatic Gain ControlDigital AGC algorithms are used for digital receiver calibration. The digitized samples are collected from the Rx ASICby the Microprocessor and the loop filter is software implemented. During the signal detection and carrier acquisitionphases a non-coherent AGC is performed, using both the in-phase (3) and quadrature (4) baseband components of theresidual carrier. During carrier tracking, a coherent AGC based on the in-phase baseband component of the residualcarrier is implemented.

Turn-Around RangingThe tone demodulation with base-band conversion is implemented inside the digital section; after mixing with the 1Ffrequency, the samples are processed by an integrate-and-dump filter (I/D) which accumulates the base-band samplesand dumps at an output rate equal to 21F . After digital-to-analog conversion, the samples are routed to ranging videocircuit composed by: high pass filter for DC offset rejection, active low pass filter for rejection of non desired spectralcomponent (spectrum replica and alias), resistive divider to route the signal both at S-band and X-band down-linkmodulator. To simplify the hardware design, the video AGC (usually applied in the video channel) has been removed.However, at low signal-to-noise ratio, the same performance have been obtained by properly tuning the overall rangingchannel, including the down-link modulation index. In Fig.3 the performance of Rosetta ranging channel (RF AGConly) in terms of down-link ranging side-bands power over overall down-link signal power totr PP is compared versus

the classical video AGC approach. The transponder digital architecture allows the application of on-board regenerativeranging. This approach becomes important in case of low signal to noise ratio typical of deep space application. Indeedthe traditional ranging channel routes to the down-link modulator all the up-link noise power reducing the useful side-band ranging components and affecting the ground station performances.

Digital Receiver Management

The Microprocessor manages the digital signal processing operations according to the State Diagram sketched in Fig.4.The following operative scenarios are foreseen:• Low input power level: -146 dBm ≤C <-126 dBm (carrier sweep rate for on-board acquisition = 20 Hz/s)• High input power level : C ≥-126 dBm (carrier sweep rate for on-board acquisition < 500 Hz/s)as consequence the receiver configures itself respectively in Narrow-Band or Wide-Band, in order to optimize thecarrier acquisition and tracking performance. An overview of the receiver software states is provided in the following.

S1: Signal DetectionThe signal detection is based on two center frequency detectors (one for the Narrow-Band and one for the Wide-Band),together with a non-coherent AGC. This architectural solution allows to close the carrier loop bandwidth only when thecarrier is inside the loop pull-in (i.e. the carrier is inside the center frequency detector bandwidth). This approachreduces the probability of false alarm and gives the opportunity to automatically discriminate between the two operativeconditions: low level signal or high level signal. When one of the two center frequency flag is active the relevant CarrierAcquisition state is entered.

S2N/S2W: Carrier Acquisition Narrow/WideIn this state the carrier tracking loop and the lock detection algorithms are performed, along with a coherent AGC.A maximum time is allowed to obtain the carrier lock condition; if this time elapses without carrier lock, the SignalDetection state is reinitialised and the signal detection is started again. After locking the carrier, the processingcontinues with the Sub-carrier Acquisition Narrow/Wide state.

S3N/S3W: Sub-carrier Acquisition Narrow/WideThe sub-carrier tracking loop and lock detection algorithms are performed during this state, together with the carriertracking loop and the carrier lock condition verification. When the sub-carrier is locked, the processing continues withthe Signal Tracking Narrow/Wide state, while if the carrier lock is lost the Carrier Acquisition Narrow/Wide state isentered.

S4N/S4W: Signal Tracking Narrow/WideDuring this state, the carrier and sub-carrier tracking loops and the lock condition verification algorithms are executed;a squelch algorithm is executed to verify the quality of the received signal.

Narrow-Band to Wide-Band and Wide-Band to Narrow-Band TransitionsTransition between the Narrow-Band to Wide-Band configuration and vice-versa are allowed to cope with variation ofsignal power and dynamic during the carrier tracking phase. If the carrier lock is lost, the Carrier AcquisitionNarrow/Wide state is entered; otherwise, if the sub-carrier lock is lost, but the carrier is still locked, the Sub-carrierAcquisition Narrow/Wide state is entered.

TECHNOLOGY

ASIC and FPGA

The design of the Rx ASIC model shall be adequate both for FPGA (Field Programmable Gate Array) and ASICimplementation. The FPGA is aimed to support the development of the transponder breadboard when the signalprocessing algorithms are tested and tuned.

Fig. 3 Rosetta ranging channel performance Fig. 4 Digital receiver: software states

Up-Link Modulation Index: 0.8 rad-pk --- Down-Link Modulation Index: 0.6 rad-pk

-60

-50

-40

-30

-20

-10

0

23 33 43 53 63 73 83 93

C/N0 (dBHz)

AGC VIDEO

AGC RF

Pr/P

tot(d

B)

S1

S2N

S3N

S4N

S2W

S3W

S4W

E1-2

E2-1

E2-3E3-4

E4-3

E1-2 E2-1

E2-3

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E3-1

E4-1

E3-1

E4-1

E3N

-3W

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-4W

E3W

-E3N

E4W

-4N

The FPGA was chosen from the ALTERA FLEX10K devices, which are S/W or EPROM configurable.

Clock Scheme

To obtain the best out of FPGA and ASIC, the project relays on a Clock and Clock Enable scheme: in general a globalclock drives a domain of registers, but the registers are active only when the clock enable is true. This type ofarchitecture in fact requires a multiplexer in front of each flip flop, and this may seem gate consuming and powerinefficient: however this is not the case, since the current FPGA technology relays on the elementary cells made ofregisters with clock enable, multiplexer and combinatory logic. Furthermore, FPGA uses a number of dedicated clocknets that run throughout the device with optimised skew. From the ASIC standpoint, the same architecture requires thegeneration of the Clock Tree, which is the state-of-the-art of the Silicon Manufacturer’s community; the gate overheaddue to the multiplexers did not require a larger die, and power consumption was not affected, since multiplexers switchat very low rates with respect to the clock frequency. The Clock and Clock Enable scheme leaves a clear andstraightforward data path which is very easy to handle when using EDA synthesis and analysis tools. A power savingstrategy was implemented on the Rx ASIC by allowing a number of functions to be turned ON and OFF, according tothe current computing needs. The ON/OFF function inhibits the relevant gates from toggling, without physicallydisconnect them from the supply rails.

Metastability

The Rx ASIC requires a number of independent clocks: the two most critical are the CPU clock which drives theMicroprocessor and the 14F clock that goes with the IF data samples. The clocks are totally independent. Each clockdrives its own registers domain, but since data exchange is required from a domain to another, suitable synchronisingcircuits are provided to prevent large register areas from going into metastable states. The synchronising circuitsprovide adequate interface so that only one flip flop goes into metastability in an interval of two clock periods.

Design Flow

The Rx ASIC was modelled with a VHDL-RTL code. The VHDL-RTL code was simulated and validated to therequirements with a VHDL Test Bench, which is a description of both the input stimuli that drive the model, and how tocatch the outputs of the model for further analysis. Afterwards the VHDL-RTL was synthesized for the FPGA housedin the Rosetta Transponder breadboard. The synthesized model was then simulated and compared to the VHDL-RTLsimulation results, to check for critical timings, and logic synthesis outputs. The above steps produce an accurateVHDL-RTL model description and Test Bench that will also be good for the ASIC development. The whole model orpart of it can be evaluated in advance for synthesis in terms of gate complexity and speed, so that the requiredperformance can be met.

Power Consumption

The power consumption of the designed device is difficult to estimate since it largely depends on the number ofswitching gates, functions settings, bit rates and cut off frequencies of the filters. The worst case estimation is 1.2 W,fully operating, at the maximum frequencies. The power consumption can be reduced performing the coherent samplingprocess at 34 1F instead of 14F , thus exploiting the sub-sampling technique.

REFERENCES

[1] M.C. Comparini, G.Boscagli, L.Simone, “Deep Space Digital Transponder for Rosetta and Mars ExpressMission” – 2nd ESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31October 2001

[2] L.Iess, G.Boscagli , “Advanced Radio Science Instrumentation for the Mission BepiColombo to Mercury" – 2ndESA Workshop on Tracking Telemetry and Command Systems for Space Applications, 29-31 October 2001

[3] L.Simone, S. Cocchi, M. D’Attilia, M.C. Comparini, D. Gelfusa, G.C. Cardarilli, M. Re, A. Del Re, “Analysisand Design of Digital Costas Loop Based on CORDIC Algorithm” – 2nd ESA Workshop on Tracking Telemetryand Command Systems for Space Applications, 29-31 October 2001