CONTENTS

1. STUDY OF LOGIC GATES AND VERIFICATION OF BOOLEAN LAWS

2. DESIGN OF ADDERS AND SUBTRACTORS

3. DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

4. DESIGN OF MULTIPLEXER

5. DESIGN OF DEMULTIPLEXER

6. DESIGN OF ENCODER AND DECODER

7. DESIGN AND IMPLEMENTATION OF 2 BIT AND 8-BIT MAGNITUDE COMPARATOR

8. STUDY OF FLIP FLOPS USING LOGIC GATES

9. DESIGN AND IMPLEMENTATION OF COUNTERS USING FLIP FLOPS

10. DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

• APPENDIX - Clock Generators

STUDY OF LOGIC GATES AND VERIFICATION OF BOOLEAN LAWS

AIM: 1. To study the truth table of Logic gates. 2. To verify Boolean laws

APPARATUS REQUIRED:

S.No. APPARATUS Specification / Range Qty 1 Power supply 0-5 V 1 2 Bread Board 1 3 Resistor 330Ω 1 4 LED 5 5 Quad-2-input NAND 7400 1 6 Quad-2-input NOR 7402 1 7 Quad-2-input AND 7408 1 8 Quad-2-input OR 7432 1 9 Quad-2-input XOR 7486 1 10 Hexa inverter gate 7404 1 11 Connecting wires

THEORY:

Basic gates like AND, OR, NOR, EXOR etc. form the building blocks of complicate ICs.

They are generally available as quadrature ICs. NOR and NAND gates are called the universal gates,

as any other gate can be form may be realized using these.

GATES AND THEIR CHARACTERISTICS

AND: output is high when both the inputs are high OR: output is high if any input is high NOT: output is invert of input NAND: output is high when one or both the inputs are high. NOR: output is high when both inputs are low XOR: output is high when one of the inputs is high XNOR: output is high when both inputs are identical.

PROCEDURE:

1. Test all the ICs using IC tester.

2. Place the IC in the breadboard.

3. Connect Vcc and the ground.

4. Connect the appropriate pins to the input and out LEDs and switches.

5. Give various combinations of the inputs and observe the output and verify the truth table

6. Repeat the above steps for all the ICs.

EX NO: 1 DATE:

B

1

23Y=A.B

SYMBOL

A

TRUTH TABLE

A B OUTPUT Y

0 0 0 0 1 0 1 0 0 1 1 1

SYMBOL

B

A Y=A+B1

23

TRUTH TABLE:

A B OUTPUT Y

0 0 0 0 1 1 1 0 1 1 1 1

B

A

SYMBOL

Y= (A.B) '1

23

TRUTH TABLE

A B OUTPUT Y

0 0 1 0 1 1 1 0 1 1 1 0

A1

2

3

B

Y=A + B

SYMBOL

TRUTH TABLE

A B OUTPUT Y

0 0 0 0 1 1 1 0 1 1 1 0

A

SYMBOL

Y= A1 2

TRUTH TABLE

A OUTPUT Y

0 1 1 0

SYMBOL

2

31Y= A+B

B

A

TRUTH TABLE A B OUTPUT

0 0 0 0 1 0 1 0 0 1 1 0

Verification of Boolean Laws

Boolean algebra is a systematic arrangement of logic which analyses the logic and arithmetic calculation of all digital equipments. Boolean algebra operates with logic expressions containing

• Logic variables • Logic operators • Parenthesis • Equal sign

Commutative Law For AND operation AB=BA For OR operation A+B=B+A This can be proved from the respective truth tables Associative Law For AND operation A (BC) = (AB) C For OR operation A+ (B+C) = (A+B) +C E.g. 1*(1*0) = (1*1)*0 = 0 1+ (1+0) = (1+1) +0 = 1 Distributive Law For AND operation A*(B+C) = AB + AC For OR operation A+ (B*C) = (A+B) *(A+C) E.g. 1*(1+0) = (1*1) + (1*0) = 1 1+ (1*0) = (1+1) * (1+0) = 1 Identity Law For AND operation A+A = A For OR operation A*A = A The AND and OR operation obey Identity Law. If both the inputs are same, output is same. E.g. 1+1 = 1 1*1 = 1

Complement Law _ For AND operation A*A = 0 _ For OR operation A+A = 1 The complement law is obeyed in different ways by AND and OR gates. In case of OR, the output is always 1, and in AND, it is always 0. Operation with 0 & 1 For AND operation A*0 = 0 A*1 = A For OR operation A+0 = A A+1 = 1 AND with ‘0’ yields ‘0’ as output. AND with ‘1’ yields input as output. OR with ‘0’ yields input as output. OR with ‘1’ yields ‘1’ as output. De-Morgan’s Laws The complement of sum of 2 Boolean variables is equal to the product of the individual complements _____ _ _ A + B = A * B The complement of product of 2 Boolean variables is equal to the sum of the individual complements _____ _ _ A * B = A + B Double Complement _ _ A = A Double complement of an input yields the same output. Redundancy Laws

A + AB = A _ A + AB = A + B

A (A+B) = A _ A (A+B) = AB

A+B=B+A

1

23

A

B+A

A+B

B

AB

1

23

TRUTH TABLE

A B A+B B+A 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1

A.B=B.A

1

23

B.A

BA.BA

AB 1

23

TRUTH TABLE

A B AB BA0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1

5V

A+1=1

1A 1

23

TRUTH TABLE

A.1=A

5VA

A1

23

TRUTH TABLE

A A.10 0 1 1

A

1

23

+0=A

AA

TRUTH TABLE

A A+0 0 0 1 1

1

23

A.0=0

A

TRUTH TABLE

A A.00 0 1 0

A A+1 0 1 1 1

A1

23

A+A=A

A

TRUTH TABLE

A A+A0 0 1 1

A

A.A=A

1

23

TRUTH TABLE

A A.A 0 0 1 1

1 211

23A

A + A=1

TRUTH TABLE

A A’ A+A’0 1 1 1 0 1

01

23

1 2

A . A=0

A

TRUTH TABLE

A A’ A.A’0 1 0 1 0 0

RESULT:

DESIGN OF ADDERS AND SUBTRACTORS

AIM: 1. To design and test a half and full adder 2. To design and test a half and full subtractor.

APPARATUS REQUIRED:

S.NO APPARATUS QUANTITY 1. Bread board 1 2. IC’s 7486,7408,7432 2 each 3. Power supply 1 3. Patch Chords

THEORY: HALF ADDER:

Half adders are capable of taking two inputs only. Their outputs are sum and carry. Adders are

circuits which are used to find the sum of the inputs.

FULL ADDER:

These adders are capable of having three inputs and they produce two outputs: sum and carry. Since

three inputs are present, eight input combinations are possible whereas in half adder only four input

combinations are possible.

Half Subtractor:

Subtractors are circuits used to find the difference between the inputs. These have 2 inputs( 4

input combinations possible ) and 2 outputs, Difference and Borrow.

Full Subtractor:

These have 3 inputs ( 8 input combination possible ) and 2 outputs, Difference and Borrow.

Procedure:

1. Test all the ICs using the IC tester. 2. Place the ICs in the slots in breadboard and lock it in place. 3. Connect Vcc and ground. 4. Connect the appropriate inputs to the switches and outputs to the LEDs. 5. Give various combinations of inputs and verify the truth table.

Exp No : 2

HALF ADDER: SYMBOL:

Y

X SUM(S)

CARRY(C)

HALFADDER

TRUTH TABLE:

X Y S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

From the truth table, S = X ⊕ Y C = X • Y CIRCUIT DIAGRAM:

FULL ADDER: SYMBOL:

SUM(S)

B

AFULL ADDER

CARRY(C)C

TRUTH TABLE:

A B Cin S Cout0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

SIMPLIFICATION: Sum S = A⊕ B⊕ C Carry C = AB+BC+CA

HALF SUBTRACTOR: TRUTH TABLE

From truth table: _ B = XY _ _ D = XY + XY = X ⊕ Y

INPUTS OUTPUTS

X Y B D 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0

CIRCUIT DIAGARM:

FULL SUBTRACTOR:

TRUTH TABLE:

_ B = YZ + X (Y+Z) D = X ⊕ Y⊕Z

INPUTS OUTPUTS

X Y Z B D 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

CIRCUIT DIAGRAM:

RESULT:

Ex No:3 DESIGN AND IMPLEMENTATION OF CODE CONVERTERS AIM: To implement

(i) Binary to gray code converter (ii) Gray to binary code converter

Equipments required

S.No Component Range Quantity 1 Bread board - 1 2 EX-OR gate IC7486 2 3 Power supply (0-5)V 1 3 Connecting wires - as required

Theory The gray code is often used in digital systems because it has the advantage that only one bit in the

numerical representation changes between successive numbers. The Boolean expressions for binary to

gray conversion are

G3=D

G2=C (+) D

G1=B (+) C

G0=A (+) B

The binary code is a 2 bit code. It is a weighted code with the digits in each position having a weight

of 2.It is used in computers. The Boolean expressions for gray to binary to gray conversion are

A=(G3 (+) G2) (+) (G1 (+) G0)

B=G3 (+) G2 (+) G1

C=G3 (+) G2

D=G3

Procedure 1.Place the IC's on a bread board.

2.Connect circuit as per logic diagram.

3.Apply input and verify output.

Binary to Gray Code Converter:

Truth Table:

BINARY GRAY D C B A G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0

Circuit Diagram:

Gray to Binary Code Converter:

Truth Table :

GRAY BINARY G3 G2 G1 G0 D C B A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1

Circuit Diagram:

Result:

EX NO: Date: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AIM: To design and implement

i. 4:1 mux ii. 8:1 mux iii. Full adder realization using MUX

APPARATUS REQUIRED:

S.NO APPARATUS QUANTITY 1. Breadboard 1 2. IC’s 7411(3-i/p AND),

7404,7432 2 each

3 IC74153 1 4 Power supply 1 5 Patch Chords As required

THEORY: MULTIPLIXERS: It has 2n inputs and 1 output controlled by n control lines whose status selects which of the 2n inputs will occur as output. It is used as a data selector. DESIGN OF MUX : 2:1 MUX SYMBOL:

1IsoIsY +=−

Truth Table:

S I0 I1 Y 0 0 X 0 0 1 X 1 1 X 0 0 1 x 1 1

2 : 1MUX

SELECTLINE

2 INPUTS OUTPUT

2:1 MUX Circuit Diagram:

4:1 MUX SYMBOL:

S1

D1

S0

4 : 1 MUX

D3

D2Y

D0

TRUTH TABLE:

INPUTS SELECT LINES

OUTPUT

D0 D1 D2 D3 S1 S0 Y 1 0 0 0 0 0 D0S1’S0’ 0 1 0 0 0 1 D1S1’S0 0 0 1 0 1 0 D2S1S0’ 0 0 0 1 1 1 D3 S1 S0

CIRCUIT DIAGRAM:

Procedure 1.Place the IC's on a bread board.

2.Connect circuit as per logic diagram.

3.Apply input and verify output.

PIN Diagram for IC 74153 (Dual MUX) and IC7411 (3 i/p AND):

4:1 MUX Using IC 74153:

__

oG = 0 __

1G = 1 __

oG = 1 __

1G = 0

S0 S1 1Y 0 0 A0 0 1 B0 1 0 C0 1 1 D0

S0 S1 2Y 0 0 A1 0 1 B1 1 0 C1 1 1 D1

8:1 MUX using IC74153: Truth Table:

FULL Adder Using IC74153:

Truth Table:

RESULT:

S2 S1 S0 O/P Y

0 0 0 A0

0 0 1 B0

0 1 0 C0

0 1 1 D0

1 0 0 A1

1 0 1 B1

1 1 0 C1

1 1 1 D1

A B C Carry Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

EX NO: 5 DATE: DESIGN AND IMPLEMENTATION OF DEMULTIPLEXER AIM: To design and implement

i. 4:1 De-mux ii. 8:1 De-mux

using logic gates and ICs APPARATUS REQUIRED:

S.NO APPARATUS QUANTITY 1. Bread board 1 2. IC’s 7411,7404,7432 2 each 3. IC74155 1 4. Power supply 1 5. Patch Chords

THEORY: DEMULTIPLEXER: It performs the reverse action of that of a multiplexer. A single input is demultiplexed by ‘n’ select lines to give 2n outputs. Procedure: 1.Place the IC's on a bread board. 2.Connect circuit as per logic diagram. 3.Apply input and verify output. DEMULTIPLEXER: SYMBOL:

1: 2 DEMUX Circuit Diagram: 1:2 DEMUX TRUTH TABLE

D S Y0 Y1

0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1

INPUT 1 : 2nDEMUX

2n OUTPUTS

n SELECT LINES

1:4 DEMUX SYMBOL: 1:4 DEMUX TRUTH TABLE:

1:4 DEMUX Circuit Diagram:

S0 S1 D Y0 Y1 Y2 Y3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN Diagram of IC74155:

1:4 DEMUX Circuit Diagram using IC74155:

aG

__= 1

bG__

= 0

aG

__= 0

bG__

= 1

1:8 DEMUX Circuit Diagram using IC74155:

Input Output

DbbG

__ S0 S1 Y 4

Y5 Y6 Y7

X 1 X X 1 1 1 1 1 X X X 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 1 1 0

Input Output

Da

aG__ S0 S1 Y0

Y1 Y2 Y3

X 1 X X 1 1 1 1 0 X X X 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0

Truth Table for 1:8 De-mux:

0

__G S2

S1

S0

Y0

Y1 Y2 Y3 Y4

Y5 Y6 Y7

X X X X 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0

RESULT:

EX NO:6 DATE: DESIGN AND IMPLEMENTATION ENCODER AND DECODER Aim:

1. To design 8 to 3encoder and verify their truth table. 2. To design 3 to 8 decoder and verify its truth table.

Equipments Required:

Sl.No. Equipments Required Quantity 01. Bread board 1 02. IC7404,IC 7432,IC7411 3 Each 03. Connecting wires As required 04. Power supply 1

Theory: Encoder:

An encoder in a digital function that produces a reverse operation from that of a decoder. An

encoder has 2n

input lines and n output lines.

Decoder: A decoder is a combinational circuit that converts binary information from n inputs to a maximum of

2n unique output. The name decoder is also used in conjunction with some code converter such as a

BCD to seven segment decoder.

Procedure:

1. In a breadboard, the connections are made as per the circuit diagram

2. +5v is given to 14th pin and 7th pin given the ground.

3. The input values are given and the corresponding output values are verified as per the truth

table.

Circuit Diagram for 8 to 3 Encoder:

TRUTH TABLE FOR 8 to 3 ENCODER

Circuit Diagram for 3 to 8 Decoder:

TRUTH TABLE FOR 3 to 8 DECODER

INPUT OUTPUT X Y Z D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1

RESULT:

EX NO:7 DATE: DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

Aim:

1. To design, construct and verify the truth table of 2-bit magnitude comparator. 2. To construct a 4-Bit and 8-bit magnitude comparator using IC7485.

Equipments Required:

Equipment Range Quantity Breadboard - 1 4-bit Magnitude comparator IC7485 2 Power supply 0-5 V 1 AND gate IC7408 2 OR gate IC7432 1 NOT gate IC7404 1 EX-OR gate IC7486 1 Connecting wires - As needed

Theory:

TWO-BIT MAGNITUDE COMPARATOR.

The two bit magnitude comparator can be constructed using the logic gates

as shown. The inputs are 2 two bit numbers. If the inputs are same the output of (A=B) is HIGH and

all others are low. If any one of the input is greater then the output of that corresponding input will be

HIGH. For example, if A is greater than B then, the output of (A>B) will be HIGH and vice-versa.

Thus a basic circuit which compares the two inputs and generates the output is designed and its truth

tables are verified.

Truth table:

INPUTS OUTPUTS

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0

Circuit diagram for 2-Bit Magnitude Comparator:

4-BIT MAGNITUDE COMPARATOR

The IC7485 is a 4-bit magnitude comparator that can be expanded to almost any length, It

compares two 4-bit binary, BCD or other monotonic codes and presents the three possible magnitude

results at the outputs. There are two expansion schemes available; they are series expansion and

parallel expansion

Pin diagram: 12345678 9

10111213141516

IC7485

VCC

A2

A1

A3

A0

B1

B0

B2

B3

I(A<B)

I(A>B)I(A=B)

A>B

A<BA=B

GND

LOGIC DIAGRAM FOR 4 -BIT MAGNITUDE COMPARATOR:

LOGIC DIAGRAM FOR 8 -BIT MAGNITUDE COMPARATOR:

IC7485

A2 A1A3 A0 B1 B0B2B3

I(A<B)

I(A>B)I(A=B)

A>B

A<BA=B

Input A Input B

IC7485

A2 A1A3 A0 B1 B0B2B3

I(A<B)

I(A>B)I(A=B)

A>B

A<BA=B

Input A Input B+5V

GND

MSB LSBLSBMSB

Output

Procedure:

Place the ICs carefully on the breadboard.

Connect the 16th pin to the supply and 8th pin to the ground.

Switch on and off the corresponding switches of the input variables and check for the output.

Result:

EX NO: 8 DATE: STUDY OF FLIP FLOPS Aim:

To design and study the following flip flops. i) RS flip flop ii) clocked RS flip flop iii) D flip flop iv) JK flip-flop v) T- flip flop.

Apparatus required:

Bread board , IC 7402, IC 7400, IC 7408, IC 7404, IC 7411,power supply, wires. Theory:

A flip flop circuit can maintain a binary state indefinitely until directly by an input signal to switch states. 1) SR latch:

It is called direct coupled RS flip flop and is constructed by using 2 NAND gates. It

has two inputs and two outputs. 2) Clocked RS flip flop: By adding gates to the inputs of the logic circuit, flip flop can be made to inputs levels during occurrence of clock pulses. This flip flop contains NOR and AND gates and it is a three input and two output flip flop. 3) D flip flop: It is an RS flip flop with an inverter on the R output, thus the input is reduced to one. The clock input is often given to variable designation CP or CL to indicate their input enables gated latch to make data entry possible into the flip flop. It is a two input and two output flip flop. 4) JK flip flop: It is a refinement of RS flip flop. The inputs J and K behave like S and R to set and clear the flip flop. It has NOR and AND gate. It is a three input and two output flip flop. 5) T flip flop: It is a single input version of the JK flip flop. It is a two input and two output flip flop. It contains AND and NOR gates.

SR FLIP FLOP: LOGIC DIAGRAM:

i): CIRCUIT DIAGRAM USING NOR GATE:

STATE TABLE:

INPUTS OUTPUTS S R Q Q’

STATE

0 0 0 1 No change 0 1 1 0 Set 1 0 0 1 Reset 1 1 0 0 indeterminate

ii) CLOCKED SR FLIP FLOP: LOGIC DIAGRAM:

CIRCIUT DIAGRAM:

STATE TABLE:

CP S R Q Q’ STATE 0 0 0 0 1 No change 0 0 1 0 1 No change 0 1 0 0 1 No change 0 1 1 0 1 No change 1 0 0 0 1 No change 1 0 1 0 1 Reset 1 1 0 1 0 Set 1 1 1 1/0 1/0 Indeterminate

iii) D flip flop: Logic diagram:

Circuit diagram:

State diagram:

INPUTS OUTPUTS CP D Q Q’ 1 0 0 1 1 1 1 0

iv) JK FLIP FLOP: LOGIC DIAGRAM:

Clk

CIRCIUT DIAGRAM: STATE TABLE:

INPUTS OUTPUT

Q(t) J K Q(t+1) 0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0 1 0 1 1

1 1 0 1 1 1 1 0

v) T FLIP FLOP: LOGIC DIAGRAM:

T Q >C Q’

Clk

CIRCUIT DIAGRAM:

STATE TABLE:

PRESENT STATE

INTPUT OUTPUT

Q T Q(t+1) 0 0 0 0 1 1 1 0 1 1 1 0

RESULTS:

Clk

T

EX NO: 9 DATE:

DESIGN AND IMPLEMENTATION OF COUNTERS USING FLIP FLOPS.

Aim:

1. To Design and implement binary ripple counter using flip flops. 2. To design and implement a synchronous counter using flip flops.

Sl.No. Equipments Required Quantity

01. IC7476,IC7411, IC7404, IC7408 ,IC7432

2

02. Bread board 1 03. Power supply 1 04. Connecting wires As

required Theory: Binary Ripple Counter:

In a ripple counter the flip flop output transition serves as a source for triggering other flip

flops. In other words the clock input of some or all flipflops are triggered not by common clock pulses

but rather by transition that occurs in other flipflops outputs.

Synchronous counter:

In asynchronous counters, the flip flops do not all change state at the same time, but change as a result

of a previous output. The output of one flip flop is the input to the next; the state changes consequently

``ripple through'' the flip flops, requiring a time proportional to the length of the counter. It is possible

to design synchronous counters, using JK flip flops, where all flip flops change state at the same time;

i.e., the clock pulse is presented to each JK flip flop at the same time.

Procedure: i. Connections are made as per circuit diagram on a Bread board.

ii. Connect the supply inputs

iii. The input is applied and output is verified.

State Diagram: 3-bit Counter

Pin Details of JK flip flop: 7476 Dual J-K Flip Flops:

7473 Dual J-K Flip Flops:

1 2 3 4 5 6 7

891011121314

J2

J1 K2

K1

Q2 Q2Q1Q1 GND

Clk ClkClr ClrVcc

IC7473

Result:

EX NO: 10 DATE: DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

Aim: To design different types of shift registers like serial in serial out ,serial in parallel out, parallel in parallel out and parallel in serial out using d flip flop. Apparatus required: IC7408 , IC7432 , IC7474, Bread board. Theory:

A register capable of shifting its binary information either to the right or to the left is called a

shift register .It consists of a chain of flipflops in cascade with output of one flipflop as the input of

the next flipflop .A the flipflops receive a common clock pulse.The common clock pulse causes shift

registers to move from one state to the next.

Procedure:

• Connect the circuit as per the circuit diagram.

• ICs are firmly placed on the bread board of the trainer kit.

• The supply votage and ground connections are properly given.

• Checking is made to see if proper turnsare given as per the truth table.

SERIAL IN SERIAL OUT

SERIAL IN PARALLEL OUT

OBSERVATION TABLE

PARALLEL IN PARALLEL OUT

OBSERVATION TABLE

PARALLEL IN SERIAL OUT

OBSERVATION TABLE

PIN Diagram for IC7474(Dual D-Flip flop)

Result:

Appendix

Clock Generator

IC 555 Timer Pin connections

The 555 timer is an extremely versatile integrated circuit which can be used to build lots of different circuits.

. Astable circuits

Astable circuits produce pulses. The circuit most people use to make a 555 astable looks like this:

As you can see, the frequency, or repetition rate, of the output pulses is determined by the values of two resistors, R1 and R2 and by the timing capacitor, C.

The design formula for the frequency of the pulses is:

The HIGH and LOW times of each pulse can be calculated from:

The duty cycle of the waveform, usually expressed as a percentage, is given by: