Digital Integrated Circuits (83-313) Integrated Circuits (83-313) Semester B, 2015-16 ......
Transcript of Digital Integrated Circuits (83-313) Integrated Circuits (83-313) Semester B, 2015-16 ......
DigitalIntegratedCircuits
(83-313)
SemesterB,2015-16
Lecturer:AdamTeman
TAs:Itamar Levi,RobertGiterman1
Lecture 1:
Introduction
WhatwillwedointhisCourse?
2
InDigitalElectronicCircuits,welearnedthebasicsof
buildingadigitalgateandgottoknowanumberof
methodsindigitalcircuitdesign.
Inthiscoursewewillstepupalevel,including:
Connectingthetheoretical(schematic)implementationofthe
circuittoitsphysical(layout)implementation.
Learnaboutparasitics thatareinherenttointegratedcircuit
design.
Considerthetrade-offsinusingdifferentarchitecturesand
designalternatives.
Learnhowto“put-it-all-together”towardscompilingaVLSI
chip.
WhatwillwedointhisCourse?
3
ThiscoursedealswiththeCircuitLevel andGateLevel
designofdigitalcomponents.
Togetabetter“hands-on”understanding,wewilluse
CadenceVirtuoso to:
Compileourcircuits.
Simulatecircuitoperation.
Understandphysicalimplementationandprocessvariations.
Uponcompletionofthiscourse,youwillhaveagood
understandingofwhat’shappening“underneaththe
HDL”.
There’sNoFreeLunch!
Understanding,designingand
optimizingthetrade-offs
between:
Performance
Power
Cost
Reliability
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Whatwillwelearntoday?
5
Course
LogisticsDesign
Abstraction
andStyles
Howachipis
born
Costofan
Integrated
Circuit
6
Course Administration
• Lecturer: Dr. Adam Teman
Lecture: Monday 09:00-12:00. Class 249
One break in the middle!
Office Hrs: Monday 14:00-15:00. Office 413
• Teaching Assistants:
Itamar Levi [email protected]
Office Hrs: Wednesday 1630-1730
Robert Giterman [email protected]
Office Hrs: Wednesday 1200-1300
Labs: TBD
• Course Web Page: Moodle
Grading
9
§ Quizzes:
§ Intro Quiz: 8%
§ 3 Quizzes: 45%
§ 6 Homeworks: 42%
§ Participation and Evaluation: 5%
Labs
10
Labsare2hourslong.
Labsaredoneingroupsoftwo.
Eachgrouphasalabeveryotherweek.
SignupforLab1TODAY!
Itamar andRobertwillpassaroundasignupsheet.
Exactgroupingscanbesetinthelab,butsincetheystartonWednesday,
youwillneedtosignuptoday.
DuringthefirstlabitismandatorytosignanNDA.
LabSchedule
11
Week Homework Lab
1-2 SPICE WritingaSPICEnetlist.
ControllingSPICEwithascript.
3-4 MOSFETS BasicMOSFET Parameters
5-6 AutomaticLayout
inVirtuoso
CustomFloorplanning,Placementand
RoutinginVirtuoso
7-8 Advanced
MOSFETS
AdvancedDeviceParameters
9-10 Verilog/Verilog-A MixedSignal Simulation
11-12 SystemDesign Designing asmallmemory
ReadingMaterial
12
MainBook:
Rabaey, et al., “Digital Integrated Circuits: A Design Perspective”, 2nd Edition, 2003.Highly recommended: UC Berkeley EE141 – lectures online (most recent from 2012)
Butmostlectureswillhaveareadinglist.
Inordertogetabetterunderstanding,itishighly
advisedtousethesereferences!
CourseSyllabus
13
Lecture 1: Introduction Lecture 2: Process and LayoutLecture 3: The NanoScaled MOSFETLecture 4: ScalingLecture 5: InterconnectLecture 6: MemoriesLecture 7: Sequential LogicLecture 8: ArithmeticLecture 9: Back to the Future
IntroQuiz:14/3
Quiz1:11/4
Quiz2:30/5
Quiz3:20/6
NoLectureson:18/4(Pesach),25/4(Pesach),23/5(ISCAS),13/5(Shavuot)
2
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Whatwillwelearntoday?
14
Design
Abstraction
andStyles
Course
Logistics
Howachipis
born
Costofan
Integrated
Circuit
Example:dynOR
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cpu_dca
control
cgu
cgu_mux
DynOR-light arch. v2.1
same high voltage for all modules, except for the cpus
in cpu_dca and cpu_ref,which have a separate low
voltage and level shifters
cpu
tms_err dca_ctrl
mem_data
SPREG 1024x32
membus membus
clockbox
mor1kx
mif_muxclk_ext_i
mem_instr
SPREG 1024x32
cpu_refcpu
mem_data
SPREG 1024x32
membus membus
clockbox
mor1kx
mem_instr
SPREG 1024x32
debug_mon
mem_edram
conf_ctrl
reg. filereset_sync
...
rst_n_ext_i
moduleresets
serialif
master
...
clk_cgu
sdat_i
eflags, notifiers, ...
sdat_o
clockbox cdca:
ext
cgu
CG
CG
CG
cpu
mem
dca
clockbox cref:
ext
cgu
CG
CG
cpu
mem
scan chain 0
scan chain 1
gp_i[1:0]
gp_o[21:0]
io_mux_ctrl
io_mux_i
tms_rst_gen
cpu_input_sync
debug signals:divided clock,eflags, notifiers,cgu periods,im addr.,edram if
cpu_input_sync sregsreg
Digitalvs.Analog
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q DigitaldesignenablesAbstraction!
q Abstractionisonlyavailablewhenthereisseparation
(i.e.nofeedback)betweenblocks.
q In otherwords– noisesuppression.
q Thisisverydifficult withAnalogdesign.
q Inaddition,DigitaldesignisScalable,whereasthe
parasiticeffectsintroducedbyscalingcauselimitations
toanalogscaling.
DeviceLevelAbstraction
21
FabricationPlantsorFoundriessupplya
ProcessDesignKit (PDK).
ThePDKincludes:
Devices(Transistors,Resistors,Capacitors,Diodes)
Layers
Rules
Various“Flavors”ofPDKsareavailable,e.g.:
GeneralPurpose/HighSpeed/LowPower
RF/ImageSensor
Flash/DRAM
VariousnumberofMetalInterconnectLayers Device Level
CircuitLevelAbstraction
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UsingthedevicessuppliedinthePDK,Schematics aredrawn.
Simulators,suchasSPICE,areusedtotestandoptimizethe
circuits.
Variousparameters(calledCDFparameters)canbemodifiedto
optimizetheschematic,e.g.:
LengthandWidthoftransistors.
NumberofFingers.
CapacitancesandResistances.
CircuitsaredrawnwithaLayoutEditor and
parasitics areextractedforaccuratesimulation.
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Device Level
CircuitLevel
GateLevelAbstraction
23
Drawncircuitsareabstractedintoa
blackboxforuseasgates.
Thesegatesaredefinedbyeasyto
usecharacteristics,suchas:
BooleanFunctionality.
Interface(i.e.pins orports).
Delayandpowerconsumption.
Inputandoutputcapacitance.
Sizeandgeometry.
Onceagateisabstracted,itcanbe
usedbyhigherleveltools,suchasHDLs.
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Device Level
CircuitLevel
GateLevel
ModuleLevelAbstraction
24
Gatesandotherlowlevelcircuitsareconnected
togetherintomodules(adders,memories,etc.).
Thesearetestedforfunctionalityandareabstracted
forsystemintegration.
Analogmodulesareabstractedfromcircuitlevel.
Digitalmodulesandfullsystemsarecomprisedwith
HDLs,instantiatinggatesandmodules.
EDAtoolsareusedtoverifyfunctionalityatalldepths
ofhierarchy.
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Device Level
CircuitLevel
GateLevel
ModuleLevel
SystemLevelAbstraction
25
Architecturaldesigndefineshighlevelabstractionsto
buildasystem.
Thisabstractionleveldefines:
Registers
InstructionSets
ControlBlocks
Buses
etc.
SystemsareimplementedwithHDLsand
functionalityisverifiedwithlogicalverification.
Systemaredefinedtocomplywithstandards
andimplementprotocols. Device Level
CircuitLevel
GateLevel
ModuleLevel
SystemLevel
HigherLevelAbstraction
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Programmerswritecodeinahighlevel
programminglanguage (C,Java,Perl,etc.)
ACompiler translatesthecodeintoanAssembly
language.
Compilerstrytooptimizetheinstructionsaccordingtothe
actualarchitecturetheyarecompilingto.
AnAssembler translatestheAssemblyinto
MachineLanguage (i.e.0’sand1’s).
Device Level
CircuitLevel
GateLevel
ModuleLevel
SystemLevel
VLSIDesignStyles
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Duetotimeandcostconstraints,veryfewteamsand/or
companiesdevelopproductsfromdevicelevelthrough
tosystemlevel.
VariousDesignStyles areavailabletoshortenthetime-
to-market anddevelopmentcost.
Trade-offs aretakenintoconsideration,asabstractions
areusuallydesignedgenerically andthereforecome
withsomeoverhead.
VLSIDesignStyles– FullCustom
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FullCustomDesign
Theoriginaldesignstyle.
Everythingisdoneat
transistorlevel
Rarelyusedindigitaldesign
Highcost
But,givessignificantgainin
performance.
Analogdesignsmostly
INTEL4004 www.arstechnica.com
VLSIDesignStyles– StandardCells
Standard-cellsbaseddesign
(ASIC- ApplicationSpecificIntegratedCircuit)
HDLsaremappedtoLibraries
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VLSIDesignStyles– GateArray
GateArrayDesignorStructuredASIC
Designimplementationisdonewithmetalmaskdesignand
processing
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VLSIDesignStyles- FPGA
FPGA– FieldProgrammableGateArray
arrayofconfigurablelogicblocks,
andprogrammableinterconnectstructures
Fastprototyping,costeffectiveforlowvolumeproduction
HDL(hardwaredescriptionlanguage)– isused
35http://lsiwww.epfl.ch/LSI2001/teaching/webcourse
DesignStyles– ProsandCons
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FullCustomDesign:
Customizationforoptimizedpower,performance,area.
Highcomplexity=cost,time-to-market,highrisk.
StandardCell:
Simple,fast,reliable.
OnlyDigitaldesigns.Excesspower,wirelength,etc.
GateArray:
Reducednumberofmasksà Inexpensive.
Highpercentageofoverhead,limitedspeed.
FPGA:
Postsiliconconfigurability,veryinexpensive.
Highpercentageofoverhead.Highcostperchip.
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Whatwillwelearntoday?
37
Howachipis
bornCourse
Logistics
Design
Abstraction
andStyles
Costofan
Integrated
Circuit
Howachipisborn…
38
A&Aand Specification
LogicDesign&
IPIntegration
LogicVerification
Physical Design
Sign-off&
TapeOut
PhysicalDesignFlow
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StandardCells
HardIPs
HDLCodeSynthesizer
PlaceandRoute
StaticTiming
Analysis
Floorplan
Tapeout
DRC,LVS,LEC,
Gatelevel sim
ALittleBitAboutCAD
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Process DesignKit(PDK)
Device Library
TechFile
Schematic
Composer
AnalogDesign
Environment
LayoutDesigner
SPICESimulator
FastSPICE Simulator
AMSSimulator
ModelFile
StatisticalDistribution
AnalogLib
DesignRules
Parasitics
Waveform
Hierarchy Editor
DRC
LVS
RCX
SchematicComposer
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Graphicaltoolfordrawingelectrical
circuits.
Usesanabstractrepresentationfor:
Devices
Sources
Wires
Allwiresareidealà R=C=0
Directlytranslatesintoanetlist:
SPICEnetlist
Spectrenetlist
V1 1 0 dc 24V2 3 0 dc 15R1 1 2 10kR2 2 3 8.1kR3 2 0 4.7k.end
AnalogDesignEnvironment
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Graphicaltoolforcreatingtestbenches (ADE,ADE-XL).
Create“tests”thatrunsimulationsona“top-level”netlist.
Maintypesoftests:
DCOperatingPoint
DCSweep
TransientAnalysis
ACAnalysis
Define“outputs”tobeprintedorplotted.
Define“variables”toenableparametricsweeps.
Directlytranslatesintoaspicenetlist orscript(“Oceanscript”)
thatrunsthesimulationsanddisplaystheoutputs.
.dc V1 0 24 24
.print dc v(1) v(2,3)
.tran .05 1
.print tran v(1,2)
AnalogDesignEnvironment
44
Severalsimulatorscanbeusedinyoursimulation:
SPICE(Spectre)
FastSpice (UltraSim)
APS
AMS
Variousmodelscanbeusedtodescribedevices.
Cornersimulationchangesmodelstosimulateglobalprocess
variations.
MonteCarlosimulationsusestatisticaldistributionstosimulation
localprocessvariations.
Layout– ConnectivitytoSchematics
45
Afterreachingoptimalcircuittopology,thelayouteditoris
enactedtoproduceaphysicalrepresentationofthecircuit.
Theprocess“techfile”describesthevariousdesignlayersand
designrules.
Inordertoassistthelayoutdesignerincircuitcompilation,Layout-
XLusesconnectivitybetweenthelayoutandschematic:
GenerateFromSourcecreates“p-cells”oftheschematicdevices.
Netnamesconnectbetweentheschematicandlayout.
Fly-linesandWiresautomaticallyconnectnodesonthesamenet.
Pinlayersareusedtodescribeschematicports/pins.
LayoutVerification– DRC/LVS/RCX
46
DesignRuleCheck(DRC)ensuresthatthelayoutmeets
thedesignrulerequirements.
LayoutVsSchematics(LVS)ensuresthatthelayout
trulyrepresentsthecircuit.
ParasiticExtraction(RCXorPEX)extractstheparasitic
resistance,capacitanceandinductanceofthelayout.
Themostcommontoolsforperforminglayout
verificationare:
CadenceAssura/PVS
MentorGraphicsCalibre
DRC
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DRCcanbeappliedinteractivelyin
Layout-XLbyturningon“DRD”
TheDRCcheckertestscomplex
geometricpatternsforeachlayeras
describedinthePDK’srulefile.
DRCwarningsinclude:
Circuitlevelrules
Chiplevelrules
RecommendedRules(ForDFM)
LVS
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LVSusesagreedyalgorithmtocompare
netlists.
The“Source”netlist istheschematic
(alreadyinnetlist format).
The“Target”netlist isthelayoutas
compiledbyanextractorthatfindsdevices
andconnectsthem.
ThestartingpointfortheLVScheckeristhe
interface(pins/ports).Iftheseare
incorrect,youwillget“strange”errors.
LVSalsochecksvariousdesign
requirementssuchasbulkconnections.
RCX
49
RCXisaparasiticextractorthatcreatesanetlist that
includesthenon-idealitiesofthelayout.
Actualdevicesizes,suchasLdiff.
ResistanceandCapacitanceofwires.
CouplingCapacitance
InordertorunRCX,youmustFIRSTrunLVS.
TheoutputofRCXisalistofnetparasitics anda
netlist thatcanbepluggedbackintothecircuit
simulatorforcomparisontoprelayoutresults.
The“new”CadenceextractoriscalledQRC.
PostLayoutSimulation
50
Pre-layoutsimulationisdoneaccordingtogeneric
modelswithaveragedeviceparametersandidealwires.
Aftercreatingalayoutofyourdesign,itisessentialto
re-simulateyourdesignwiththeactualparasitics – for
betterorforworse.
Yourcircuitwillnowhaveanew“view”inadditiontoits
“schematic”view.Thisviewiscalled“extraction”or
“calibre”orsomethingsimilar.
Thecommonwaytotellthesimulatortousethisviewis
byinvokingtheHierarchyEditor.
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Whatwillwelearntoday?
52
Costofan
Integrated
Circuit
Course
Logistics
Design
Abstraction
andStyles
Howachipis
born
NoFreeLunch
53
InVLSIDesign,wealwayshaveatrade-offbetween:
Foreverycircuit/system,wewillhavetoevaluatethe
specandchoosethemostbeneficialtrade-off.
InDigitalElectronicCircuits,wediscussedthebasic
metricsformeasuringSpeed,Power,andReliability.
Now,wewilldiscussCost.
Speed CostReliabilityPower
CostofIntegratedCircuits
54
NRE(non-recurrent
engineering)costs
designtimeandeffort,
maskgeneration
one-timecostfactor
Recurrentcosts
siliconprocessing,packaging,test
proportionaltovolume
proportionaltochiparea
MaskCosts
TotalCost
55
qCostperIC
qVariablecost
fixed costcost per IC = variable cost per IC +
volume⎛ ⎞⎜ ⎟⎝ ⎠
die cost + package cost+ test costvariable cost =
final test yield
No. of good chips100%
Total number of chipsYield = ×
DieCost
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Singledie
Wafer
From http://www.amd.com
cost of wafercost of die =
dies per wafer die yield×
fixed costcost per IC = variable cost per IC +
volume⎛ ⎞⎜ ⎟⎝ ⎠
die cost + package cost+ test costvariable cost =
final test yield
EdgeLosses
57
( )2wafer diameter/2 wafer diameterDies per waferdie area 2 die area
π π× ×= −
×
fixed costcost per IC = variable cost per IC +
volume⎛ ⎞⎜ ⎟⎝ ⎠
die cost + package cost+ test costvariable cost =
final test yieldcost of wafer
cost of die = dies per wafer die yield×
Defects
60
4die cost (die area) die areaf= ∝
Yield=¼=0.25 Yield=19/24=0.79
fixed costcost per IC = variable cost per IC +
volume⎛ ⎞⎜ ⎟⎝ ⎠
die cost + package cost+ test costvariable cost =
final test yieldcost of wafer
cost of die = dies per wafer die yield×
TotalCost- summary
61
fixed costcost per IC = variable cost per IC +
volume⎛ ⎞⎜ ⎟⎝ ⎠
die cost + test cost + package costvariable cost =
final test yield
cost of waferdie cost =
dies per wafer die yield×
%Yield good chips=
Beforepackaging
Afterpackaging
( )2wafer diameter/2 wafer diameterDies per waferdie area 2 die area
π π× ×= −
×
4die cost die area∝
SomeExamples(1994)
62
Chip Metal layers
Line width
Wafer cost
Def./ cm2
Area mm2
Dies/wafer
Yield Die cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 601
4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
ImportantConceptsFromThisLecture
63
q Abstraction
q Scaling
q Flavors
q Foundry
q Interconnect
q Schematics
q Simulator
q Layout
q Parasitics
q Extraction
q Interface
q Instantiate
q Hierarchy
q Verification
q Standards&Protocols
q DesignStyles
q Trade-offs
q FullCustomDesign
q StandardCellDesign
q Libraries
ImportantConceptsFromThisLecture
64
q GateArray
q SignOff
q Tapeout
q Synthesis
q Floorplan
q PlaceandRoute
q StaticTiming
q PostLayoutSimulation
q Corners
q MonteCarlo
q OceanScript
q Virtuoso
q Calibre
q Assura
q SPICE
q Netlist
q Testbench
q DCOperatingPoint
q TransientAnalysis
q DCSweep
q ACSweep
q ProcessVariations
ThreeLetterWords
65
q PDK– ProcessDesignKit
q HDL– HardwareDescriptionLanguage
q EDA– ElectronicDesignAutomation
q ASIC– ApplicationSpecificIntegratedCircuit
q FPGA– FieldProgrammableGateArray
q IP– IntellectualProperty
q DRC– DesignRuleCheck
q LVS– LayoutVs.Schematics
q RCX– Resistance/Capacitance
Extraction
q ADE– AnalogDesign
Environment