Digital final

Flip-flops,Shift registers, Counters

H.ABIRAMIAsst. Prof(S.G) / ICE,

SETHU INSTITUTE OF TECHNOLOGY,KARIAPATTI

1

DIGITAL INTEGRATED CIRCUITS

SMALL SCALE INTEGRATION

LESS THAN 12 GATES

MEDIUM SCALE INTEGRATION

12 TO 99 GATES

LARGE SCALE INTEGRATION

100 TO 9999 GATES

GATES FLIP FLOPSENCODERS

DECODERS

SHIFT

REGISTERS

MULTIPLEXERS

DEMULTIPLEXERSADDERS MEMORY

SMALL

MICROPROCESSORS

FLIP-FLOPS,SHIFT REGISTERS,COUNTERS 2

LOGIC GATES A logic gate is an elementary building block of a digital circuit.

Most logic gates have two inputs and one output terminals.

At any given moment, each terminal is in one of the two binaryconditions low (0) or high (1), represented by different voltagelevels

Logic gates are at the heart of digital electronics

Video recorders, security lamps, alarm systems, and washingmachines are just some of the things controlled by electronicswitches called logic gates


Logic circuits are classified into two groups:

Combinational logic circuits

Sequential logic circuits

Basic building

blocks include:

Basic building blocks

include FLIP-FLOPS:

LOGIC CIRCUITS

Logic gates make decisions

Flip Flops have memory


Combinational Circuits

Addition: Half Adder (HA)

Full Adder (FA)

Subtraction: Half Subtractor (HS)

Full Subtractor (FS)

Multiplexer

Demultiplexer



Multiplexer / Demultiplexer• The basic function of the Multiplexer (MUX).

• The typical application of a MUX.

• A 4-to-1 MUX designed with Small Scale Integration (SSI).

• A 4-to-1, 8-to-1, & 16-to-1 Medium Scale Integration (MSI)

MUX.

• The basic function of the Demultiplexer (DEMUX).

• The typical application of a DEMUX.

• A 1-to-4 DEMUX design with Small Scale Integration (SSI).

• A 1-to-4, 1-to-8, & 1-to-16 Medium Scale Integration (MSI)

DEMUX.

• A 7-segment message display using MUX/DEMUX.


What is a Multiplexer (MUX)? A MUX is a digital switch that

has multiple inputs (sources)and a single output(destination).

The select lines determine whichinput is connected to the output.

MUX Types 2-to-1 (1 select line)

4-to-1 (2 select lines)



Multiplexer Block Diagram

Select

Lines

Inputs(sources)

Output(destination)

12N

N

MU

X


Typical Application of a MUX

MP3 Player

Docking Station

Laptop

Sound Card

Digital

Satellite

Digital

Cable TV

Surround Sound System

MU

X

D0

D1

D2

D3

Y

B A Selected Source

0 0 MP3

0 1 Laptop

1 0 Satellite

1 1 Cable TV

Multiple Sources Single DestinationSelector


4-to-1 Multiplexer (MUX)

B A Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

MU

X

D0

D1

D2

D3

Y

B A


What is a Demultiplexer (DEMUX)? A DEMUX is a digital switch

with a single input (source) and a multiple outputs (destinations).

The select lines determine which output the input is connected to.

DEMUX Types 1-to-2 (1 select line)




Demultiplexer Block Diagram

Select

Lines

Input(source)

Outputs(destinations)

2N1

N

DE

MU

X


Typical Application of a DEMUXSingle Source Multiple DestinationsSelector

D0

D1

D2

D3

X

DE

MU

X

B A Selected Destination

0 0 B/W Laser Printer

0 1 Fax Machine

1 0 Color Inkjet Printer

1 1 Pen Plotter

B/W Laser

Printer

Color Inkjet

Printer

Pen

Plotter

Fax

Machine


1-to-4 Demultiplexer (DEMUX)

B A D0 D1 D2 D3

0 0 X 0 0 0

0 1 0 X 0 0

1 0 0 0 X 0

1 1 0 0 0 X

D0

D1

D2

D3

X

B A

DE

MU

X

The Sequential Circuit Model


x1 z

1

xn z

m

(a)

y1

Yr

yr

Y1

Memory

Combinationallogic

Combinational

logic

(b)

x1

z1

xn

zm

FLIP-FLOPS

S

R

Q

Q

•Memory device capable of storing one bit

•Memory means circuit remains in one state after

condition that caused the state is removed.

•Two outputs designated Q and Q-Not that are

always opposite or complimentary.

•When referring to the state of a flip flop, referring

to the state of the Q output.


CLOCKED R-S FLIP-FLOP

Set

Reset

S

R

Q

Q

FF

ASYNCHRONOUS

Outputs of logic circuit can

change state anytime one or

more input changes

Set

Reset

S

R

Q

Q

FF

ClockCLK

SYNCHRONOUS

Clock signal determines exact

time at which any output can

change state


TRIGGERING OF FLIP-FLOPS

• Level-triggering is the transfer of data from input to output of

a flip-flop anytime the clock pulse is proper voltage level.

• Edge-triggering is the transfer of data from input to output

of a flip-flop on the rising edge (L-to-H) or falling edge (H-

to-L) of the clock pulse. Edge triggering may be either

positive-edge (L-to-H) or negative-edge (H-to-L).

Level triggering

Positive-edge triggering

Negative-edge triggering

H

L

time

NGT-Negative Going TransitionPGT-Positive Going Transition



Edge-triggering

In a positive edge-triggered D Flip-

Flop, the output looks at the input only

during the instant that the clock

changes from low to high.

Clock

Q

D

D Q

clk

Edge-triggered D Flip-flop: Every rising edge, output is set to the input

The “carrot”symbol meansedge-triggered


Negative Edge-triggeringIn a negative edge-triggered D Flip-Flop, the

output looks at the input only on the falling

edge of the clock.

D

D Q

clk

Q

Clock

Negative Edge-triggered D Flip-flop: Every falling edge, output is set to the input

S-R Flipflop

“Q” only changes when CLK is high (i.e. level-sensitive)

When CLK is high, behavior same as RS latch


S

R

Q

Q

CLK

1 0 0

1 0 1

1 1 0

1 1 1

CLK S R

No change

0

1

Undefined

Q

0 X X No change

D-Flipflop

Make level-sensitive D-latch from level-sensitive RS-latch by connecting

S = D and R = not D


JK Flip-flop


T Flip-flop


Master-Slave Edge-Triggered Flip-Flop Can connect two level-sensitive latches in Master-Slave configuration to

form edge-triggered flip-flop

Master latch “catches” value of “D” at “QM” when CLK is low

Slave latch causes “Q” to change only at rising edge of CLK

FLIP-FLOPS,SHIFT REGISTERS,COUNTERS23

CLK

D Q

D

QM

CLK

MasterLatch

SlaveLatch

QM

2 x 8 = 16 Transistors

Q

CLK

JK Master Slave Flip-flop


1. Logic gates make decisions, flip flops have ____________________?

2. One flip flop can store how many bits?

3. What are the two outputs of a flip flop?

4. When referring to the state of a flip flop, we’re referring to the state

of which output?

5. What does it mean to SET a flip flop?

6. What does it mean to RESET a flip flop?

TEST

Memory

1

Q Q-NOT

Q

Q = 1

Q = 0


TEST

1. Type of flip flop where the outputs of circuit can change state anytime

one or more input changes? ASYNCHRONOUS

2. Type of flip flop where the clock signal controls when any output can

change state? SYNCHRONOUS

3. What do we call a digital signal in the form of a repetitive pulse or square wave?

CLOCK

4. Which is easier to design and troubleshoot, clocked or not clocked flip flops?

Clocked flip flops are easier to troubleshoot because we can stop the

clock and examine one set of input and output conditions.


COUNTERS


Overview

° Counters are important components in computers

• The increment or decrement by one in response to input

° Two main types of counters

• Ripple (asynchronous) counters

• Synchronous counters

° Ripple counters

• Flip flop output serves as a source for triggering other flip flops

° Synchronous counters

• All flip flops triggered by a clock signal

° Synchronous counters are more widely used in

industry.

Applications:

• Watches

• Clocks

• Alarms

• Web browser refresh

Asynchronous Binary counter


Truth Table


Decade Counter


Decade Counter Truth Table


Clock diagram -Decade


Ring CountersA ring counter is basically a circulating shift register in which the output of

the most significant stage is fed back to the input of the least significant

stage. The following is a 4-bit ring counter constructed from D flip-flops. The

output of each stage is shifted into the next stage on the positive edge of a

clock pulse. If the CLEAR signal is high, all the flip-flops except the first one

FF0 are reset to 0. FF0 is preset to 1 instead.


Ring Counters Truth Table


Johnson Counter


Asynchronous Up-Down Counters


Synchronous(parallel) counters

• All of the FFs are triggered simultaneously by the clock input

pulses.

• All FFs change at same time

° Remember

• If J=K=0, flop maintains value

• If J=K=1, flop toggles

° Most counters are synchronous in computer systems.

° Can also be made from D flops

° Value increments on positive edge

Synchronous Counter


Synchronous Counter


SHIFT REGISTER

Introduction :

Shift registers are a type of sequential logic circuit, mainly for storage of

digital data. They are a group of flip-flops connected in a chain so that

the output from one flip-flop becomes the input of the next flip-flop.

Serial In - Serial Out, Serial In - Parallel Out, Parallel In - Serial Out,

Parallel In - Parallel Out, and bidirectional shift registers. A special

form of counter - the shift register counter, is also introduced.


OVERVIEW OFSHIFT REGISTERS


A shift register is a sequential logic device made up of

flip-flops that allows parallel or serial loading and

serial or parallel outputs as well as shifting bit by bit.

Common tasks of shift registers:•Serial/parallel data conversion

• UART (an example)

• Time delay

• Ring counter

• Twisted-ring counter or Johnson counter

• Memory device

CHARACTERISTICS OF SHIFT REGISTERS


Number of bits (4-bit, 8-bit, etc.)

Loading

Serial

Parallel (asynchronous or synchronous)

Common modes of operation

Parallel load

Shift right-serial load

Shift left-serial load

Hold

Clear

Recirculating or non-recirculating

SERIAL / PARALLEL DATA CONVERSION


1 0 1 0 1 1 1 1Serial in Serial out

Shift registers can be used to convert from serial-

to-parallel or the reverse from parallel-to-serial.

1 0 1 0 1 1 1 1Serial in

Parallel out

1 0 1 0 1 1 1 1 Serial out

Parallel in

1 0 1 0 1 1 1 1

Parallel in

Parallel out

A basic four-bit shift register can be constructed using four D flip-flops, as shown

below. The operation of the circuit is as follows. The register is first cleared,

forcing all four outputs to zero. The input data is then applied sequentially to the

D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is

transmitted from left to right. Assume a data word to be 1001. The least

significant bit of the data has to be shifted through the register from FF0 to FF3.


Serial In - Serial Out

(SISO)

Shift Registers

The data is loaded to the register when the control line is HIGH

(ieWRITE). The data can be shifted out of the register when the

control line is LOW (ie READ).


Serial In - Serial Out

(SISO)

Shift Registers

For this kind of register, data bits are entered serially in the same manner asdiscussed in the last section. The difference is the way in which the data bitsare taken out of the register. Once the data are stored, each bit appears on itsrespective output line, and all bits are availablesimultaneously. A construction of a four-bit serial in - parallel out register isshown below.


Serial In - Parallel Out

(SIPO) Shift Registers

SERIAL LOAD SHIFT REGISTER

FLIP-FLOPS,SHIFT

REGISTERS,COUNTERS 46

Note the use of D FFs.Clock (CLK) inputs wired in parallel.

Clear (CLR) inputs can be activated with LOWor disabled with HIGH.

Preset (PS) inputs deactivated.

Parallel outputs here.Order= A B C D

Inputs here:(1) Data(2) Clock(3) Clear

Clear input:Active = 0

Deactivated = 1

Clock input:Positive-edge

triggering

Clock Pulse 1

Clear = 0

Data = 1

0 0 0 01 0 0 0

Clock Pulse 2

Clear = 1

Data = 1

1 1 0 00 1 1 0

Clock Pulse 3

Clear = 1

Data = 1

Clock Pulse 4

Clear = 1

Data = 0

0 0 1 1

Clock Pulse 5

Clear = 1

Data = 0

0 0 0 1

Clock Pulse 6

Clear = 1

Data = 0

Clock Pulse 7

Clear = 1

Data = 1

1 0 0 00 1 0 0

Clock Pulse 8

Clear = 1

Data = 04-bit

serial-inparallel outshift right

shift register

A four-bit parallel in - serial out shift register is shownbelow. The circuit uses D flip-flops and NAND gates forentering data (ie writing) to the register.


Parallel In - Serial Out

(PISO) Shift Registers

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit

and D3 is the least significant bit. To write data in, the mode control line is

taken to LOW and the data is clocked in. The data can be shifted when the

mode control line is HIGH as SHIFT is active high. The register performs

right shift operation on the application of a clock pulse, as shown in the

animation below.


Parallel In - Serial Out

Shift Registers

For parallel in - parallel out shift registers, all data bits appear on

the parallel outputs immediately following the simultaneous entry

of the data bits. The following circuit is a four-bit parallel in -

parallel out shift register constructed by D flip-flops.


Parallel In - Parallel Out

Shift Registers

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