Digital Electronics Chapter 3 Gate-Level Minimization.
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Transcript of Digital Electronics Chapter 3 Gate-Level Minimization.
![Page 1: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/1.jpg)
Digital Electronics
![Page 2: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/2.jpg)
Chapter 3
Gate-Level Minimization
![Page 3: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/3.jpg)
Karnaugh Maps
Simplify
F =A'B'C + A'BC' + AB'C+A'BC + ABC
![Page 4: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/4.jpg)
K-Map
Simplify
F =A'B'C + A'BC' + AB'C+A'BC + ABC
F = C + A'B
![Page 5: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/5.jpg)
K-Map with “don’t care”Simplify
F(w,x,y,z) = Σ (1,3,7,11,15)
d(w,x,y,z) = Σ (0,2,5)
F = z (y + w' )
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DeMorgan’s Picture!
Two Equivalent Representations
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How Bubbles Move !
F = AB + CD
Three equivalent representations of F = AB + CD
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NAND Implementation
F = xy' + x'y + z
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Designing for Equivalence
Design a circuit to check if x = y
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Hint: Review XOR and XNOR
XNOR will be high if x = y
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Odd and Even Functions
(a) Checks for odd number of 1’s
(b) Checks for even number of 1’s
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Parity Generator / Checker
Even Parity Generator Even Parity Checker
P = 1 if x,y,z have odd number of 1’s so that the four bits, x, y, z, and P have an even number of 1’s
C= 1 if there is error, that is if the four bits received have an odd number of 1’s
![Page 13: Digital Electronics Chapter 3 Gate-Level Minimization.](https://reader036.fdocuments.net/reader036/viewer/2022081501/5697bfdc1a28abf838cb0fd1/html5/thumbnails/13.jpg)
VHDL
Verilog Hardware Description Language
// A simple example
module my_example (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1 (e,A,B);
not g2 (y,C);
or g3 (x,e,y);
endmodule
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Comments on my_example
// indicates a comment line
statements are terminated with ;
endmodule has no semicolon
keywords like module, input etc. must be in lowercase
gate declarations must have the output first then the inputs separated
by commas
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Circuit Diagram of my_example
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That’s All Folks!