Number systems and Codes

1) Codes – Decimal, Binary, Octal, Hex2) Conversions between the above codes3) XS-3, Gray, BCD (8421, 2421, etc)4) Hamming code5) 1’s Complement notation (Addition, etc)6) 2’s Complement notation (Addition, etc)7)

Digital Arithmetic/Boolean Algebra

1) Boolean Algebra Axioms and theorems

a) Identity: X+0 = X, X.1 = Xb) Commutative: X+Y = Y+X, X.Y = Y.Xc) Distributive: X.(Y+Z) = X.Y + X.Z, X+Y.Z = (X+Y).(X+Z)d) Idempotent law: X+X = X, X.X = Xe) De-Morgan’s law: (X+Y)` = X`.Y`, (X.Y)` = X`+Y`f) Absorption law: X+X.Y = X, X.(X+Y) = X.g) Duality (replace ANDs and ORs): X.Y+Z` = (X`+Y`).Zh) Consensus theorem: X.Y+X`.Z+Y.Z=X.Y+X`.Z

ProofX.Y+X`.Z+Y.Z = X.Y+X`.Z+Y.Z(X+X`) = X.Y+X`.Z+X.Y.Z+ X`.Y.Z= X.Y(1+Z)+ X`.Z(1+Y) = X.Y+X`.Z

i) Shannon’s expansion theorem: Any function F can be represented asF = X.F(X=1)+X`.F(X=0)Example

If F = X`Y +XYZ`+X`Y`ZF(X=1) = YZ`F(X=0) = Y+Y`ZSo, as per Shannon’s theorem, F = X.(YZ`) + X`(Y+Y`Z) which is the R.H.S of the first equation, from where we started. Similar, deductions can be made out from any of the other variables also

2) Any Boolean expression can be expressed in terms of MIN terms and MAX terms. A literal is a variable with a term which may or may not be complemented. For an expression of N variables, each MIN term is a product of N literals, and each MAX term is the sum of N literals, with each variable appearing exactly once in both the cases.

3) In summary, any expression can be represented in terms of MIN or MAX terms. If an expression if represented using MIN terms (their sum), it is called as Sum of Products (SOP). Similarly, if a boolean expression is represented as the product of MAX terms, it is called as Product of sums (POS).

Conversion of an SOP based expression to a POS based expression is done using the Duality/De-Morgan’s laws.

4) Prime Implicants, K-MAP, etc

Logic Gates

1) Logic Gates

AND (Output is 1, only if all inputs are ones)

A B Y = A.B0 0 00 1 01 0 01 1 1

OR (Output is 1, if at least one input is one)

A B Y = A+B0 0 00 1 11 0 11 1 1

XOR (output is 1, if odd number of inputs is/are one/ones)

A B Y = A^B0 0 00 1 11 0 11 1 0

NOT (Output is reverse of input)

A Y = ~A0 11 0

NAND (Output is 1, if atleast one input is 0)

A B Y = ~(A.B)0 0 10 1 11 0 11 1 0

NOR (Output is 1, only if all inputs are zeros)

A B Y = ~(A+B)0 0 10 1 01 0 01 1 0

XNOR (Output is 1 only if both the inputs are the same)

A B Y = ~(A^B)0 0 10 1 01 0 01 1 1

2) Universal Gates

NAND and NOR gates are called as universal gates, as it is possible to realize all other logic gates using these two gates individually.

3)

Combinational logic

1) Combinational logic involves the logic that doesn’t have any memory (no state information).

2) Basic combinational building blocks include – Multiplexers (2^n inputs, n select lines and 1 output), Demultiplexers (1 input, n select lines and 2^n outputs), Decoder (n inputs and 2^n outputs), Encoders (n outputs and 2^n inputs)

3) Priority Encoder

4) Adders – Half adder, Full adder, Ripple carry adder, Carry Look ahead, CSA, Carry Skip adder, BCD adder

5) Subtractors

6) Comparators

7) Multipliers

8) Parity circuit

Latches and Flip-Flops

1) A basic S-R latch is a back to back connected NOR/NAND gates (2-input). If both the inputs are 1’s, both the outputs become 0’s. Now, if at this instance (assumed to be a stable condition), both the inputs are made zeros, both the outputs toggle between both zeros and both 1’s (assuming equal delays for both the gates). In practice, both the paths will have different delays and the outputs fluctuate for sometime and settle down on a stable value (not predictable which state though)

2) A gated SR latch (also called a transparent latch) has an enable signal to control the latch. When the gate input is 0, the latch will preserve its state as it is. When the enable signal is high, the latch behaves as the circuit shown in point 1. The latch then preserves the state when the enable goes low again. Even in this Latch, it is not a good idea to move from both inputs ones to both inputs zeros (also possible by driving the enable signal low)

3) The setup and hold times of a latch are specified w.r.t. the falling edge of the enable signal

4) D- latch stores the value present at the input. The D- latch is an extension of the above circuit, where the input combination of both ones (and even both zeros) is avoided by complementing the inputs going to S and R inputs. The S input is the D-input of the latch and the negated –s (not gate) goes to the R- input of the latch.

5) D- latch has removed the issue that occurs in S-R latch when both the inputs are ones. J-K latch is an extension of S-R latch (2 – inputs, no issue when both the inputs are 1’s). Infact, it is a combination of S-R and T- latches

when both inputs are 1’s, outputs are the negation of previous outputs when both inputs are 0’s, outputs are same as the previous outputs when J = 1, K = 0, Q = 1, Q’ = 0 when J = 0, K = 1, Q = 0, Q’ = 1

S = J.Q`, R = K.Q (JK from SR)

6) When the 2 inputs of a JK – latch are shorted, a T- latch is obtained.

When T = 0 , Q(n+1) = Q(n), Q`(n+1) = Q`(n) When T = 1, Q(n+1) = Q(n)’, Q`(n+1) = Q`(n)’

7) JK Master – Slave8) FLOP conversion

Sequential Design

1) Shift registers – 4 types2) Counters – Up counters, Down counters, UP/DOWN counters, Johnson counters,

Ring counter.3)

Finite State Machines

4) Mealy is faster, uses fewer states, maybe transparent to glitches5) If edge sensitive control, typically Mealy is used. If level sensitive, Moore is

preferred.6)

Meta-stability is the inability of a flop output

Timing and Problems in Digital Designs

1) Meta-stability

Meta-stability is the inability of a flop output to assume a definite state of either 1 or 0 for an indefinite time, as the input was not stable for the minimum amount of time during which it was supposed to get sampled.

Possible reasons for Meta-Stability

a) Setup/Hold violations on the data input (w.r.t the sampling edge) of the FLOP.b) Source FLOP and Target FLOP being in different clock domains (different

frequencies). This can be eliminated using proper synchronization techniques.c) Source and Target FLOPs working at the same frequency, but the corresponding

clocks have a phase difference/Skew.

Setup Time

Setup time of a FLOP is the minimum time before the clock/sampling edge for which the input signal should be stable.

Hold Time

Setup time of a FLOP is the minimum time after the clock/sampling edge upto which the input signal should be stable.

If the input signal to a Flop changes in the window of time defined by the setup and hold times (window around the sampling edge, be if positive edge or negative edge), the FLOP output will go into a meta-stable state. The IC foundries provide a library with set of flops that have different characteristics (setup/hold, etc) with an estimate of the MTBF (mean time between failures), which is dependent on things like Temperature, Load, Voltage, along with other on chip fabrication related variations.

Timing

Any Digital ASIC can be visualized as a set of combinational clouds between FLOPS. The maximum frequency at which the chip can work is an analysis of all sets of the following paths.

a) FLOP to FLOP (this path more or less defines the maximum frequency).b) Primary input to first level of FLOPS.c) Last level of flops to Primary outputs.d) Primary inputs to Primary outputs.

The synthesis tool tries to analyze all the above paths, and based on the constraints (Target Frequency, Max Load at each node, Input Drive strengths, any input latencies, etc) tries to map the Library (selecting from the various cells) on to the RTL, thereby generating a net-list for the specified constraints. The tool tries to meet the constraints as much as possible. Otherwise, it gives the list of paths and the corresponding violations. It is left to the designer from then on to fix the design to meet the timing. This process doesn’t involve any stimulus, and hence it is popularly known as ‘Static timing analysis’ or simply STA.

Note: Dynamic timing analysis is done in simulations. Typically, it involved mapping the exact delays (SDF annotation) on to each cell of the net-list, specifying the exact delays on the inputs and run the vectors. It is essentially running simulations with exact delays.

Here are a few timing related definitions.

Propagation Delay (tpd): It is the time taken by a combinational cloud to arrive at a stable state for a set of inputs. The combinational cloud is assumed not to change its state after this time for a set of inputs.

Contamination Delay (tcd): Minimum time taken by a combinational cloud to start changing for a given set of inputs. The combinational cloud arrives at a final value after a few toggles on the output. It is to be understood that before the contamination delay (from the time an input changes), the outputs of the combinational cloud are guaranteed not to change.

For sequential circuits, the definitions change a little bit.

CLK-Q Delay (propagation delay of a flop): This is the amount of time required for a change in the FLOP input to result in a permanent change in the FLOP output.

Contamination Delay (tcd): Minimum time required for a FLOP clock input to result in an initial change in the FLOP output.

Now, let us take a simple circuit with timing defined for each cell and try to arrive at the maximum clock frequency of the circuit. Please note that the synthesis tool does similar analysis on all such paths in a larger circuit.

It is to be understood that the work to be done in one clock cycle determines the maximum clock frequency of the circuit above. This work essentially considers the following things.

a) The input to FLOP A will take the propagation delay of 10ns to appear on the output.

b) The combinational delay will be of 5ns because of the inverter.c) The second flop needs the setup time to be valid. i.e. the data should be ready

before the setup time of the second FLOP, which is 2ns.

In total, it takes 10+5+2 = 17ns for the delay between FLOPS. So, max freq = (1/17) = 58.8 Mhz

It is to be noted that the inverter between the Flops is a simple example for a combinational cloud between FLOPS. The frequency is determined by the FLOP to FLOP path that has the most delay. Such a path is called the ‘most critical path’ (it spreads from the primary input to the primary output through a chain of intermediate flops).

Other than the setup time, circuits should also satisfy the hold time. The contamination delays typically make sure that the hold time on the input of a flop is satisfied.

In the circuit above, the contamination delays are analyzed to see if there could be a hold violation. In the path A->B, the contamination delay of Flop A (2ns) > the hold constraint of the Flop B (1ns). Similarly, in the path A->C, the total contamination delay is 4 ns (2ns for Flop A and 2ns for the combination cloud). In essence, as it takes at least the hold time of the target flop, there would be no hold violation in the circuit above. In this case, the contamination delay (on the D input of a flop) makes sure that the input to the Flop doesn’t change until at least the hold time.

It should be obvious that even if the contamination delays are lesser, the propagation delays (both of the source FLOP and of the combinational cloud) will also add up such that the input to the target flop doesn’t change within the hold time, as any input change at the source flop takes that much more time to cause a change in the input of the target flop.

If the delay between flops is less than the target time period, the remaining time is shown by the synthesis as +ve slack (the data is ready at the target flop well before the target flop samples it). Otherwise, it becomes –ve slack.

If a circuit has setup violations, it should be possible to run it, but at a lesser frequency. But, a circuit/chip having Hold violations cannot be run even at lower frequencies.

2) Data Hazards and Glitches

Combinational clouds that have imbalanced paths (w.r.t time) from the inputs to the outputs may result in glitches (momentary toggling between 0<->1 because of imbalanced paths). Hazard is a circuit which may produce a glitch.

Types of Hazards

a) Static – Zero Hazard

b) Static – One Hazard

c) Dynamic Hazard

or

3) Clock Skew

In huge synchronous circuits, there could be problems as a result of the Clock arriving at different times at different internal components. This also defines the overall operating frequency. Positive skew occurs when the target flop sees the clock at a time (= skew) later than the source clock. Negative skew is the opposite.

4)

Miscellaneous

Q and A

1) There is a timing violation, what are some of the things you would try to do to eliminate it or improve the timing on that path?

A) Look for parallelism in the RTL code – Optimize the logic in such a way that it reduces the overall combinational delay. There could be priority logic somewhere (perhaps unnecessarily).

B) If it is fine, try to move the logic from before the flop to after the flop. This should be fine if the output of the logic is not immediately used in the next cycle or if the next cycle has sufficient time available already.

C) If it is fine, go for a register file based memory than a RAM (if there is such an element in the design). Register files are faster, but perform worse w.r.t Power and area. So, it becomes a trade-off.

D) Look for any chances of pipelining.E) Reduce the load on critical nodes by replicating the drivers.F) Use one hot encoding instead of binary encoding for state registers.G) Timing critical paths can use low Vt cells to improve timing (in the backend), but

with a penalty on power.

2) If the design doesn’t meet power, what are various things that you would do to meet the power specification?

A) Look for the data path and gate the various flops and combinational clouds with the required controls to reduce dynamic power.

B) Use high Vt cells to reduce power, but with a penalty on timing.C) Avoid register file based memoriesD) Look for algorithm level changes. For example, use Gray coding on the address

bus if the design mostly operates on sequential addresses. That way the toggling on the address bus gets minimized, thereby reducing Dynamic power.

E) If the application permits, run the chip at a lower frequency.F) Voltage scaling can also be done to reduce power.G) Use Clock Gating

3) What are multi-cycle paths

Sometimes, a combinational (or non-sequential) path (between 2 registers) may take more than one cycle to arrive at a stable result. It could be because of the combinational delay and/or because of the delay due to large wire lengths. The nature of the design could be in such a way that the result is not required in the following cycle. Such paths are called multi cycle paths.

4) What is a false path

Any path sensed by the synthesis tool that is not essentially a functional path. Any path that holds no meaning for the working of the module.

5) What is a critical path

A path that takes the maximum delay between 2 flops or through a series of flops is called as a critical path.

6) If a design (just before tape out) has both setup and hold violations, and it is fine to fix only one of them, what would you fix? If there are 2 chips, one has hold and other has set-up violations, which chip can still be used?

It would be good to fix the Hold violations, as the Chip can be run at a lower speed to avoid the setup violations (of course, the application needs to be trimmed down a bit to be run at a lower frequency).

7) How do you convert an XOR gate into a buffer and an inverter

8) Implement 2-input AND, OR, XOR, NAND, NOR, XNOR gates using a 2x1 Mux

AND

OR

XOR

NAND

NOR

XNOR

9) Compare and contrast Synchronous and Asynchronous resets

A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the clock. The reset signal is applied as is any other input to the state machine.

Advantages:

The advantage to this type of topology is that the reset presented to all functional flip-flops is fully synchronous to the clock and will always meet the reset recovery time.Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant.

Synchronous resets provide some filtering for the reset signal such that it is not effected by glitches, unless they occur right at the clock edge. A synchronous reset is recommended for some types of designs where the reset is generated by a set of internal conditions. As the clock filters the logic equation glitches between clock edges.

Disadvantages:

The problem in this topology is with reset assertion. If the reset signal is not long enough to be captured at active clock edge (or the clock may be slow to capture the reset signal), it will result in failure of assertion. In such case the design needs a pulse stretcher to guarantee that a reset pulse is wide enough to be present during the active clock edge.

Another problem with synchronous resets is that the logic synthesis cannot easily distinguish the reset signal from any other data signal. So proper care has to be taken with logic synthesis, else the reset signal may take the fastest path to the flip-flop input there by making worst case timing hard to meet.

In some power saving designs the clocked is gated. In such designed only asynchronous reset will work.

Faster designs that are demanding low data path timing, can not afford to have extra gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter what the clock signal is. This is considered as high priority signal and system reset happens as soon as the reset assertion is detected.

Advantages:

High speeds can be achieved, as the data path is independent of reset signal. Another advantage favoring asynchronous resets is that the circuit can be reset with or without a clock present. As in synchronous reset, no work around is required for logic synthesis.

Disadvantages:

The problem with this type of reset occurs at logic de-assertion rather than at assertion like in synchronous circuits. If the asynchronous reset is released (reset release or reset removal) at or near the active clock edge of a flip-flop, the output of the flip-flop could go meta-stable. Spurious resets can happen due to reset signal glitches.

Conclusion

Both types of resets have positives and negatives and none of them assure fail-proof design. So there is something called "Asynchronous assertion and Synchronous de-assertion" reset which can be used for best results.

10) Design a 3-input NAND gate using minimum number of 2-input NAND gates

11) Implement a D-FLOP using a 2x1 Multiplexer

12) Implement a J-K Flip Flop using a D Flip Flop

13) What would you do to avoid Hold violations

A) Add buffers (delay elements) just before the target flopB) Add lockup latches, if the Hold violations is a lot

14) FLIP FLOPS VS Latches

Flip Flops are edge sensitive and Latches are level sensitive. Latches and sensitive to glitches, where are Flip flops are immune to Glitches. Latches need lesser number f gates than flip flops, and therefore latches consume lesser power. Latches are faster than Flip flops.

15) Why are Latches not desirable in digital designs or why should ‘Latch inferences’ be avoided unless until it is required for sure.

Synthesis tool will infer Latches if RTL is not coded properly. In this Case, Latch inference is logically incorrect. This will lead to synthesis and simulation mismatches. Therefore, Latch inference should be verified during LINT stage of the RTL. Also, STA tools analyze timing based on the single clock analysis. Tools are not efficient for Latch analysis and Latches will be a problem during DFT. Therefore, latches should be avoided unless it is needed.

16) Given a clock signal of frequency ‘f’, design a simple circuit that generates an output signal whose frequency is ‘f’/2

17) Given a clock signal of frequency ‘f’, design a simple circuit that generates an output signal whose frequency is 2f

18) If A*B = C => A*C = B and B*C = A, then which Boolean operation is ‘*’

XOR.

19) What are the various state encoding techniques used. State their advantages and disadvantages.

One-Hot encoding: Each state is represented by a bit flip-flop). If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 1000, 0100, 0010, and 0001. If the value is 0100, then it means second state is the current state.

One-Cold encoding: Same as one-hot encoding except that '0' is the valid value. If there are four states then it requires four bits (four flip-flops) to represent the current state. The valid state values are 0111, 1011, 1101, and 1110.

Binary encoding: Each state is represented by a binary code. A FSM having '2 power ‘N' states requires only N flip-flops.

Gray encoding: Each state is represented by a Gray code. A FSM having '2 power N' states requires only N flip-flops.

20) Design a divide by three sequential circuit with 50% duty cycle.

Any divide by N circuit, where N is odd and it is required to generate a signal with 50% duty cycle can be done in the following way.

Step1: Design a counter that counts from 0 to N-1 (0 to 2 for divide by 3, 0 to 4 for divide by 5, etc)

Step2: Use to T flip flops (separately). Generate the enable to the first FLIP FLOP when the counter value = 0. Generate the enable to the second FLIP FLOP when the counter value = (N-1) or 2 in this case.

Step3: XOR the 2 T-FF outputs

Here, div1 and div2 are the two T-FF outputs.

The following circuit can be used for non-integer divisions (1.5, 2.5 etc). The similar thought process can be applied to other non-integer divisions.

21) Construct a deterministic finite state machine to accept the set of all binary strings without leading 0’s, of integers that are powers of 8 (Just draw the state transition

diagram indicating all the transitions, the Initial and the Final states. The final state is the state where the strings which satisfy the above criterion end)

22) How do you implement a 16:1 MUX using 4:1 MUXes

23) Implement the function, F(X,Y,Z) = S(0,1,3,6) using a single 4x1 MUX and an inverter

24) Design a D-FLIP FLOP from 2 latches

25) Design a Transparent latch using a 2:1 MUX

26) What is race-around condition in a J-K Latch

The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the output to complement again and repeat complementing until the pulse goes back to 0, this is called the race around problem. To avoid this undesirable operation, the clock pulse must have a time duration that is shorter than the propagation delay time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered construction.

27) How do we generate random sequences in digital circuits?

By using LFSRs (Linear Feedback Shift Registers), we can generate pseudo random sequences.

28) Draw Mealy and Moore state diagrams for a 11011 sequence detector

Moore State Machine

Mealy State Machine

29) In a 4-bit Johnson counter, how many unused states are there?

A 4-bit Johnson counter has the following sequence 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000. So, there would be 8 unused states.

30) Synchronous Vs Asynchronous Designs31) Synchronous Vs Asynchronous memories

32) Synchronous and Asynchronous FIFOs33) Synchronization34) Calculation of the Depth of a FIFO35) List out a few common LINT errors/Warnings

a) Latch inferenceb) Combinational feedbackc) Undriven inputsd) Unconnected/Not loaded outputse) Multiple drivers on a net

36) Define Clock Skew, Negative Clock Skew and Positive Clock skew

Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock.

There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

37) SETUP/HOLD/META-STABILITY (Refer the chapter on timing)38) What is the difference between a Latch based and a FLOP based design

39) How do you implement a full subtractor using a full adder

Calculate the 2’s complement of operand 2. OP1 – OP2 = OP1 + 2’s complement of OP2.

40) If you add two four-bit a) Signed numbers and b) Unsigned numbers, how do you detect overflow (addition crosses 4-bit signed and unsigned boundaries)

a) For signed, it is the XOR of the carry into MSB and carry out of MSBb) For unsigned, it is the unsigned carry out of the MSB.

41) Design a circuit to get a) 90 degrees b) 180 degrees and c) 270 degrees phase shift in the input signal

42) What advantages do synchronous counters have over asynchronous counters43) What type of FLIP FLOPS can be used to design a memory cell?

D is a good choice (check again)

44) What is MTBF and what is its significance

45) What are the applications of a buffer

a) To introduce a small delay in a pathb) To work around high fan-out/load cells – Split the node and reduce the load, to

improve the timing.

46) What is skew, what are problems associated with it and how to minimize it?

In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times.

This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways. Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough, then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data that should have been clocked through. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period.

Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period, at which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this linear program, zero clock skew is merely a feasible point. Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay buffer so that all clock inputs arrive at the same time

47) What is Slack

'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must happen'.

Negative slack implies that the 'actually happen' time is later than the 'deadline' time. In other words it's too late and there is a timing violation, you have a timing problem that needs some attention. There could be cases where the ‘actually happen’ time is before the ‘deadline’ time. In such cases, there is positive slack.

48) Mealy VS Moore

Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges). Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.

Advantages and Disadvantages.

a) In Mealy, as the output variable is a function both input and state, changes of state of the state variables will be delayed with respect to changes of signal level in the input variables, there are possibilities of glitches appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the input signal level. b) All of the concepts can be applied to Moore-model state machines because any Moore state machine can be implemented as a Mealy state machine, although the converse is not true.

c) Moore machine: the outputs are properties of states themselves, which means that you get the output after the machine reaches a particular state, or to get some output your machine has to be taken to a state which provides you the output. The outputs are held until you go to some other state

Mealy machine: Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after that clock cycle.

d) Mealy is faster, uses fewer states. Mealy gives immediate response to input and Moore gives response in the next clock.

NOTE: If edge sensitive control, typically Mealy is used. If level sensitive control, Moore is preferred.

49) Design a circuit to calculate the square of a number. It should use combinational logic elements only.

50) What is a Snake path?

A combinational path that goes from one module and returns to the same module through several modules.

51) Design a digital one-shot circuit. If there is an input that is high for more than one-cycle, the output should be high for one cycle.

Take 2 D-flops in sequence and AND its outputs.

52) Design a divide (frequency)-by-5 circuit

53) What is reset removal and reset recovery