Dig i Taltys

Instrumentation EngineeringDigital Electronics

WORKBOOKWORKBOOKWORKBOOKWORKBOOKWORKBOOK

2016

Detailed Explanations ofTry Yourself Questions

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T1.T1.T1.T1.T1. Find the value of x.(135)x + (144)8 = (214)x + 2

[x = 7]

T2.T2.T2.T2.T2. Write gray code for binary numbers from 0000to 1111.

T3.T3.T3.T3.T3. In a particular number system the cubic equation

x3 + bx2 + cx – 190 = 0has roots x = 5, x = 8, and x = 9.Find the baseof number system.

[15]

T4.T4.T4.T4.T4. Consider the addition of numbers with differentbases(X)7 + (Y)8 + (W)10 + (Z)5 = (K)9

If X = 36, Y = 67, W = 98 and K = 241 then findthe value of Z.

[34]

T5.T5.T5.T5.T5. Consider a System System System System System SSSSS as shown in the figurebelow

1compliment

’s 2compliment

’sI0I1I2I3

Y0Y1Y2

Y3

System S

System System System System System SSSSS performs 1’s compliment of the inputand then 2’s compliment to produce output.

A new System System System System System HHHHH is designed in which 3 SystemSystemSystemSystemSystem

SSSSS are cascaded

System S

I0I1I2I3

System S

System S

O0

O1

O2

O3

Output

System H

If the applied input (I3 I2 I1 I0) is 1010, then whatis the output (O3 O2O1 O0).

[1101]

Number Systems and Codes1

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Boolean Algebra and Logic Gates2

T1.T1.T1.T1.T1. Find minimum number of two input NANDgates needed to implement the boolean

function f(A,B,C, D) = �� .[7][7][7][7][7]

T2.T2.T2.T2.T2. A bank has 3 locks with 1 key for each lock.Each key is owned by a different person. In orderto open the vault atleast two people must inserttheir keys into the assigned locks. All the keysare not inserted at the same time. If the systemis to be designed with only two input NANDgates, then find the number of NAND gatesrequired.

[6][6][6][6][6]

T3.T3.T3.T3.T3. A Boolean expression containing 3 variable istrue only if any of the following conditions issatisfied.1. A is true and either B is true or C is false.2. A is false and B is true3. C is true and either A is true or B is falseFind the minimized Boolean expression.

[[[[[AAAAA + + + + + BBBBB + + + + + CCCCC]]]]]

T4.T4.T4.T4.T4. A car alarm system is to be designedconsidering 4 inputs, door closed (D), key in(K), seat pressure (S) and seat belt closed (B).The alarm (A) should sound if1. the key is in and door is not closed or2. the door is closed, the key is in, driver in

the seat and seat belt is not closed.The system is to be designed with 2 input basic

gates and inputs are available in basic form only.Find the number of gates required.

[6]

T5.T5.T5.T5.T5. If the waveforms A, B, C shown in figure beloware applied to the Ex-NOR gates. Find thefrequency of output.

Y

AB

C

A

B

C

1 sμ

[125 kHz]


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Combinational Logic Circuits3

T1.T1.T1.T1.T1. Design 4 × 2 priority encoder using basic gatesonly.

T2.T2.T2.T2.T2. Design 4 × 1 multiplex using only 2 input NANDgates.

T3.T3.T3.T3.T3. Design a logic circuit for detecting equality of2-bit binary numbers.

T4.T4.T4.T4.T4. Design a combination circuit that accepts a 2bit number as input and generate binary numberequal to square of the input number.

T5.T5.T5.T5.T5. Consider the logic circuit given below:

I0′I1′

I15′

I13

A B C D

A B CDB D A

I0I1

I15 S2 S1 S0

16 × 1MUX

In′1 × 16De MUX

S3 S2 S1 S0S3

Input at line I13 in 16 × 1 Mux corresponds to

output at line �′Ι of 1 × 16 De Mux. Find the

value of ‘n’.[n = 7]


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Sequential Circuits4

T1.T1.T1.T1.T1. Reduce the following state diagram and alsowrite the reduced state table.

�

� �

�

�

��

��

��

��

��

��

��

��

[20 marks : 2013][20 marks : 2013][20 marks : 2013][20 marks : 2013][20 marks : 2013]

T2.T2.T2.T2.T2. Draw finite state machine model for S – R,J – K, D and T flip-flops.

T3.T3.T3.T3.T3. Consider the circuit given below.

BCD

UpCounter

I1

I0

2x4Decoder

Y3

Y2

Y1

Y0MSB

LSB

Clock

Find the duty cycle of Y2 .[30%]

T4.T4.T4.T4.T4. Consider the circuit given below

Ripple UpMOD 10

Counter

A0

A1

A2

A3

B0

B1

B2

B3

Comp--arator

A>B

A=B

A<B

MOD 10Ripple Down

Counter

MOD 10Ripple

UpCounter

LSB

MSB

C2

C3

C1

Clock

MSB and LSB of MOD 10 ripple up counter actsas clock to 4 bit ripple down and up counterrespectively.Initially all the counter were cleared and outputof comparator was A = B. The clock pulse isapplied. Find the minimum number of clockpulses required to make A = B again.

[17]

T5.T5.T5.T5.T5. Consider the circuit given below

bf

a

g

d

e c

a

b

c

d

e

fg

4 bit RippleUp Counter

4 bit RippleDown Counter

Enable

LSB

MSB

LSB

MSBC1

C2

7 segmentdisplay

Clk

If Enable = 0 ; 7 segment display 11 (b = c = e= f = 1)

6 Instrumentation Engineering • Digital Electronics


Enable = 1 ; 7 segment display data accordingto InputsInitially both the counter were cleared. After 78clock pulses find the data displayed on the 7segment display.

[11]


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Memories5.

T1.T1.T1.T1.T1. Consider the ROM shown below

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

(MSB)X3 X2 X1 X0

BCD to Decimal decoder

Y3

Y2

Y1

Y0

(MSB)

If the coding scheme for X3 X2 X1 X0 is BCD thenfind coding scheme for Y3 Y2 Y1 Y0 .

T2.T2.T2.T2.T2. Consider the digital circuit given below.

X

X X

X

X X

X Y Z

A0

A1

A2

3 : 8Decoder

D0

D1

D2

D3

D4

D5

D6

D7

X

Find the simplified expression for “D4” outputof decoder.

[0]


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Vdd

A

B

C

Y

D F

GE

Find the Boolean expression for Y .[[[[[ABCABCABCABCABC + + + + + ADFADFADFADFADF + ( + ( + ( + ( + (EEEEE + + + + + GGGGG)))))FFFFF ]]]]]

Integrated-Circuit LogicFamilies6


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T1.T1.T1.T1.T1. With a neat block diagram, explain the operationof 8-bit successive approximation ADC. Whatis the maximum conversion time for this type ofADC?

[10 marks : 2004][10 marks : 2004][10 marks : 2004][10 marks : 2004][10 marks : 2004]


GrayCode

Converter

Digital toAnalog

ConverterInput 6 bits

LSB

MSBMSB

LSB

Va

The full scale reading of Digital to Analogconverter is 10.5 V. Each bit of Gray codeconverter output is given to digital to analogconverter through an invertor. If input to thecircuit is 110011, then corresponding outputvoltage Va is _____ Volts.

[3.45 V]

T3.T3.T3.T3.T3. Consider the system shown in figure below.

3 bitSynchronousUp Counter

–

+Y0Y1

Y2

LSB

MSB

OutputClock

Ideal op-ampV1

V2

If V1(t) = 2sin(0.1 πt) + 1V2(t) = 4sin(0.1 πt)

1 t sec2 3 4 5

Clock

0The output of ideal opamp and clock act as input

ADC and DAC7to AND gate. If counter is positive edgetriggered. If the output of the counter wascleared at t = 0, then output (Y2 Y1 Y0) of thesystem at t = 10 sec is _______.

[100]

T4.T4.T4.T4.T4. Consider the system given below

I10

I9I8I7

4 bitup

counter

3 bitup

counter

3 bitdown

counter

4 bitdown

counter

I13

I12

I21

I6I5I4

I3I2I1I0

14 bitDAC

Step Size = 1 mV

Output

4 Bit

0

1

2

3

RingCounter

Clock

LSB

MSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

The clock input is connected to the 4 bit ringcounter. The output of the ring counter acts asthe clock for the other counters. All the countersshown in figure are positive edge triggered.The output of all counters act as input to a 14bit DAC with step size (D) equal to 1 V. If initiallyall counter are cleared then find the output ofDAC after 20 clock pulses.

[10.96 V][10.96 V][10.96 V][10.96 V][10.96 V]



EXPLANATIONS

CHAPTER–1CHAPTER–1CHAPTER–1CHAPTER–1CHAPTER–1

T1.T1.T1.T1.T1. (x = 7)Converting into decimal number systemx2 + 3x + 5 + 82 + 4 × 8 + 4 = 2(x+2)2 + x + 2 + 4x2 + 3x + 105 = 2x2 + 8 + 8x + x + 6x2 + 5x – 91 = 0(x + 13) (x –7) = 0x = –13, 7base can’t be negative⇒ x = 7

T2.T2.T2.T2.T2.Binary No.Binary No.Binary No.Binary No.Binary No. Gray Code.Gray Code.Gray Code.Gray Code.Gray Code.

0000 00000001 00010010 00110011 00100100 01100101 01110111 01001000 11001010 11011011 11101100 10101101 10111110 10011111 1000

T3.T3.T3.T3.T3. (15)(15)(15)(15)(15)5 × 8 × 9 = (360)10 = (190)8

360 = B2 + 9 BB = –23, 15Base can’t be negative. So B = 15.

T4. (34)T4. (34)T4. (34)T4. (34)T4. (34)(36)7 = (27)10(67)8 = (55)10

(98)10 = (98)10(Z)5 = (Z)5

(241)9 = (199)10∴ (Z)5 = (199)10 – (27)10 – (55)10 – (98)10

(Z)5 = (19)10

∴ Z = 34


11Electronics Engineering

T5.T5.T5.T5.T5. (1101)(1101)(1101)(1101)(1101)Let a number N is given to the system

output after 1’s compliment = 15 – Noutput after 2’s compliment = 16 – 15 + N = N + 1

3 such systems are connected in cascade.so final output = Input + (3)10 = 1010 + 0011

= 1101

CHAPTER–2CHAPTER–2CHAPTER–2CHAPTER–2CHAPTER–2T1.T1.T1.T1.T1. (7)(7)(7)(7)(7)

A

B

CD

Minimum NAND Gates required are 7.

T2.T2.T2.T2.T2. (6)(6)(6)(6)(6)Let the 3 locks are A, B, C0 - key not inserted1 - key inserted

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1

A B C Y

X

11 1X

00 01 11 1001

ABC

Y AB BC AC= + +

The expression for Y is similar to carry in full adder circuit.So, Number of NAND Gates required are = 6.

T3.T3.T3.T3.T3. (((((AAAAA + + + + + BBBBB + + + + + CCCCC)))))

1. ( )�� +

2. ��

3. ( )� � �+

Expression = �� + + + +



= � � ��+ + = A + B + C

T4T4T4T4T4 (a)(a)(a)(a)(a)

A = �� +A = �� +

K

D

S

B

T5T5T5T5T5 (125)(125)(125)(125)(125)

A

B

C

1 sμ

8 sμ

Y

Frequency of output =�

��

=μ


T1.T1.T1.T1.T1.I3 I2 I1 I0 Y1 Y0

0 0 0 1 0 00 0 1 x 0 10 1 x x 1 01 x x x 1 1

Y1 = � � �+I I I = I3 + I2

Y0 = � � � � � � �+ = +I I I I I I I



Y0

Y1

I0

I1

I2

I3

4 × 2 Priority Encoder

T2.T2.T2.T2.T2.

I0

I1

I2

I3

S1 S0

T3.T3.T3.T3.T3.A1 A0 B1 B0 Y0 0 0 0 10 1 0 1 11 0 1 0 11 1 1 1 1

Y =� � � � � � � � � � � �� + + � � � �� +

=� � � � � � � � � � � � � �� + + +

= � � � � � � � � � �� + + +

= ( )( )� � � ��



A1B1

A0B0

T4.T4.T4.T4.T4.

Y3

Y2

Y1

Y0

X1

X0

CombinationalCircuit

X1 X0 Y3 Y2 Y1 Y0

0 0 0 0 0 00 1 0 0 0 11 0 0 1 0 01 1 1 0 0 1

Y = x0 Y1 = 0 Y2 = � �x x Y3 = x1x0

x1

x0

Y3

Y2

Y1

Y0

T5.T5.T5.T5.T5. (7)(7)(7)(7)(7)

I0′I1′

I15′

I13

A B C D

A B CDB D A

I0I1

I15 S2 S1 S0

16 × 1MUX

In′1 × 16De MUX

S3 S2 S1 S0S3

A B C D′ ′ ′ ′

I13 → A B C D1 1 0 1

A ′ = � � �� ⊕ = ⊕ =



B ′ = B ⋅ D = 1 ⋅ 1 = 1

C′ = � = D = 1

D′ = �� = =In → A ′ B′ C ′D′

0 1 1 1(A′ B′C′D′) = 7

⇒ n = 7


T1.T1.T1.T1.T1.

�

� �

�

�

��

��

��

�

��

��

��

��

��

Considering the input sequence 01010110100 starting from the initial state a. Each input of 0 or 1 producesan output of 0 or 1 and causes the circuit to go the next state. From the state diagram, we obtain the outputand state sequence for the given input sequence as follows. With the circuit in initial state a, an input of 0produces an output of 0 and circuit remains in state a. With present state at a and input of 1 and the outputis 0 and the next state is b. With present state b and an input of 0, the output is 0 and the next state is c.Continuing this process, we find the complete sequence to be as follows:

��

��

��

In each column, we have the present state, input value and output value. The next state is written on top ofthe next column.

• We now proceed to reduce the number of states. Two states are said to be equivalent if, for eachmember of the set of inputs, they give exactly the same output and send the circuit either to the samestate or to an equivalent state. “When two states are equivalent one of them can be removed“When two states are equivalent one of them can be removed“When two states are equivalent one of them can be removed“When two states are equivalent one of them can be removed“When two states are equivalent one of them can be removedwithout altering the input-output relationship.”without altering the input-output relationship.”without altering the input-output relationship.”without altering the input-output relationship.”without altering the input-output relationship.”



State TState TState TState TState Table:able:able:able:able:��

� �

�

�

�

�

� � �

� �

� �

� � �

� � �

� � �

� � �

=x x x x��

• Now apply the statement written above under inverted comma, we look for two present states that goto the same next state and have the same output for both input combinations. Such states are g and e.They both go to states a and f and have outputs of 0 and 1, for x = 0 and x = 1 respectively. Thereforestates g and e are equivalent, and one of these states can be removed. The row with present state gis removed, and state g is replaced by state e.

Reducing State TReducing State TReducing State TReducing State TReducing State Table:able:able:able:able:

��

� �

�

�

�

� � �

� �

� �

� � �

� � �

� � �

=x x x x

• Present state f now has next states e and f and outputs 0 and 1 for x = 0 and x = 1, respectively. Thesame next states and outputs appear in the row with present state d. Therefore states f and d areequivalent, and state f can be removed and replaced by d. The final reduced table is shown below:

Reduced State TReduced State TReduced State TReduced State TReduced State Table:able:able:able:able:

��

� � � � � �

� � �

� �

� �

� � � �

� � � �

=

• The state diagram for the reduced table consists of only five states. This state diagram satisfies theoriginal input-output specifications and will produce the required output sequence for any given inputsequence.

��

��

��



Reduced state diagram:Reduced state diagram:Reduced state diagram:Reduced state diagram:Reduced state diagram:

�

�

�

�

��

�

��

�

��

��

�

��

T2.T2.T2.T2.T2.(i) SR flip - flop

0 1

S = 1 R = 1

S = 0 R = 1

R = 0S = X

R = XS = 0

(ii)J- K flip - flop

0 1

J = 1 K = X

J = X K = 1

K = 0J = X

K = XJ = 0

(iii) D flip - flop

0 1

D = 1

D = 0

D = 0 D = 1

(iv) T flip - flop

0 1

T = 1

T = 1

T = 0T = 0



T3.T3.T3.T3.T3. (30%)(30%)(30%)(30%)(30%)Output of counter

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � � � �

� � � � I I

Duty cycle = ��

��× =

T4.T4.T4.T4.T4. (17)(17)(17)(17)(17)All the counters are positive edge triggered. In 10 clock pulses MSB of counter C1 goes from low to highonce. LSB of counter C1 goes from low to high 5 times.

00

000000

11

00

001111

00

00

110011

00

01

010101

01

Output of C1

C2

C3

After 17 clock pulseCount of C2 = 9Count of C3 = 9

⇒ Minimum 17 clock pulses are required to make A = B high again.

T5.T5.T5.T5.T5. (11)(11)(11)(11)(11)After 78 clock pulseOutput of counter C1 = (1110)2 = (14)10

Output of counter C2 = (0010)2 = (2)10

7 segment displaya b c d e f g Enable1 1 1 0 0 0 1 0



b

ce

f

a

d

g

⇒ Data displayed on 7 segment is ‘11’


T1.T1.T1.T1.T1.

� � � � � � � ��

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

� � � � � � � �

Clearly Y3 Y2 Y1 Y0 is a 2421 code.

T2.T2.T2.T2.T2.A2 = XZ ⊕ XY = X(Z ⊕ Y)A1 = YZ ⊕ XZ = Z (X ⊕ Y)A0 = XY ⊕ YZ = Y(X ⊕ Z)



D4 = � � ��

A2 =1 1

XYZ

= f2(X, Y, Z) = Σ(5, 6)

�� =

XYZ

1 1 0 1

1 0 1 1 = f1 (X, Y, Z) = Σ(0, 1, 2, 4, 6, 7)

�� =

XYZ

1 1 0 1

1 1 1 0 = f0 (X, Y, Z) = Σ(0, 1, 2, 4, 5, 7)

D4 = � � �� = f2 f1 f0 = 0


T1.T1.T1.T1.T1. (d)(d)(d)(d)(d)Drawing switch equivalent

A

B

C

D E

F

G

Y

From this Y isY = [ADF + ABC + (E + G)DBC + (E + G) F ]′Y = [ADF + ABC + (E + G) (DBC + F)]′




T1.T1.T1.T1.T1.

� ��

��

��

�

��

��

��

!�

"#�

$#��%

��

&��'��

��

��

�%

�(

��

)"&

��

("&

"#� "��'��

$#� $��'��

��

��

The operation of successive approximation A/D converter is as follow:

(i) The SOC goes low, counter is cleared and the digital output is 0000 0000.

(ii) At the same time the input analog voltage is applied such that V0 goes high and the EOC signal goeshigh and the conversion starts.

(iii) During the first clock pulse, the control circuit loads a high MSB into the SAR whose output is then1000 0000.

(iv) If Vin > VDAC, the positive output of the comparator indicates that the MSB is to remain set.

(v) If Vin < VDAC, the negative output of the comparator signals the control circuit to reset the MSB.

(vi) The next lower bits are then handled in the same way. This process is continued until the SAR tries allthe bits.

(vii) When the conversion is complete, the control circuit sends a low EOC signal.

(viii) At the falling edge of the EOC signal the digital equivalent is loaded into the buffer register.

(ix) Thus the buffer register contains the digital output.

So the conversion speed of successive approximation A/D converter is slower than that of parallel A/D converter but faster than that of dual slope A/D converter.

The maximum conversion time for this type of ADC is nTC where n is the number of bits and TC is the timeperiod of one clock pulse.



T2.T2.T2.T2.T2. (3.45)(3.45)(3.45)(3.45)(3.45)Input 110011

Gray code 101010Input to Digital to Analog converter 010101 = 21

Analog voltage =

��

�× = 3.45 V

T3.T3.T3.T3.T3. (100)(100)(100)(100)(100)

v2( )t

v1( )tt1 t2

2010

At t1 and t2 v1(t) = v2(t)2sin(0.1 πt) + 1 = 4sin(0.1 πt)

t = � ��! ! ��

� �

⇒ t1 =��

�

t2 =��

��

Output of AND gate = Clock to the counter

Clock

10

253

53

Logic 0

10 20

20t (sec)

t (sec)

t (sec)

Vsat

Logic 0

Output of op-amp

The clocks applied to the synchronous up counter are 4.⇒ Output of counter is 100.

T4.T4.T4.T4.T4. (10.94)(10.94)(10.94)(10.94)(10.94)In 4 clock pulses each output of ring counter is complemented once.So in 20 clock pulses each output is complemented 5 times.⇒ output of every counter connected at input of DAC will change 5 timesSo Input to 14 bit DAC is



I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I01 0 1 0 1 0 1 0 1 1 1 0 1 1

Binary equivalent = 10939Analog output voltage = Step size × Binary equivalent

= 1 × 10–3 × 10939= 10.94 Volts

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