Diffuse Optical Tomography

Optimization and Miniaturization 

ECE 4902-Spring 2014Thomas Capuano (EE&BME), Donald McMenemy (EE),

David Miller (EE), Dhinakaran Dhanaraj (EE)Faculty Advisor

Dr. Quing Zhu

∗DOT Procedure∗Present System∗Project Goals∗Proposed System∗Budget∗Timeline

Overview

∗DOT – Diffuse Optical Tomography∗ Used in conjunction with Ultrasound

∗Procedure∗ 1) Shine infrared light (140MHz) on

tissue∗ 2) Infrared light is scattered and

absorbed by tissue∗ 3)DOT System captures propagated

light∗ 4) Calculate the scattering and

absorption coefficients∗ 5) Coefficients are used determined

tissue type

DOT Procedure

∗Source Box: ∗ Houses laser diodes and drivers∗ Two Optical switches

∗ Allows for laser wavelength selection∗ Allows for source position selection

∗ Connects laser to probe∗Detection Box:

∗ Connects probe to photomultiplier tube (PMT)∗ Comprised of analog signal processing circuitry and

digital acquisition

DOT System High Level

∗ PC: ∗ NI PCI-1411 (~$1000)

∗ Extracts Ultrasound Images∗ Two NI PCI-6251 with Shielding Cable ($2000)

∗ Records the Input Waveforms∗ Sends Optical Switch Control Signals

∗ Position Selection∗ Laser Wavelength Selection

∗ LabView∗ Synchronizes the Control of the System∗ GUI∗ Data Output for MATLAB Post-Processing

DOT System High Level

∗Goals∗ Reduce Cost∗ Reduce Size ∗ Improve User Friendly Operation

∗Methods∗ Digitize all system controls∗ Redesign analog to digital conversion∗ Control and communication over USB∗Generate GUI for control and processing

Proposed System

∗ FPGA∗ DE0-Nano

∗ Allows for Pin Function Customization∗ Allows for Hardware Algorithms∗ Easy Connectivity Between FPGA and Designed PCB

∗ NIOS II Softcore Processor∗ Interfaces with Altera IP Cores∗ Interfaces with AD7609 Avalon Slave Module

∗ Tools∗ Quartus II – Programming Hardware (HDL)∗ Qsys – System Level and IP Cores∗ ModelSim – Testbench∗ NIOS IDE – Programming Software (C)

Control Function

∗Avalon Memory Mapped Interconnect∗Function

∗ Allows Data communication between multiple devices over the same data lines∗ Primary Signals: Read Data, Write Data, Memory

Address, Read Enable, Write Enable, Wait For Response

∗Advantage∗ Less Connections∗ More Control and Flexibility in Data∗ Interface with Current Altera IP

Data Bus

∗FPGA Output Voltage : 3.3V∗Optical Switch Voltage : 5V∗Level-Shifter

∗ 3.3V to 5V Bidirectional Voltage Translator∗ Number of Bits = 4∗ TXB0104

Control Signals

∗ Required Signals to AD7609∗ RESET

∗ Done Prior to Conversion∗ CONVST X

∗ Triggers ADC∗ CSRD

∗ Triggered 8* Times

∗ * when only collecting bits [17:2]

Analog-to-Digital Converter

∗VHDL State Machine component in Qsys system

∗Ignoring LSBs 0 and 1 of [17-0] to increase sampling frequency

∗Collects 256 samples, stores in embedded (M9K) RAM blocks

AD7609 Control Code

∗Simulated sampling frequency 284KHz∗14 samples per period

AD7609 Control Code

AD7609 State Flow

∗Function∗ Set the Gains of the Photomultiplier Tubes∗ DC Voltages Between 0.2V and 1.2V

∗Part∗ AD5391

∗ DAC∗ ADR431

∗ Voltage Reference∗Control

∗ SPI Interface

Digital-to-Analog Converter

∗ Expansion Ports∗ 8 GPIO Pins∗ 8 GND Pins∗ 4 5V Pins∗ 4 3.3V Pins

∗ Power∗ 5V

∗ LM2937∗ 3.3V

∗ LM2937-3.3∗ System Voltage

∗ +/- 15V 6A DC

Miscellaneous

∗UART (PC to FPGA)∗ FTDI -FT232R

∗USB-to-Serial∗USB Port Treated

as Virtual COM Port∗ Uses

∗Set Voltages for DAC∗Trigger Data Acquisition∗Record Data from ADC

Communication

∗DVI to USB video recorder∗Ultrasound image storage before and after

DOT∗ Provides consistent data for position

∗Epiphan Systems Inc. - DVI2USB 3.0∗ 24-bit Color ∗ Up to 30 Frames Per Second∗ 1920x1200 Resolution∗ Controllable through DirectShow API

Frame Acquisition

∗ADCs: $280 (Provided)∗DACs: $60∗PCBA: $230 ∗FPGA: $100∗Video Acquisition: $700∗Total: $1090

Budget

Timeline

Questions?