HIGH SPEED TECHNOLOGY INFRASTRUCTURE ENGINEERING FOR HIGH SPEED
DFF High Speed
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A High-Speed Low-Power D Flip-Flop Rajasekaran Chandrasekaran" 2, Yong Lian1'2, Ram Singh Rana' lInstitute of Microelectronics, Singapore. [email protected] 2Department of ECE, National University of Singapore. Singapore {g030579 1, eleliany }(nus.edu.sg Abstract - This paper proposes a new D flip-flop configuration based on Differential Cascode Voltage Switch with Pass-Gate Logic. The circuit is able to reduce the transition time from the input to output. The flip-flop was implemented in 0.18 ftm CMOS technology. The flip-flop was simulated using HSPICE to assess the performance and was further evaluated by measurements on a test chip. The maximum operating frequency of the flip-flop is 5 GHz according to simulation. The test chip operates correctly at 3 GHz. This performance makes it one of the fastest flip-flops with a rail-to-rail input and voltage swing. I. Introduction Flip-flops are an integral part of digital systems as they form the core of the timing circuits. The system clock controls the rhythm of the chip. The high density of modem digital processors increases the clock load. With increasing requirement for high-speed and low power, flip-flops with fewer transistors are preferred for their low power consumption and small area occupation. The proliferation of logic circuits with very small propagation delay also forces the flip-flops to have very small latency as otherwise the flip-flop delay occupies a larger part of the clock cycle. Many schemes have been proposed in the literature [1-5] for flip-flops with very few transistors. Most of them use either transmission gates or multiplexers in order to reduce the latency of the flip-flop. The latching of the input is usually done using a sense amplifier. Other implementations employ a differential latch type configuration either with or without a pre-charge and evaluation cycles. Multiplexer based implementations normally implement the latches using multiplexers [2]. The flip-flop is constructed as a cascade of two latches triggered by opposite phases of the clock. Their efficiency is dependent on the fast operation of the multiplexers and the ability of the multiplexer circuit to function as a latch. A multiplexer based flip-flop is shown in Fig. 1. This implementation can employ very few transistors depending on the multiplexer. The main drawback is that the latching operation can be weak reducing the ability of the flip-flop to drive large loads. Another implementation uses cross-coupled pMOS transistors or sense-amplifiers to perform the latching operation [2-4]. This requires that the input to the flip-flop consists of both the true and complement forms. The sampling operation is usually done by a stack of transistors forming a pull-down and gated by the D input and the clock. Fig 1 Multiplexer Based Flip-Flop Some variations involve pre-charge and evaluation phases, wherein the outputs are pulled usually to the high state during the pre-charge phase and during the evaluation phase, the inputs are sampled and the output changed accordingly [2]. One such implementation is shown in Fig. 2. Fig 2 Differential Flip-Flop The flip-flops discussed above sample the input at either the rising or the falling edge of the clock. This necessitates that the clock be at a higher frequency than the data rate. Double edge triggered flip-flops [6, 7] sample the input at both the edges of the clock thereby allowing twice the data rate at the same clock frequency. These usually include a multiplexer functionality built into them. WVhen one of the latches is in the hold state, the other latch samples the input data. In this way, data is transferred at both the edges of a 0-7803-9210-8/05/$20.00 ©2005 IEEE 152 Authorized licensed use limited to: University of Waterloo. Downloaded on July 05,2010 at 18:33:24 UTC from IEEE Xplore. Restrictions apply.
Transcript of DFF High Speed
A High-Speed Low-Power D Flip-Flop
Rajasekaran Chandrasekaran" 2, Yong Lian1'2, Ram Singh Rana'
lInstitute of Microelectronics, Singapore. [email protected] of ECE, National University of Singapore. Singapore {g030579 1, eleliany }(nus.edu.sg
Abstract - This paper proposes a new D flip-flop configurationbased on Differential Cascode Voltage Switch with Pass-GateLogic. The circuit is able to reduce the transition time from theinput to output. The flip-flop was implemented in 0.18 ftmCMOS technology. The flip-flop was simulated using HSPICEto assess the performance and was further evaluated bymeasurements on a test chip. The maximum operatingfrequency of the flip-flop is 5 GHz according to simulation. Thetest chip operates correctly at 3 GHz. This performance makesit one of the fastest flip-flops with a rail-to-rail input and voltageswing.
I. Introduction
Flip-flops are an integral part of digital systems as theyform the core of the timing circuits. The system clockcontrols the rhythm of the chip. The high density of modemdigital processors increases the clock load. With increasingrequirement for high-speed and low power, flip-flops withfewer transistors are preferred for their low powerconsumption and small area occupation. The proliferation oflogic circuits with very small propagation delay also forcesthe flip-flops to have very small latency as otherwise theflip-flop delay occupies a larger part of the clock cycle.
Many schemes have been proposed in the literature [1-5]for flip-flops with very few transistors. Most of them useeither transmission gates or multiplexers in order to reducethe latency of the flip-flop. The latching of the input isusually done using a sense amplifier. Other implementationsemploy a differential latch type configuration either with orwithout a pre-charge and evaluation cycles.
Multiplexer based implementations normally implementthe latches using multiplexers [2]. The flip-flop is constructedas a cascade of two latches triggered by opposite phases ofthe clock. Their efficiency is dependent on the fast operationofthe multiplexers and the ability ofthe multiplexer circuit tofunction as a latch. A multiplexer based flip-flop is shown inFig. 1. This implementation can employ very few transistorsdepending on the multiplexer. The main drawback is that thelatching operation can be weak reducing the ability of theflip-flop to drive large loads.
Another implementation uses cross-coupled pMOStransistors or sense-amplifiers to perform the latchingoperation [2-4]. This requires that the input to the flip-flop
consists of both the true and complement forms. Thesampling operation is usually done by a stack of transistorsforming a pull-down and gated by the D input and the clock.
Fig 1 Multiplexer Based Flip-Flop
Some variations involve pre-charge and evaluation phases,wherein the outputs are pulled usually to the high state duringthe pre-charge phase and during the evaluation phase, theinputs are sampled and the output changed accordingly [2].One such implementation is shown in Fig. 2.
Fig 2 Differential Flip-Flop
The flip-flops discussed above sample the input at eitherthe rising or the falling edge of the clock. This necessitatesthat the clock be at a higher frequency than the data rate.Double edge triggered flip-flops [6, 7] sample the input atboth the edges of the clock thereby allowing twice the datarate at the same clock frequency. These usually include amultiplexer functionality built into them. WVhen one of thelatches is in the hold state, the other latch samples the inputdata. In this way, data is transferred at both the edges of a
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clock cycle. The implementation is shown in Fig. 3. logic is of use in minimizing the transistor count. Thefeedback connection of the pMOS transistors serves to latchthe output. The addition of a clock function makes thesecircuits function as a flip-flop with added logic.
An implementation of the flip-flop using DCVSPG [9] isshown in Fig. 5. The circuit uses two latches, one usingnMOS transistors and one using pMOS transistors. The useof complementary latches eliminates the need for two clocksignals as the latches are operated by the opposite phases of asingle clock.
out+
Fig 3 DET Flip-Flop+
_1r- +r
L.L-+
In applications where the transistor count is required to below, due to area or power considerations, flip-flops can beimplemented using transmission gates and inverters as shownin Fig 4. [1] The transmission gates serve to transmit the inputduring the sample phase and the inverter sense-amplifiershold the output value in the latch phase. The feedbackinverters need to be of smaller size than those of the forwardpath to reduce the power consumption and the transfer delaythat is dependent on the transmission-gate inverter seriespath.
Fig 4 Transmission Gate Flip-Flop
In this paper, we present a new D Flip-Flop circuit basedon the principle of Differential Cascode Voltage Switch withPass-Gate (DCVSPG) [7]. The proposed D Flip-Flop is ableto operate at very high speed while the power consumption iskept low. The paper is organized as follows. Section IIexplains the functioning of the DCVSPG flip-flop followedby the discussion of the proposed flip-flop circuit in SectionIII. In Section IV, the simulation and measurement results arepresented. Section V concludes the paper with a summary.
II. DCVSPG Logic and Flip-Flop
Differential Cascode Voltage Switch with Pass-Gate(DCVSPG) Logic [8] is derived from Differential CascodeVoltage Switch (DCVS) Logic and Pass transistor logiccombining the advantages of both. The combination of thetwo makes the implementation of the logic ratio-free. Thistranslates to the optimization of the individual transistors forhigh performance. The high logic functionality of Pass gate
Fig 5 DCVSPG Flip-Flop using complementary latches
The use of the pMOS latch severely undermines theperformance of the flip-flop as the delay of the latch intransferring the input depends on the pMOS input transistors.The presence of transistors in series also contributes to anincrease in delay.
III. Proposed D Flip-Flop Circuit
A new D-latch circuit is presented in Fig. 6. The outputexpressions of a D-latch with differential inputs can be givenas
Q=D-CLK+Q-CLK
Q=D-CLK+Q.CLK(1)
The above expressions express the sample and latchingoperations. When CLK goes high, the pass transistors areswitched on and the input is is transferred to the output. Thecomplementary inputs pull one of the outputs down and theother output is pulled up by the latching action of thecross-connected pMOS transistors. The latch remains out ofoperation as the transistor controlling it is switched offby thelow CLK . The use ofpass transistor helps reduce the delay ofpassing the data to the output as the delay depends entirely ona single transistor. Another factor contributing to the fasttransfer of the input to the output is that the pull-up of theoutput need not be done for the whole logic level. The inputpass transistor passes a weak high logic, which aids thepull-up thereby reducing the transfer delay.
When CLK goes low and CLK is high, the latch is
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activated and it holds the value until CLK goes high again.The control of the regeneration circuit by the CLK signalreduces the possibility of the latching wrong data due tospurious inputs. The transfer delay of the flip-flop is alsoinfluenced by the size of the latching transistor pair, as theinput pass transistor is loaded by the latch. A very smalllatching transistor leads to a fast transfer of the input to theoutput but the regenerative gain of the latch becomes too lowto hold the transferred value. A large transistor increases theload on the input leading to a reduction in the operating speedof the circuit. Hence, the latch sizing is a trade-off betweenspeed and regenerative gain. The transistors used in theproposed D-latch circuit all have minimum length. Thewidths of the transistors have been optimized for high-speedoperation.
Q 'QB
Do
CLI
CLK
CLKB 4>0
functionality of the flip-flop is tested using input at half therate of the clock signal. The resulting output follows the inputand the maximum operating frequency can be easily verified.The results of simulation for a clock frequency of 5 GHz andinput data rate of 2.5 Gbps is shown in Fig. 8. The powerconsumed at 5 GHz by the flip-flop was found to be 2 mW.
The flip-flop was implemented in a test chip with theinputs driven by buffers. The complementary D inputsrequired by the full adder were generated using inverters inthe chip. The performance was tested by applying sinusoidalsignals to the inputs. The complementary clock inputsrequired by the flip-flop were fed from outside the chip. Togenerate the complementary inputs without any skew, theCLK and CLK inputs were connected via a 1800 powersplitter with added DC bias to ensure voltage swing from0-1.8 V.
DFlip-Flop
-Q
_-QB
Fig 7 Test Circuit for Simulation
CLD DB
CLKB
Fig 6 Proposed D Latch circuit
The flip-flop is formed by cascading two latch circuits in amaster-slave configuration. Since both the latches arerequired to work at the same speed, separate sizing for theslave latch is not necessary.
IV. Simulation, Measurement and Results
The layout of the D flip-flop is developed using Cadence.The post-layout simulations have been done using HSPICEfor a 0.18 pim/1.8 V CMOS technology. All the transistorshave minimum channel length. Since flip-flops are normallyused in cascade with other such cells, their inputs may not beideal. To simulate the actual operating conditions, as closelyas possible, the setup shown in Fig. 7 is used. The
Fig 8 D Flip-Flop simulation results for a clock frequency of 5 GHzand input of 2.5 GHz
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The input D was fed from another signal source with a DCbias. The outputs at 1.5 Gbps corresponding to an input of 1.5GHz and clock of 3 GHz are shown in Fig. 9. The powerconsumption of the flip-flop core could not be measures asthe power supply was shared by the buffers driving the output.The total power consumption including the buffers wasmeasured to be 20 mW as compared to 12 mW when the testset-up was simulated using HSPICE.
Volume: 35, Issue: 6 , June 2000, Page(s):876 - 884.[4] Jimenez R., Parra P., Sanmartin P., Acosta A.,
"High-performance edge-triggered flip-flops usingweak-branch differential latch," Electronics LettersVolume 38, Issue 21, 10 Oct. 2002 Page(s):1243 - 1244
[5] Jian Zhou, Jin Liu, and Dian Zhou, "Reduced setup timestatic D flip-flop," Electronics Letters, Volume 37, Issue5, 1 Mar 2001, Page(s):279 - 280.
[6] Pedram. M, Qing Wu, and Xunwei Wu, "A new designof double edge triggered flip-flops," Proceedings of theASP-DAC 1998. 10-13 Feb. 1998, Page(s):417 - 421.
[7] Johnson T.A., Kourtev I.S., "A single latch, high speeddouble-edge triggered flip-flop (DETFF),"The 8th IEEE Intemational Conference on Electronics,Circuits and Systems, Volume 1, 2-5 Sept. 2001,Page(s): 189 - 192 vol.1
[8] Fang-Shi Lai, and Wei Hwang, "Design andimplementation of differential cascode voltage switchwith pass-gate (DCVSPG) logic for high-performancedigital systems," IEEE Joumal of Solid-State Circuits,Vol. 32, Issue 4, April 1997, Page(s):563 - 573.
[9] Afghahi, M., "A robust single phase clocking for lowpower, high-speed VLSI applications,"- IEEE Journal ofSolid-State Circuits, Volume 31, Issue 2, Feb. 1996,Page(s):247 - 254.
Fig 9 Test results for clock of 3 GHz and D input of 1.5 GHz
V. Conclusions
A D flip-flop circuit has been introduced which offershigh-speed consuming less power. It uses a pass transistorimplementation to sample the input and a DCVSPG stylelatching stage. It overcomes the threshold voltage problemassociated with pass transistor circuits and produces fullvoltage swing at the output. This circuit has a very smalllatency and can be used for high-speed applications.
References
[1] Uming Ko, and Balsara P.T., "High-performanceenergy-efficient D-flip-flop circuits," IEEE Transactionson Very Large Scale Integration Systems, Vol. 8, Issue1, Feb. 2000, Page(s):94 - 98.
[2] Li Ding; Mazumder, and P.; Srinivas, N., "A dual-railstatic edge-triggered latch," The 2001 IEEEInternational Symposium on Circuits and Systems,Volume: 2, 6-9 May 2001 Page(s):645 - 648 vol. 2.
[3] Nikolic B., Oklobdzija V.G., Stojanovic. V., Wenyan Jia,James Kar-Shing Chiu, Ming-Tak Leung, M., "Improvedsense-amplifier-based flip-flop: design andmeasurements," IEEE Journal of Solid-State Circuits,
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