Device Interface Board Design for Wireless LAN TestingProject Plan

TeamMay 06-15

ClientECpE Department

Faculty AdvisorDr. Weber

Team MembersJoseph Chongo, EEMatthew Dahms, EE

Srisarath (Sunny) Patneedi, CprEJustine Skibbe, EE

REPORT DISCLAIMER NOTICEDISCLAIMER: This document was developed as a part of the requirements of an electrical and computer engineering course at Iowa State University, Ames, Iowa.This document does not constitute a professional engineering design or a professional land surveying document. Although the information is intended to be accurate, the associated students, faculty, and Iowa State University make no claims, promises, or guarantees about the accuracy, completeness, quality, or adequacy of the information. The user of this document shall ensure that any such use does not violate any laws with regard to professional licensing and certification requirements. This use includes any work resulting from this student prepared document that is required to be under the responsible charge of a licensed engineer or surveyor. This document is copyrighted by the students who produced this document and the associated faculty advisors. No part may be reproduced without the written permission of the senior design course coordinator.

Date Submitted09/22/2005

Table of Contents

List of Figures........................................................................................................ ii

List of Tables...................................................................................................... iiiList of Definitions............................................................................................... iv1. Introductory Material.......................................................................................1

1.1 Abstract........................................................................................................11.2 Acknowledgement.......................................................................................11.3 Problem Statement and Solution.................................................................1

1.3.1 Problem Statement................................................................................11.3.2 Problem Solution...................................................................................2

1.4 Operational Environment.............................................................................21.5 Intended User and Intended Use.................................................................3

1.5.1 Intended User........................................................................................31.5.2 Intended Use.........................................................................................3

1.6 Assumptions and Limitations.......................................................................31.6.1 Assumptions..........................................................................................3

1.6.1.1 User Assumptions...........................................................................31.6.1.2 System Assumptions......................................................................3

1.6.2 Limitations.............................................................................................41.7 Expected End-Product and Other Deliverables...........................................4

2. Proposed Approach and Statement of Work................................................52.1 Expected end product and other deliverables..............................................5

2.1.1 Functional Requirements......................................................................52.1.2 Constraints Considerations...................................................................52.1.3 Technology Considerations...................................................................52.1.4 Technical Approach Considerations......................................................62.1.5 Testing Requirements Considerations..................................................62.1.6 Security Considerations........................................................................62.1.7 Safety Considerations...........................................................................72.1.8 Intellectual Property Considerations......................................................72.1.9 Commercialization Considerations........................................................72.1.10 Possible Risks and Risk Management................................................72.1.12 Project Tracking Procedures.............................................................10

2.2 Statement of Work.....................................................................................11

3. Estimated Resources and Schedules..........................................................163.1 Personal Effort Requirements....................................................................163.2 Other Resource Requirements..................................................................183.3 Financial Requirements.............................................................................183.4 Project Schedule........................................................................................19

4. Closure Materials..........................................................................................214.1 Project Team Information...........................................................................21

4.1.1 Client Information................................................................................21

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4.1.2 Faculty Advisor Information.................................................................214.1.3 Team Members’ Information...............................................................21

4.2 Closing Summary......................................................................................214.3 References................................................................................................22

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List of FiguresFigure 1: Teradyne J750 v Figure 2: Proposed project setup 2Figure 3: Gantt chart 23

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List of TablesTable 1: Milestone Completion Scoring Rationale 9Table 2: Milestones & Grading Weights 11Table 3: Estimated personal efforts 20Table 4: Estimated additional resources 21Table 5: Estimate project costs 21Table 6: Schedule of Deliverables 22Table 7: Team contact information 24

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List of DefinitionsESD – Electrostatic discharge, or simply the discharge of static electricityECpE – Electrical and Computer EngineeringIG-XL – Software package used to develop test programs for the Teradyne J750ISU – Iowa State UniversityI/O – Input and outputPLL – Acronym used for phase locked loopRF – Radio frequency, refers to signals with frequency in the 9 kHz-300 GHz rangeS/R – Refers to a Send/Receive networkTeradyne J750 – Digital input/output test system donated to Iowa State University by Teradyne. See Figure 1.

Figure 1 – Teradyne J750

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1. Introductory MaterialIncluded in the introductory materials are the abstract, acknowledgements, problem statement and solution, operating environment, intended users and uses, limitations and assumptions, expected end-product and other deliverables.

1.1 AbstractIn a previous senior design project, a wireless front-end was added to

Iowa State University’s Teradyne J750 high-speed RF tester. This provided the J750 with the capability to wirelessly test digital logic chips. However, one of the unresolved issues is the lack of the ability to pass a clock signal from the J750 to the wireless interface. Currently, the wireless interface is not completely independent and the clock signal is passed via wire to synchronize the two devices.

The goal of this project is to assess the different options of recovering the clock signal at the wireless interface and implement the most viable recovery option. If this is possible, this function will be added to the existing wireless tester. If this were fully implemented, the device would be capable of operating in a completely wireless environment.

1.2 AcknowledgementThe team would like to extend a special thanks to Dr. Robert Weber for the time he has dedicated to advising the team through the course of the project.

1.3 Problem Statement and SolutionThis section summarizes the general problem as well as the proposed solution.

1.3.1 Problem StatementIowa State University’s Department of Electrical and Computer

Engineering introduced a senior design project for the 2004 – 2005 academic year with the goal of developing a wireless interface capable of receiving test signals and transmitting results to the department’s Teradyne Integra J750 tester. Over the span of that year, the May05 team was able to successfully prove that the Teradyne tester is capable of testing digital I/O devices using a wireless S/R network. However, the team’s final design did not include any method for clock recovery and synchronization. Without this, the two devices would not be able to communicate properly and data would be lost. Regardless, the group was still able to test their device by running a clock signal from one device to another via a copper wire.

For this project, the goal is to modify the current setup so that the wireless interface shall be capable of recovering a clock signal transmitted by the Teradyne system. Under current conditions, the Teradyne tester is presented with unknown delay conditions. This is caused by the delay between when the signal is sent to the chip under test and when the chip under test replies. Therefore, this team will develop a method to recover a clock signal at the

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wireless interface and devise a means for the J750 to receive a reply after some unknown delay. The final system will resemble Figure 2.

Figure 2 – Proposed Project SetupGraphic courtesy of May05 Senior Design Team

1.3.2 Problem SolutionCurrently, the clock used by the wireless interface is connected via wire to the J750. Options must be researched in order to find the feasible solution to make the interface fully wireless. The main option under scrutiny for clock recovery is the phased lock loop (PLL). In the course of research, other more viable options may arise and the best one will be selected based on cost, implementation, user friendliness, and performance.

1.4 Operational EnvironmentThe finished setup should operate indoors with a temperature range of 27°C to 33°C. Because the J750 is sensitive to temperature and the client is the Department of Electrical & Computer Engineering, it will only operate and test digital I/O indoors in an air-conditioned room. Additionally, it should not be subject to mechanical shock or ESD. Mechanical shock should not be an issue as all users are expected to treat the setup with proper care. To ensure that ESD does not become a problem, all users will be expected to wear ESD bands while using the tester.

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1.5 Intended User and Intended UseThis section defines the intended users and uses of the project.

1.5.1 Intended UserThe intended user is any student or faculty member of the Department of Electrical & Computer Engineering that needs to test the RF capabilities of a wireless device. The user must possess a basic knowledge of RF communication, digital logic and an understanding of how to run tests using the J750. More specifically, the user must be able to synchronize the frequency that runs the clock cycle, with the rest of setup. Additionally, the user must be able to follow the reference manual developed by the previous design team.

1.5.2 Intended UseThe intended use of the project is to sever the tie to all wired inputs from the J750 to the wireless interface. The wireless interface will, therefore, receive a training signal that will program the clock so that it functions on the same cycle as the tester. This preamble will be used for the sole purpose of synchronizing the J750 clock cycle to that of the wireless interface.

1.6 Assumptions and LimitationsThe following section defines the expected assumptions and limitations for

the end-product. Additional assumptions and limitations will be added as decisions are made about the project.

1.6.1 AssumptionsThis section will provide details of the user and system assumptions

1.6.1.1 User Assumptions The user has knowledge in electrical and/or computer

engineering. The user knows English. The user-documentation is/will be

written in English. The user has previous experience testing circuits with the

Teradyne J750. The user has read the Teradyne J750 instruction manual and

will observe all necessary safety precautions as prescribed in that manual.

The user is knowledgeable of electrical hazards.

1.6.1.2 System Assumptions A sufficient clock training signal can be sent by the Teradyne

J750 over the wireless connection to initialize the clock recovery circuitry.

The clock recovery circuitry will be able to interact with the existing FPGA.

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The current wireless communication network can transmit up to five feet. This assumption is based on the May05 team’s documentation.

The phase difference between the system clock of the Teradyne J750 and the recovered clock at the wireless interface will not be greater than the overall system clock speed.

1.6.2 LimitationsThis section will provide details of the limitations identified with the project

The Teradyne J750 is sensitive to temperature fluctuations and must operate within of the calibrated temperature. The current system is set for .

The Teradyne J750 is only capable of testing digital I/O. Because of this, all chips tested with the wireless interface must have digital I/O.

The maximum rate at which user can send data is at 115.2 Kbps The existing transmitter and receiver communicate at 916.5 MHz.

Therefore, nearby wireless signals at similar frequencies may disrupt the setup.

The communication link shall be limited to one frequency. The IG-XL software shall be used in writing the test code for the

Teradyne J750. The distance between the wireless interface and the Teradyne system

will be limited to five feet.

1.7 Expected End-Product and Other DeliverablesThis section will provide the details of the expected end-product and other deliverables

By the end of the spring 2006 semester the project will produce: A completely independent electrical interface between the Teradyne J750

and wireless interface for digital I/O chips. The wireless interface will be able to recover a clock signal generated and

transmitted by the Teradyne tester. A demo test of a digital chip using the Teradyne J750 and the completed

wireless interface.

2. Proposed Approach and Statement of WorkThe following section will introduce the proposed approach and state the

work necessary for completion of the project.

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2.1 Expected End Product and Other DeliverablesThe following section will explain the functional requirements and

constraint considerations of the end product.

2.1.1 Functional RequirementsThe following describes the functional requirements of the end product

With the use of a clock recapturing mechanism in connection with the FPGA, the wireless interface will be able to function as an independent entity.

The send/receive network must establish a strong communication link between the Teradyne system and the wireless interface.

The wireless interface must be capable of testing the I/O of a digital device.

The IG-XL software must instruct the Teradyne system to send a preamble for the purpose of clock recovery.

2.1.2 Constraints ConsiderationsThe following will define the constraints considerations of this project

The Teradyne J750 is sensitive to temperature fluctuations and must operate within of the calibrated temperature. The current system is set for .

The Teradyne J750 is only capable of testing digital I/O. Because of this, all chips tested with the wireless interface must have digital I/O.

The maximum rate at which user can send data is at 115.2 Kbps The existing transmitter and receiver communicate at 916.5 MHz.

Therefore, nearby wireless signals at similar frequencies may disrupt the setup.

The communication link shall be limited to one frequency. The IG-XL software shall be used in writing the test code for the

Teradyne J750. The distance between the wireless interface and the Teradyne

system will be limited to five feet. Only digital components will be tested with the Teradyne J750.

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2.1.3 Technology ConsiderationsIn the following section, technology considerations will be discussed and

as well as the method to be used in determining the best action.Based upon the preference of the faculty advisor, a phase locked loop will

most likely be used as the clock recapturing mechanism. The primary technological decision that will be made is the selection of a PLL integrated circuit as a possible means of clock recovery. To determine the most suitable chip, the following criteria will be considered:

Cost Chip speed Compatibility with digital I/O Ability to customize with peripheral electronics Reliability

Technological solutions other than the phase locked loop will be considered if complications arise preventing the use of this technology. For example, other solutions shall be considered if a phase locked loop proves to be incompatible with the May05 team’s current setup.

2.1.4 Technical Approach ConsiderationsThe methodologies that will be used in completing this project are

described in this section. The approach to be used will include research, design, implementation

and testing. This process will be followed within every stage of the project. This approach will minimize the risks and increase the chances of success.

The first stage is to decide on the goals as well as the budget of the project. The second stage will be to research possible technology, specifically, possible clock recovering mechanisms. For the third stage, the clock recovery circuitry will be designed. Next, parts will be selected and acquired. Following this, the circuit will be built. Lastly, the end-product circuit will be tested.

2.1.5 Testing Requirements ConsiderationsThis section will describe the testing considerations required for the

functionality of the phased lock loop. Testing shall be performed in a modular fashion. The functionality of each

stage developed will be verified one stage at a time. The following tests will be conducted to ensure full functionality of the phased lock loop:

Test if the existing FPGA interface and Teradyne J750 are still functioning properly. Criteria for the test are: strong signal and receiving signals as expected.

Test the setup by monitoring the signal sent by the Teradyne and the signal received by the interface.

Test the setup by monitoring the reply sent by the interface and the signal received by the Teradyne.

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Test the clock recovery mechanism to ensure the loop bandwidth, phase noise and phase margin are favorable for the setup. Criteria for the test are: Reliable regeneration of transmitted clock signal.

2.1.6 Security ConsiderationsThis section will discuss the security concerns brought out by the

development of the project as well as the operation of it by the user.This project does not contain proprietary information therefore no concern

exists of an outside individual gaining knowledge of this project’s outcome. In the design and test phase of this project, signals to and from the J750 must not violate either FCC regulations or interfere with other nearby devices or laboratory equipment.

2.1.7 Safety ConsiderationsSafety considerations that include the user as well as the equipment will

be described in this section. The primary concern lies with damaging the equipment. To ensure safety,

all users will be required to wear ESD wristbands to avoid unwanted electrical shocks to the J750. As the device will not be operating around high voltage conditions, this is not a concern. In addition to this, the user should use caution when repositioning the Teradyne tester to avoid personal injury.

2.1.8 Intellectual Property ConsiderationsThis project is being implemented for the ECpE department and will not be

used for a profit, therefore there are no issues regarding the protection of information. The usefulness of the information, however, will be limited to those who have access to the Teradyne testing laboratory.

2.1.9 Commercialization ConsiderationsThe complete modification to the Teradyne J750, that is, the fully wireless

interface, could be useful to companies who test various wireless systems. However, for the initial stage of design, the team will focus only on a single implementation of its design since Iowa State only owns one Teradyne J750 unit. Further commercialization considerations will be investigated only if the project produces a cost effective, user friendly, well performing product.

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2.1.10 Possible Risks and Risk ManagementThe following section summarizes a set of potential risks that may be

encountered and the proposed solution(s) to keep the project on schedule.

2.1.10.1 Risk: Failure of components created by previous team.Management: All team members will observe ESD precautions while handling electronic devices. If an irreparable failure is discovered during testing, all necessary parts will be repurchased and rebuilt based on existing documentation.

2.1.10.2 Risk: Loss of a team member due to internship or coop.Management: Each team member will document his or her progress in a logbook. Particular attention will be paid to implementation successes and failures so that other team members will not have to retry a solution that has already been proven unsuccessful.

2.1.10.3 Risk: Data or documentation loss.Management: Each team member shall observe the group established convention for labeling documents with the document author name, date, author and time. Updated documents shall then be emailed to the group. Each team member shall save updated documents as a new file instead of overwriting existing file. Team members will store backup copies on the ISU network. This eliminates the possibility of ever having to start any document from the beginning.

2.1.10.4 Risk: The Teradyne J750 cannot function properly with unknown propagation delays resulting from the wireless interface.Management: The wireless interface must be capable of sending a response within one clock period to the Teradyne system’s clock. The delay of each system component must be thoroughly investigated before test data sets can be implemented.

2.1.10.5 Risk: Unable to duplicate May05 team’s work.Management: Each team member shall read documentation created by the May05 team. Meetings shall be scheduled with any remaining May05 team members to ensure proper use of existing equipment. Team members will test existing equipment.

2.1.10.6 Risk: Improper use of Teradyne J750.Management: Contact shall be made with a department representative proficient in the use of the Teradyne system. No certification is needed prior to using the tester other than the approval of a certified department representative. Once approval is received, testing can begin. Team members are also expected to read relevant instructions within existing Teradyne J750 documentation.

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2.1.11 Proposed Project Milestones and Evaluation CriteriaSuccess for the project will rely on the ability to meet the goals and

milestones of the project plan as shown below. Each milestone will receive a score based on how well the goals for that particular milestone were met.

Table 1: Milestone Completion Scoring RationaleProgress Numerical Score (%)

Greatly Exceeded Criteria 100Exceeded Criteria 90Met Criteria 80Partially Met Criteria 70Did Not Meet Criteria 40Did Not Attempt 0

Once the project is completed, each milestone will receive a final score based on its weight and importance.

2.1.11.1 Milestone: Project DefinitionDescription: Defining the project sets a clear goal in mind for the entire team to rally around. This will engender teamwork and ensure that everyone is on the same page, hopefully to avoid future misunderstandings.Evaluated By: Client and faculty advisorEvaluation Criteria: The evaluators will look at the definition in terms of readability, how well it is to understand, clarity, and efficiency.Weight: 16%

2.1.11.2 Milestone: Technological SelectionDescription: Determining which process will provide the interface with the best performance is the primary goal of this project. This will include all the research that goes into which option is the best.Evaluated By: Project TeamEvaluation Criteria: Criterion includes the ease of integration with the already in-place interface, the cost, and documentation of research.Weight: 12%

2.1.11.3 Milestone: End-Product DesignDescription: This design should include all the relevant interface designs, part specifications and coding functions.Evaluated By: Team members and faculty advisorsEvaluation Criteria: Evaluators will look at the design and review for redundancy, coding functionality and understandability, as well as a cost analysis of the parts to be used.Weight: 15%

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2.1.11.4 Milestone: End-Product ImplementationDescription: End-product design’s implementation of the end-product designEvaluated By: Team members and faculty advisorsEvaluation Criteria: Criteria to be analyzed will include the correlation between the design and implementation (that is, how closely the two match), the team’s ability to appropriately account for non-ideal conditions, and the team’s prowess at modifying the existing components with little or no variation to the existing operation.Weight: 10%

2.1.11.5 Milestone: End-Product TestingDescription: This phase is essential because a product that hasn’t been tested is not reliable. Testing will take place under a large variety of circumstances.Evaluated By: Team membersEvaluation Criteria: The approach taken with testing needs to be efficient and systematic so as to account for all variables.Weight: 15%

2.1.11.6 Milestone: End-Product DocumentationDescription: This is represented by the additions to the existing wireless testing manual. It will include a description to users on how to program the clock signal sent by the Teradyne to the interface.Evaluated By: Faculty advisorsEvaluation Criteria: This will be evaluated by checking that the modifications are seamlessly integrated into the existing document and that they are easy to read, follow, and are at a level appropriate to the users.Weight: 10%

2.1.11.7 Milestone: End-Product DemonstrationDescription: End-product and documentation are presented to anIndustrial Review PanelEvaluated By: Faculty advisor and industrial review panelEvaluation Criteria: How well the final implementation and documentation compare to the overall project definition.Weight: 12%

2.1.11.8 Milestone: Project ReportingDescription: This is the accumulation of all weekly reports, website updates, project plan, design report and the project poster.Evaluated By: Faculty advisors

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Evaluation Criteria: Reporting should be graded based on professionalism, readability, usefulness, and subject relevance.Weight: 10%

Table 2: Milestones & Grading WeightsMilestone (%)

Project Definition 16Technological Selection 12End-Product Design 15End-Product Implementation 10End-Product Testing 15End-Product Documentation 10End-Product Demonstration 12Project Reporting 10Total 100

Using the rationale in Table 1, the success of each milestone can be evaluated. The weight of each milestone can be seen in Table 2. Based on each milestone’s completion score and weight, a final project score will be given. A successful project will receive a score of no less than 80%.

2.1.12 Project Tracking ProceduresIn order to track the project success, a Gantt chart was created via Microsoft Project. This chart will be used throughout the course of the project timeline to keep track of deadlines and milestones. This chart will be updated as necessary to match the achievements of the project team. Using the updated charts, it will be easy to see where additional efforts are needed in order to keep up with deadlines. Additionally, records of expenditures, both labor and monetary, will be kept. The records will be used in the final report, as well as a measure of control as to what the end-product is and is not capable of doing.

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2.2 Statement of WorkThe statement of work outlines the tasks and subtasks needed to complete the project. This will include the objective of each step, the approach that will be taken to complete the task, and the expected results.

Task 1: Problem Definition

Objective: Understand the problem and the previous group’s work. Approach: After doing independent research on the Teradyne J750

and reading over the documentation from the May05-29 group, there will be an in-depth discussion with the project advisor where outstanding questions will be answered or the need for more resources will be identified.

Result: All team members will have a solid understanding of the problem definition.

Subtask 1a: Meet with Project Advisor Objective: To set up a weekly meeting time so the project objective

can be clarified, ongoing issues can be discussed, and the advisor can suggest additional resources.

Approach: Schedules will be compared and weekly meetings will be set with faculty advisor.

Results: A weekly meeting time will be selected.

Subtask 1b: Research Previous Documentation Objective: To understand the background material necessary for

implementing the wireless interface device for the Teradyne J750. Approach: The Teradyne J750 senior design cookbook will be read

along with the May05-26 group's final report and the J750 manual. Using the information from these sources, simple tests will be performed to ensure understanding.

Results: A necessary understanding will be obtained for further experimentation and implementation.

Subtask 1c: Schedule Teradyne Demonstration Objective: To have a certified Teradyne operator show at least one

team member the proper measurement setup and safety considerations when working with the Teradyne J750.

Approach: An email will be sent to arrange a demonstration time. After the demonstration, all team members will meet and run tests as a group to gain a uniform understanding of how to perform tests with the Teradyne J750.

Results: Meaningful measurements can then be taken using the Teradyne J750.

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Subtask 1d: Schedule Wireless Interface Demonstration Objective: To have a member of the previous design team

demonstrate how their wireless interface device was interfaced with the Teradyne J750.

Approach: An email will be sent to set up a demonstration time. During the demonstration, team members will document the steps taken to connect and configure the existing FPGA and S/R network. After the demonstration, all team members will meet and run tests as a group to gain a uniform understanding of how to using the existing FPGA and S/R network.

Results: This will lead to a better understanding of how to integrate improvements with the old design.

Task 2: Technology Selection

Objective: To identify possible technologies, standardize the selection criteria, and choose the best option

Approach: Contact electronic vendors and use available faculty for insight into unfamiliar microelectronics parts.

Results: The best implementation for recapturing the clock signal will be chosen.

Subtask 2a: Identification of Possible Technologies Objective: To understand viable options for capturing a clock signal

from the Teradyne J750. Approach: The internet and course texts will be used to research

viable clock recapturing mechanisms. Possible solutions will be discussed with faculty advisor.

Results: Knowledge of several clock recapturing mechanisms will be obtained.

Subtask 2b: Identification of Selection Criteria Objective: To come up with a set of guidelines for evaluating

alternative technologies. Approach: A set of criteria including cost and performance will be set.

A suitable cost will be considered one that is competitive with similar technology and within the allotted budget. The performance criteria is defined by its ability to meet the needs described in the functional and technology considerations found in sections 2.1.1 and 2.1.3 respectively.

Results: A standard base for comparing different alternatives will be established.

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Subtask 2c: Technology Research and Selection Objective: To better understand the technology and ultimately choose

the best option. Approach: Data will be consolidated and alternatives will be

compared using the preset criteria. Results: The best technology option will be selected based on:

Cost Chip speed Compatibility with digital I/O Ability to customize with peripheral electronics Reliability

Task 3: End- Product Design

Objective: To create a hardware schematic and an appropriate IG-XL code that will yield a responsive phase lock loop (or viable alternative) to provide a clock cycle to the wireless interface

Approach: Using previously gathered research; an efficient design will be created. Functionality will be verified with PSpice and approved by faculty advisor.

Results: A design that can be fabricated on to a printed circuit board.

Subtask 3a: Investigate Design Schematics Objective: To simulate a pll circuit that can maintain a clock signal

sent from the J750 wirelessly. Approach: Initially, data sheets from selected pll chips will be used to

determine the necessary peripheral electronics needed to implement the entire pll circuit. Next, team members will conduct transient circuit simulations that will be used to ensure that the designed pll can capture both the phase and frequency of the transmitted clock signal.

Results: A design schematic will be available to use as a blueprint for creating the circuit used on the wireless interface.

Subtask 3b: Write Code Functions with IG-XL Objective: To write a code that can be used in conjunction with the

J750 that will capture the clock signal and hold it. Approach: Team members will experiment with the IG-XL software to

develop a program that sends the training signal to the pll. In addition to this, additional training signals will need to be sent to refresh the pll’s lock. Therefore, the maximum time of the pll’s lock will need to be investigated using a bread-boarded pll circuit.

Results: A copy of code that can be used by the J750 to properly send, receive, capture, and maintain the clock signal.

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Subtask 3c: Write Necessary Switching Code Objective: The clock recapturing mechanism must be isolated when

test data is being received. Approach: The FPGA will be programmed to isolate the clock

recapturing circuitry after recognizing the termination of the preamble so that test data transmitted by the Teradyne tester will not disturb the pll’s lock.

Results: A method of isolating and reconnecting the clock recapturing circuitry.

Task 4: End-Product Implementation

Objective: To have a fully functional modification to the existing wireless interface that can be tested for production use.

Approach: Using the circuit design and written code as a guideline, the final product will be created and tested by the team. The pll will first be tested on a bread-board. These tests will determine whether or not the pll can lock onto a transmitted frequency.

Results: Hardware that can be added to the existing interface.

Subtask 4a: Hardwire Clock Recovery Circuit Objective: To successfully add the clock recovery circuit to the

existing interface Approach: Once built, the pll will be integrated into the existing setup

and serve as the clock for the FPGA. This integration will be accomplished by referring to existing documentation left by the May05 team for information on the FPGA functionality.

Results: A completed wireless setup that needs to be tested.

Subtask 4b: Program Clock Recovery Circuit Objective: Develop a code string that will ‘teach’ the wireless

interface to follow the J750’s clock signal Approach: The IG-XL language will be used to write a suitable

preamble. A suitable preamble is considered one in which the pll can lock onto and hold for a sufficient amount of time to receive test data and to send a response back to the tester.

Results: Code that will be used each time the Teradyne J750 tests digital I/O wirelessly.

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Task 5: End-Product Testing

Objective: Test and make the appropriate changes to the end-product to ensure the most reliable device is achieved.

Approach: Team members will systematically run simulations with the fully integrated wireless interface to determine points of failure and debug as needed. Test data sets with predictable outcomes will be used so that success and failure can be easily determined.

Results: A product that is ready for demonstration.

Subtask 5a: Test Planning and Development Objective: To design a plan for testing the technology implementation

chosen by the team. Approach: The team will write a detail test plan that will simulate a

variety of circumstances that the product will undergo. The test plan will include possible data sets and timing considerations the Teradyne J750 may encounter.

Results: A plan of action will be produced.

Subtask 5b: Test Execution Objective: Implement the test plan Approach: Using the Teradyne J750, the test plan will be followed by

team members to determine system limitations. Results: System limitations plotted over a variety of situations.

Subtask 5c: Test Evaluation Objective: Providing for design flaws and debugging the system Approach: Carefully review test results and analyze problem areas

that occur and must be remedied. Results: A system that is ready for demonstration.

Task 6: End-Product Documentation

Objective: To modify the existing wireless testing cookbook Approach: The latest version of the wireless testing cookbook will be

downloaded and modifications will be added to include how to set up the clock capture functions. This documentation will be submitted to either the faculty advisor or to another representative proficient in the use of the Teradyne J750 for approval.

Results: Others will be able to reproduce the efforts of the design team.

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Task 7: End-Product Demonstration

Objective: To show clients the functionality of the wireless interface. Approach: Write testing algorithms that will demonstrate functionality

under a variety of situations. These situations will demonstrate functionality under various data sets and timing considerations.

Results: The operation of the final design will proven.

Subtask 7a: Demonstration Planning Objective: To come up with a plan for demonstrating various aspects

of the final design. Approach: The team will come up with a specific set of steps that

shall demonstrate all the capabilities of the final design. These steps will be implemented with the IG-XL code. This set will be tested and the results examined to ensure that the code to be used in demonstration functions correctly.

Results: A demonstration plan will be produced.

Subtask 7b: Faculty Advisor/Industrial Review Demonstration Objective: To show faculty advisor the capabilities of the final design. Approach: The functions of the final design will be revealed in front of

the faculty advisor. Results: Others will see the various functions of the final design.

Task 8: Project Reporting

Objective: To accurately log project successes and failures and document full implementation of design so that others can reproduce the work if necessary.

Approach: Maintain a work-in-progress report to keep information up to date and to ensure completeness. As work proceeds on the project, updates will be made bi-weekly by communications coordinator to accommodate any changes made in the design.

Results: A thorough and accurate documentation of the life of the design project will be completed.

Subtask 8a: Weekly Email Reports Objective: To update faculty advisor, the client, and senior design

teachers on the progress made each week. Approach: One group member has been assigned to write and send

out the weekly emails in a standardized form. Results: All those with interest in the project will be kept up-to-date.

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Subtask 8b: Website Updates Objective: To maintain a website with the latest team progress and

documentation. Approach: Weekly emails and finalized reports will be linked on the

website. Results: All those with interest in the project will be able to see the

latest documentation and progress.

Subtask 8c: Project Plan Development Objective: To have a document that will guide the team in technology

selection, testing, and documentation. Approach: A detailed project plan will be written in a formal format.

The content of this report will reflect the decisions made in the initial meetings of the semester.

Results: This document will give the team clear goals for completing all project objectives on time.

Subtask 8d: Design Report Development Objective: To have a document that will outline the technology

selected and how the technology will be integrated with the existing wireless interface.

Approach: A detailed design report will be written in a formal format. The content of this report will reflect the decisions made regarding the technology used and its implementation

Results: This will be a formal document outlining the technology selected and how the product will be tested.

Subtask 8e: Poster Development Objective: To have information on the project in a format that is

visually pleasing and easy for others to understand. Approach: Microsoft PowerPoint will be used to design the poster. Results: A poster containing useful information for both the

professional and casual observer will be created.

Subtask 8f: Final Report Development Objective: To formally document the final results of the project. Approach: At the conclusion of this project, the project team will

create a document that contains an executive summary, results and description of the implementation used.

Results: A complete document that described the end-product.

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3. Estimated Resources and SchedulesThe following section contains personal effort requirements, resource

requirements, financial requirements, and the project schedule.

3.1 Personal Effort RequirementsThe predicted number of hours that will be spent on each task have been

put into Table 3. These hours are an estimate of the number of hours to be spent on each subtask by each individual team member throughout the project.

The table has been broken down into problem definition, technology considerations and selection, end-product design, end-product prototype implementation, end-product testing, end-product documentation, end-product demonstration, and project reporting.

The whole team will be actively involved in every stage of this project but the electrical engineers on the team will spend more time on stages that are more related to their field such as the selection and design of a suitable clock recovery circuit. The computer engineer will invest more time in the coding of the FPGA and Teradyne system as well running test procedures and maintaining the website.

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Table 3: Estimated Personal efforts

PersonnelPr

oble

m

Def

initi

on

Tech

nolo

gy

Con

side

ratio

ns

and

Sele

ctio

nEn

d-Pr

oduc

t D

esig

n

End-

Prod

uct

Prot

otyp

e Im

plem

enta

tion

End-

Prod

uct

Test

ing

End-

Prod

uct

Doc

umen

tatio

n

End-

Prod

uct

Dem

onst

ratio

n

Proj

ect

repo

rtin

g

Est.

Tota

l

Matt Dahms

12 15 60 55 40 27 15 16 240

Joe Chongo

11 17 57 65 45 30 10 17 252

Srisarath Patneedi

9 8 55 55 60 25 17 10 239

Justine Skibbe

10 13 59 55 50 26 16 18 247

Total 42 53 230 231 195 108 58 61 978

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3.2 Other Resource RequirementsThe Teradyne tester is already donated to the Iowa State Campus and is

available for use, without charge. The team will need to print its project poster and purchase a pll chip. A summary of the resources required is presented in Table 4.

Table 4: Estimated additional resourcesItem Team hours Other Hours Cost

Printing of project poster

12hrs 0hrs $65.00

Teradyne Integra J750 Test System

0hrs 0hrs Donated

PLL Chip 0hrs 0hrs $20.00

Total 12hrs 0hrs $85.00

3.3 Financial RequirementsThe cost estimate for the project can be viewed in Table 5 below. This

calculation assumes that all team members’ hourly wage is 12.00 dollars per hour.

Table 5: Estimated Project CostsItem W/O Labor With Labor

Parts and Materials:a. Printing of project poster $65.00 $65.00b. Teradyne Integra J750 Test System

Donated Donated

c. Clock Recovery Chip $20.00 $20.00Subtotal $85.00 $85.00

Labor at $12.00 per hour:a. Matthew Dahms $2,700b. Joseph Chongo $2,820c. Srisarath Patneedi $2,736d. Justine Skibbe $2,760

Subtotal $11,016Total $85.00 $11,101

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3.4 Project ScheduleFigure 5 on the following page is a Gantt chart which represents the predicted schedule through the course of the project. Each task and subtask defined earlier in the Statement of Work is delineated in the Gantt chart with expected dates. The amount of time reflected for each task takes into consideration the both the relative difficulty of the task and the relative strengths and weaknesses of the team. Table 6 shows the schedule of deliverables for the fall 2005 semester of this project.

Table 6: Schedule of DeliverablesDate Deliverable09/23/05 Project Plans Due10/11/05 Bound Project Plan Due11/11/05 Design Reports Due12/14/05 Bound Design Reports Due*TBA Project Plan and Design

Reports Posted on Website*Note: Currently, the server is not set up for students to edit sites

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Figure 3: Gantt chart

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4. Closure MaterialsThis section provides the client, faculty advisor and team member’s information and the closing summary.

4.1 Project Team InformationThis section includes the project team, client and faculty advisor contact information.

4.1.1 Client InformationDepartment of Electrical and Computer EngineeringCollege of EngineeringIowa State University2215 Coover HallAmes, IA 50011

4.1.2 Faculty Advisor InformationDr. Robert J Weber301 DurhamAmes, IA 50011Office: (515) 294-8723Fax: 515-294-1152weber@iastate.edu

4.1.3 Team Members’ InformationThe contact information for the members of the project team is shown

below in table 7.

Table 7: Contact informationMatt Dahms1400 Coconino Rd #102Ames, IA 50014(515) 450-9363mcdahms@iastate.edu

Joe Chongo3222 Lincoln Way App #7Ames, IA 50014(515) 205-2336jchongo@iastate.edu

Srisarath Patneedi103 Stanton Ave. #19Ames, IA 50014(515) 708-4560prsarath@iastate.edu

Justine Skibbe4524 Steinbeck #3Ames, IA 50014(847) 508-9479jskibbe@iastate.edu

4.2 Closing SummaryIn today’s ever expanding technology dependent society, the general movement is toward wireless devices. These devices must have their RF capabilities tested. The ECpE department at ISU has a Teradyne tester which tests digital I/O and a previous group has created the wireless interface to communicate with the tester. It does not, however, have the capability to send its clock signal wirelessly from the tester. Finishing this outstanding design implementation will make this wireless interface exclusively wireless and open up new doors of research and testing to ISU’s Teradyne users.

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4.3 References Senior Design Team Spring 2005, “Teradyne J750 Tester Cookbook.”,

February 2004. Senior Design Team May 2005, “Final Report.”, April 2005. Teradyne, “Teradyne J750 software manual”, 2003.

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