Development of RF Front-End Chip for Wireless ...yossvr0.ed.kyushu-u.ac.jp/jpn/pdf/research.pdf18...
Transcript of Development of RF Front-End Chip for Wireless ...yossvr0.ed.kyushu-u.ac.jp/jpn/pdf/research.pdf18...
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Department of Electrical and Electronic Engineering Graduate School of Information Science and Electrical Engineering
Kyushu University
Development of RF Front-End Chip for Wireless Communications
H. Kanaya, R. K. Pokharel and K. Yoshida
http://yossvr0.ed.kyushu-u.ac.jp
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Driving Force: Wireless TechnologiesWireless LAN、Cell Phone、Cordless Telephone、IC Card, ITS, DSRC
Electronic-Toll Collection System.
Cell Phone Cordless PhoneWireless LAN
発進制御機発進制御機
車線監視カメラ
車両検知器
路側無線装置(アンテナ)
路側表示器(出口)
通信開始 装置
Camera Antenna
Satellite Communications
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Silicon Sea Belt Fukuoka Project
South KoreaSouth Korea
KyushuKyushu
OkinawaOkinawa
TaiwanTaiwanHong KongHong Kong
MalaysiaMalaysia
ShanghaiShanghai
*Center of Semiconductor design.*Semiconductor Industry: Driving force for the growth.* Fukuoka is addressing to establish a center of Excellence for SoC design in this area.*Conventional Semiconductor Industry (Memory, Processor)-System LSI*System LSI is expected to generate the higher added value to the cluster of related industry.
SingaporeSingapore
Silicon Sea Belt Fukuoka Project*World production: 50%*Large consumption region
Kyushu as a Silicon Island: A global base for System LSI design.
Institute of System LSI Design Industry, Fukuoka
Silicon Sea Belt Fukuoka ProjectSilicon Sea Belt Fukuoka Project
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World Class Companies of Japan and Korea:Toshiba, Sony etc
SRP Center Building
Fukuoka Tower
ヤフードーム
Yahoo Dome
Institute of System LSI Design Industry, Fukuoka (Kyushu University:Entrepreneur Promotion Center)
Established on 2004
Fukuoka Soft Research ParkMomochi Hama District
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Foundry(TSMC, Hitachi)
Innovative Ideas:Design
EDA Tools(CAD design tools)
By VDEC
Prototype model
Testing(Underground Floor)
Patents
Research Papers (Journals and International Conferences)
VDEC:VLSI Design and Education Center (University of Tokyo)
0.18um CMOS
System LSI Research and Development
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Prof. Yoshida’s Lab Introduction
Key Words of Our Research
Miniaturization & Low Power⇒ ① SoC (System on Chip)⇒ ② Antenna
Tr. Amp. Digital Ckt.
Receiving RF Ckt
Receiving IF Ckt
Intersil 2.4GHz PCMCIA Card (PRISM 2.5)
Antennas
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Block diagram of CMOS-LSI for Wireless Communications
digital
proc.
PHY
Receiving part
Transmitting part
PLL
Mixer
Mixer
LNA
PA
A/D
D/A
VGA
Buff LPF
LPF
①1-Chip:SoC Implementation (System on Chip)
With CollaborationDirect Conversion Receiver Type
② Antenna
Research contents
VCO, PLL
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Proposal of New Design Methodologies for RF Parts
Spiral Inductors MIM Capacitors
Lump Elements Transmission line
Spice Models
Freedom of Design
Meander line
λ/4 Line
Impedance reversal Ckt.(Inverter)
Reactance Compensation ckt.
Matching Circuits
Size is about 40% and the shape can be adjusted to exploit the vacant space in the chip.
①
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G C G C L
Very small C
G C L
C
Insertion of Series C(0.09pF)
freq (2.450GHz to 2.450GHz)
S(1
,1)
freq (2.450GHz to 2.450GHz)
S(1
,1)
Insertion of LInsertion of C
High Impedance(Say:100-j1000)Ohm is matched to 50-Ohm
High L is necessary.
freq (5.000GHz to 5.000GHz)
S(1
,1)
Matching by Lumped Elements
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freq (5.000GHz to 5.000GHz)
S(1
,1)
ImpedanceReversal
G C
Compensation ckt
Δ lλ/4
A
A’
Z1, θ
G CC−
fre q (5 .00 0G Hz to 5 .0 00 G Hz)
S(1
,1)
Impedance transformationDue to K-inverters
Compensation ckt
Δ lλ/4
A
A’
Z1, θ
GC
C−K
L
-L-L
Eq. Ckt of Inverter
fre q (5.000GHz to 5.000GHz)
S(1
,1)
Presented at IEEE RFIC2006.
Theory of Matching Circuit
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Prototype Design [I]
TSMC 0.25μm CMOS (1P5M)Chip size=5mm x 5mm
LNA
DAC
PLL
VGA
BG
Mixer(Down)
Mixer+LNA
Mixer(Up)
LNAw/ CPW
LNAw/ L
CPW CPW
L L
L
L
L
L
L
L
L• LNA; Cascade, w/ CPW, w/
L• Mixer; Up, Down• Down Mx +LNA• PLL• BG• VGA• DAC• Inductor TEG• CPW TEG
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Prototype Design [II]
5mm
5mm
UWB-LNA, mixer, ADC, DAC
For MIMO-MESH Project
Mixer, VCO, 1-bit ADC
Test chips.
TSMC 0.18μm CMOS (1P6M)Chip size=5mm x 5mm
Mixer
Mixer
VCO ADC
DACLNA
VCO
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PKG Substrate
Cal. patterns
Close-up Figure
TEG Chip Photo
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Lab Facilities of Testing
Cascade Microtech
Air Coplanar Probe
Spiral inductor
LSI chipProbe
50Ω cable
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Results [1]
•Power Amp. (IEEE .11b)•LNA (UWB)•VCO & DCO (IEEE .11a)•LNA + Mixer (IEEE .11b)•Ring Oscillator
TSMC:0.35um Bi-CMOS, 0.25um CMOS & 0.18um CMOS
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Power Amp.
-25
-20
-15
-10
-5
0
5
10
15
1 2 3 4 5 6 7 8
S11
S21
S22
S parameter [dB]
Freq [GHz]
10.495 [dB]
1.05
[mm
]
2.38 [mm]
Input Match Output match
TSMC0.35μm Bi-CMOS process
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Ultra wideband (UWB) Low noise Amp. (LNA)
Chip photo of the designed UWB LNA in 0.18um CMOS.
1mm
0.7mm
RF probe pads
RF probe pads
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Reference S21 NF(dB) S11 (dB) Freq. (GHz) IIP3 (dBm) Technology
JSSC[1] 9.7~7 4.5~5.1 <-11 3.1~10.6 -6.2 0.18µm CMOS
JSSC [2] 13 3.3 (max 6.5) <-7 2~10 -7 0.18µm BiCMOS
Ref. [3] 9.5 5 (max 5.6) <-10 3-11 -13 0.18µm CMOS
This work(Post-layout)
16.5(flat)
<3.7(flat)
<-9 3.1~10.6 -80.18µm CMOS
-> Presented at IEEJ Analog VLSI symposium, Aug, 2008.
Measurement results
BW 7GHz≅G
ain,
S[2
1] (d
B)
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VCO (Voltage controlled Osc.) with TML
4.8
5
5.2
5.4
5.6
5.8
6
6.2
6.4
0 0.4 0.8 1.2 1.6
Freq
uenc
y (G
Hz)
DC Control Voltage (V)
TML VCO
LC VCO
100μm
TML VCO= -112dBc/Hz @1MHzLC VCO= -110dBc/Hz @1MHz
TSMC0.18μm CMOS process
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LC-DCO (Digitally controlled OSC)
4.5
4.6
4.7
4.8
4.9
5
5.1
0 200 400 600 800 1000
Freq
uenc
y (G
Hz)
control word (10bit)
V1
V2
V3
V4
V7
V5
V6
C C 2C2C4C 4C
8C 8C
Cvar Cvar
Cvar Cvar
CvarCvar
Cvar
Cvar
Cvar
Cvar
CvarCvar
CvarCvar
V8
V9
V10
32C 16C16C 64C64C 32C
TML Capacitor
TSMC0.18μm CMOS process
On-Off
LC VCO= -119dBc/Hz @1MHz
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LNACPWMatching circuit
(50Ω)
Down conversion mixer
VCOLayout (LNA + Mixer)
Matching circuit
Size
480μm×250μm
TML
600μm×300μm
Lumped element
(約14.0nH @2.45GHz )
RF_IN
Chip Size3.3mm×2.0mm
LO
LO
LNA + Mixer (Down converter)
CPWMatching circuit
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LNA + Mixer (Down converter)
Mixer LNA
K-inverters andCPW lines
Input-matching circuit
Matching circuit between LNA and mixer
Mixer LNAInput-matching circuit
Matching circuit between LNA and mixer
-80
-60
-40
-20
0
20
40
60
80
1 2 3 4
Inpu
t Im
peda
nce
[ O
hm]
Frequency [ GHz ]
SimulationMeasured
Real parts
Imaginary parts
Input Impedance
Output by Oscilloscope(Base band freq.=10MHz)
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Ring-Oscillator
WLAN(.11a,.11b), WCDMA, GPS, PHS, GSM, IMT2000 …
●Reconfigureable RF circuit.●Multi-standard systems in one terminal.
MobileTerminal
Tel.
WLAN
Bluetooth
TV
RFID
UWB
GPSFM
DTV
Demand of Wideband Systems
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I1
I3 I4
I2Q270
Q90
Q180
Q0Vdd
VssW180
Q90Q180
Q270
M4
M3
M1
M2
Additional transition-assistance pair
pMOS
nMOS
Proposed Quadrature Ring OscillatorChip photo
TSMC 0.18um CMOS Process
Size:0.30 mm2 with bonding pads.Size: 0.01 mm2 without bonding pads.
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Measurement results
Time-Domain Tuning Range
Tuning Sensitivity = 2.9 MHz/mVTuning range = 1.7 GHz ~5.5 GHzFOM= -162.2 dBc/Hz
Figure of Merit: ⎟⎠⎞
⎜⎝⎛++⎟
⎟⎠
⎞⎜⎜⎝
⎛−=
001.0log10log20 diss
off
osc PPNFFFOM
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Baseband processing unitBaseband processing unit
DSPDSP RF Front endRF Front end
Key word: RFIC (DigitallyKey word: RFIC (Digitally--assisted assisted RF/Analog)RF/Analog)
LNA, Mixer, PA,
PLL, VCO
ADC, DAC
Digital techniques: a New Concept in RF circuit design:Digitally-assisted RF/Analog
Wireless System LSI
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Development of Miniaturized Integrated Antennas
5cm
Intersil 2.4GHz PCMCIA Card (PRISM 2.5)
Antenna
LSI Small size, thinner and one-sided directional antennas are necessary!
②
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Antenna Applications
•One-sided directional antenna300MHz, UHF, 2.4GHz (.11b), MIMO (.11a), UWB
•Electrically small antenna with matching circuitUHF, 2.4GHz, 5GHz
•Dual band antennaPDC + 3G (800MHz + 2GHz)
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θ
Z
X
Y
φ
Forward
Back
Lfront
Top layer Bottom layer
E- fieldNear field
φ =0°
φ =90°
θZ
Simulated field pattern and radiation pattern of the one-sided directional antenna
Forward
Back
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Thickness of the substratet [mm]
1.6 0.8 0.4
One-sided slot Gain[dBi]
Gain[dBi]
1.177 0.81 -1.516
Patch antenna 1.254 -1.057 -4.145
By 3D-EM Simulation
tt tt
○
×
….advantage for multiplayer MMIC circuit.
Advantages of Proposed Theory:Gain can be realizable at thinner Substrate
F
B
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Small Radiation ResistanceNarrow bandwidth
Impedance Matching
Design of Bandwidth
An antenna that dimension is much smaller than quarter wavelength…
Sensitive to the conductor resistance
One-Sided Directional Antenna
ProposedAntenna
integrates
⇒Antenna length < λ/4
Electrically small antenna (ESA)
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32
Antenna Fabrication and Measurement System
PCB
PCB Makers (MITS Co.)
High-frequency Milling Cutter
Vector Network Analyzer:HP8722C
AntennaMMCX-SMAConnector
VNA
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33
Photograph of the ESAs
Size comparison of the antennas
Enlargement of the ESAs
standard slot dipole antenna (size:74.0mm×24.0mm,gain:3.92dBi)
ESA1
ESA2
(unit : mm)
J-inverter J-inverter
G GS
MMCX Connector(50Ω)
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-50
-40
-30
-20
-10
0
2 2.2 2.4 2.6 2.8 3
Ret
urn
Loss
[dB]
Frequency [GHz]
Measured
EM Sim.
Band widthJ-Inverter
(Inter digital gap)
Photographs of the antenna19.3mm
Experimental results of the one-sided directional ESA with CPW matching circuit
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35
Antenna
PC
Reader-Writer
RF-ID Card @2.45GHz (IMS band)
Experimental results of the one-sided directional ESA with CPW matching circuit
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36
In the anechoic chamber
Test antenna
Transmitting
Receiving
Turn table
Setup of Radiation Pattern Measurement
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37
Patch antenna #245mm□×t1.6mm
ESA39×19×t0.8mm
Patch antenna #175mm□×t5mm
Comparison of the sizes of the one-sided directional antenna
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38
Patch #2 ESAPatch #10
50
100
150
200
250
300
350
FrontBack
Com
mun
icat
ion
dist
ance
(mm
)
102
103
104
105
Antenna size [m
m3]
81% reduced !
GtGrWtd
Wr ⎟⎠⎞
⎜⎝⎛=
πλ
4
2
TX RX
dGt Gr
Power received by the RX antenna
Friis' Transmission Formula
Measured communication distance and antenna size of the patch antenna and ESA
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39
UWB High Band one-sided directional antenna
y
-35
-30
-25
-20
-15
-10
-5
0
6.5 7 7.5 8 8.5 9 9.5 10 10.5
Ret
urn
Loss
[dB
]
Frequency [GHz]
Exp.
Sim.
Three resonance—broad band
7.25GHz 8.25GHz 9.25GHz
θφ =0°
φ =90°
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40
UHF visiting-card size one-sided directional antenna
-30
-25
-20
-15
-10
-5
0
800 850 900 950 1000
|S11
| (dB
)
Frequency (MHz)
-50
-25
0
25
50
75
800 850 900 950 1000
Re [Zin]Im [Zin]
Inpu
t Im
peda
nce
(Ω)
Frequency (MHz)
x-z面
y-z面 F/B:8dB
y
(Sim.)
Human body or metal surface like auto mobile.
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41
Fix
Large
Small
Portability
・B社・T社 ・S
社
★MIMO-MESH
・Sensor node
★Pico-MESH
Conventional MESH Device
New national project (PICO, MIMO) MESH Network
MESH Point
One-sided directional planar antennas
MIMO-MESH, Pico-MESH
More than 10kgLimitation= 2~3 hubs
RF front end + IP Core
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42
New Antenna22mm×28mm5dBi (One-sided directional)
MESH Antenna @5GHz
X
Z
Y
Z
XY
ConventionalH:15.7mm×D:1.1mm5dBi
F/B:10 dB
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43
Node A Node B
点線上でノード B の位置を変化
100m
42m
Ath0 : 192.168.0.*/24
Ath1 : 192.168.1.*/24
Ath0 : 192.168.0.2
Ath1 : 192.168.1.2
Ath0 : 192.168.0.1
Ath1 : 192.168.1.1
Node A Node B
Node PhotoNode
Field: Building
※Speed:36Mbps, Frequency:52ch(5.26GHz), Amp. output:17dBm(50mW)
W2,8F
←Scan→
Measurement system of communication distance
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0
5
10
15
20
25
0 50 100 150 200 250
スル
ープ
ット[M
bps]
ノード間の距離[m]
金谷研アンテナ put
金谷研アンテナ get
黒アンテナ put
黒アンテナ get
Our antenna: putOur antenna: get
Conventional: getConventional: put
communication distance > 200m
Measured communication distanceTh
roug
h pu
t [M
bps]
Node distance [m]
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45
Back bone network
Wire
Node
Host
Wireless Line
PC
Internet phone
Wireless Line
Ant
Mounted 6 plates
Antenna plateCase
A small antenna is necessary !!
・Small size・One sided directional・Wide band (4.9GHz~5.7GHz)
MIMO-MESH Point
![Page 46: Development of RF Front-End Chip for Wireless ...yossvr0.ed.kyushu-u.ac.jp/jpn/pdf/research.pdf18 Reference S21 NF(dB) S11 (dB) Freq. (GHz) IIP3 (dBm) Technology JSSC[1] 9.7~7 4.5~5.1](https://reader033.fdocuments.net/reader033/viewer/2022050414/5f8a7663cf6d1b67554d1b22/html5/thumbnails/46.jpg)
46
9.4cm
5.8cm
A1 A2 A4A3
A5 A6 A7 A8
Antenna plate
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47Thank you for your Attention!
Conclusion
RF COMOS Front-end (RFIC)Planer type small antenna
Detail:
Applications:3G, .11a,b &g,MIMO,PICO and UWB
RFIC Japan