Development of Modem Core Structure and Technologies for ... · Development of Modem Core Structure...
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Development of Modem Core Structure and Technologies for DVB-RCS2 Return Link Xilinx Estonia OÜ I www. xilinx.com Project goal Actions completed Results Contact The objective of the project was to perform system analysis of DVB-RCS2 Return Link, define modem architecture, perform trade-off analysis of technologies used in functional blocks within the modem, analyze and design modulator and demodulator algorithms, and implement these algorithms in Matlab environment. The results of the systems design would contribute to preparing the future product development of DVB-S2 return link modem. The system requirement speci fication document describes the system requirement and speci fication of the DVB-RCS-2 Return Link Modem. The functional design document describes the system architecture and each functional block in transmitter and receiver. The Matlab models of the modem simulate the system behavior of the functional blocks and provide indications of the performance of the modem to be built. Therefore, trade-offs of complexity and performance can be evaluated without time-consuming rebuild of the hardware. Various algorithms for each functional block are evaluated and tradeoff analysis was conducted. The synchronization mechanism includes symbol synchronization, frame synchronization, and carrier synchronization. The soft demapper produces Log-Likehood Ratio (LLR) efficiently using the MAX algorithm. The Turbo decode employs the backward-forward algorithm to take advantage of the tail-biting property of the DVB-RCS2 system Turbo code. A modem architecture with good performance and reasonable complexity is presented. Work packages • Systems Analysis and Design: design DVB-RCS2 modem architecture and generate its requirements in order to set the baseline on the development. o Perform systems analysis and define modem (modulator and demodulator) architecture o Define minimum performance target for the phy- sical layer of the target application profile, such as modulation scheme, waveforms, synchronization, and etc. o Perform trade-offs of technologies for functional blocks in the architecture o Select candidate technologies of the functional blocks and perform their top-level design, inclu- ding their structures o Generate systems requirements of the modem system and the functional blocks o Document systems requirements specifications of the modem In this task you should define some target performance objectives • Functional Design and Implementation: develop and design algorithms for functional blocks in modem, based on the systems requirements specifications, and implement them in Matlab. Particularly, main emphasis is on development of functional blocks in the demodulator. o Analyse and design algorithms for functions in the modulator and demodulator o Develop algorithms for functions in the demodu- lator, including Turbo coder, Frame synchroniza- tion, Carrier recovery, Symbol synchronization o Implement modulator and demodulator algo- rithms in Matlab • Integration and Simulator Development: integrate Matlab algorithms program codes to construct a mo- dem simulator at system level. Also, integration of the modem simulator with satellite channel is targeted in order to construct a full RCS2 system simulator o Integrate modulator algorithms in Matlab to form a modulator-level simulator and verify o Integrate demodulator algorithms in Matlab to form a demodulator-level simulator and verify o Integrate modulator and demodulator simulators to form a modem-level simulator and verify o Integrate satellite channel and RF subsystem model with the modem simulator o Construct raw and RCS2 IP data frames to use to verify the simulator o Validate the system simulator with the construc- ted data frames • Performance Evaluation: evaluate and analyze per- formance of the developed modem and produce final project report o Perform tests for the modem performance evalu- ation to verify the minimum performance target o Analyze technical factors for increasing the RCS2 return link performance and efficiency in through- put, modulation scheme, waveforms, synchroni- zation, and others pertinent to the system perfor- mance DVB-RCS2 transmitter is illustrated in Fig 1. The payload is randomized by the Energy Dispersal block, and then 32-bit Cyclic Redundancy Check (CRC32) is appended. DVB-RCS2 Turbo encoder adds double binary Circular Recursive Systematic Convolutional (CRSC) code that adopts the tail biting technique. Symbol Insertion block adds the preamble, pilots, and post-amble. The Linear Modulation (LM) mapper maps the data into proper sig- nal constellation. The Pulse Shaping block performs the Square Root Raised Cosine (SRRC) filtering for spectrum mask compliance. DVB-RCS2 receiver is illustrated in Fig 2. The received baseband (BB) signal is process by the Symbol Sync to find the symbol boundary. The Matched Filter block is to perform the Square Root Raised Cosine (SRRC) filte- ring. Carrier Sync block removes any residual frequency offset. Frame Sync block is to find the boundary of the preamble and payload. Digital Automatic Gain Control (DAGC) controls the magnitude of the signal entering the Demapper. The Demapper converts the complex signal to soft bits Log-Likelihood Ratio (LLR). DVB-RCS2 Turbo Decoder implements parallel architecture to decode the payload. CRC32 block checks the integrity of the pay- load and the Descrambler removes the Energy Dispersal effect. Figure 1: DVB-RCS2 return link TC-LM user traffic baseband TX Architecture Figure 2: DVB-RCS2 return link TC-LM user traffic baseband RX Architecture Figure 3: 8 PSK Constellations Figure 4: BER vs SNR in AWGN Tarmo Pihl, Wireless Marketing Director; [email protected] S 5 Q S 4 S 6 S 7 S 3 S 2 S 0 S 1 100 8PSK π/8 r=1 110 111 011 010 101 001 000 10 -1 10 -2 10 -3 10 -4 10 -5 0 2 4 6 8 10 12 14 16 18 QPSK 1/3 123B QPSK 2/3 264B QPSK 2/3 355B QPSK 3/4 400B QPSK 3/4 539B QPSK 5/6 599B 10 -6 Project team: Alfred Lin - Sr Systems Engineer Estonian Space Of fice www.eas.ee/space European Space Agency
Transcript of Development of Modem Core Structure and Technologies for ... · Development of Modem Core Structure...
Development of Modem Core Structure and Technologies for DVB-RCS2 Return Link
Xilinx Estonia OÜ I www. xilinx.com
Project goal
Actions completed
Results
Contact
The objective of the project was to perform system analysis of DVB-RCS2 Return Link, defi ne modem architecture, perform trade-off analysis of technologies used in functional blocks within the modem, analyze and design modulator and demodulator algorithms, and implement these algorithms in Matlab environment. The results of the systems design would contribute to preparing the future product development of DVB-S2 return link modem.
The system requirement specifi cation document describes the system requirement and specifi cation of the DVB-RCS-2 Return Link Modem. The functional design document describes the system architecture and each functional block in transmitter and receiver. The Matlab models of the modem simulate the system behavior of the functional blocks and provide indications of the performance of the modem to be built. Therefore, trade-off s of complexity and performance can be evaluated without time-consuming rebuild of the hardware.
Various algorithms for each functional block are evaluated and tradeoff analysis was conducted. The synchronization mechanism includes symbol synchronization, frame synchronization, and carrier synchronization. The soft demapper produces Log-Likehood Ratio (LLR) effi ciently using the MAX algorithm. The Turbo decode employs the backward-forward algorithm to take advantage of the tail-biting property of the DVB-RCS2 system Turbo code. A modem architecture with good performance and reasonable complexity is presented.
Work packages
• Systems Analysis and Design: design DVB-RCS2 modem architecture and generate its requirements in order to set the baseline on the development.o Perform systems analysis and defi ne modem
(modulator and demodulator) architectureo Defi ne minimum performance target for the phy-
sical layer of the target application profi le, such as modulation scheme, waveforms, synchronization, and etc.
o Perform trade-off s of technologies for functional blocks in the architecture
o Select candidate technologies of the functional blocks and perform their top-level design, inclu-ding their structures
o Generate systems requirements of the modem system and the functional blocks
o Document systems requirements specifi cations of the modem In this task you should defi ne some target performance objectives
• Functional Design and Implementation: develop and design algorithms for functional blocks in modem, based on the systems requirements specifi cations, and implement them in Matlab. Particularly, main emphasis is on development of functional blocks in the demodulator.o Analyse and design algorithms for functions in the
modulator and demodulatoro Develop algorithms for functions in the demodu-
lator, including Turbo coder, Frame synchroniza-tion, Carrier recovery, Symbol synchronization
o Implement modulator and demodulator algo-rithms in Matlab
• Integration and Simulator Development: integrate Matlab algorithms program codes to construct a mo-dem simulator at system level. Also, integration of the modem simulator with satellite channel is targeted in order to construct a full RCS2 system simulatoro Integrate modulator algorithms in Matlab to form
a modulator-level simulator and verify o Integrate demodulator algorithms in Matlab to
form a demodulator-level simulator and verify o Integrate modulator and demodulator simulators
to form a modem-level simulator and verify o Integrate satellite channel and RF subsystem
model with the modem simulator
o Construct raw and RCS2 IP data frames to use to verify the simulator
o Validate the system simulator with the construc-ted data frames
• Performance Evaluation: evaluate and analyze per-formance of the developed modem and produce fi nal project reporto Perform tests for the modem performance evalu-
ation to verify the minimum performance target o Analyze technical factors for increasing the RCS2
return link performance and effi ciency in through-put, modulation scheme, waveforms, synchroni-zation, and others pertinent to the system perfor-mance
DVB-RCS2 transmitter is illustrated in Fig 1. The payload is randomized by the Energy Dispersal block, and then 32-bit Cyclic Redundancy Check (CRC32) is appended. DVB-RCS2 Turbo encoder adds double binary Circular Recursive Systematic Convolutional (CRSC) code that adopts the tail biting technique. Symbol Insertion block adds the preamble, pilots, and post-amble. The Linear Modulation (LM) mapper maps the data into proper sig-nal constellation. The Pulse Shaping block performs the Square Root Raised Cosine (SRRC) fi ltering for spectrum mask compliance.
DVB-RCS2 receiver is illustrated in Fig 2. The received baseband (BB) signal is process by the Symbol Sync to fi nd the symbol boundary. The Matched Filter block is to perform the Square Root Raised Cosine (SRRC) fi lte-ring. Carrier Sync block removes any residual frequency off set. Frame Sync block is to fi nd the boundary of the preamble and payload. Digital Automatic Gain Control (DAGC) controls the magnitude of the signal entering the Demapper. The Demapper converts the complex signal to soft bits Log-Likelihood Ratio (LLR). DVB-RCS2 Turbo Decoder implements parallel architecture to decode the payload. CRC32 block checks the integrity of the pay-load and the Descrambler removes the Energy Dispersal eff ect.
Figure 1: DVB-RCS2 return link TC-LM user traffi c baseband TX Architecture
Figure 2: DVB-RCS2 return link TC-LM user traffi c baseband RX Architecture
Figure 3: 8 PSK Constellations Figure 4: BER vs SNR in AWGN
Tarmo Pihl, Wireless Marketing Director; [email protected]
S5
Q
S4
S6
S7 S3
S2
S0
S1
100
8PSK
π/8
r=1110
111011
010
101 001
000
10-1
10-2
10-3
10-4
10-5
0 2 4 6 8 10 12 14 16 18
QPSK 1/3 123B QPSK 2/3 264BQPSK 2/3 355BQPSK 3/4 400BQPSK 3/4 539BQPSK 5/6 599B
10-6Project team:Alfred Lin - Sr Systems Engineer
Estonian Space Offi cewww.eas.ee/space
European Space Agency
