Development of CCDs and Relevant Electronics for the X-ray CCD camera of the MAXI

Experiment onboard the International Space Station

Osaka UniversityE. Miyata, C. Natsukari, T. Kamazuka, H. Kouno, H. Tsunemi

NASDA (National Space Agency of Japan) M. Matsuoka, H. Tomida, S. Ueno, K. Hamaguchi

Graduate University for Advanced StudiesI. Tanaka

OUTLINE• International Space Station• MAXI : Monitor of All-sky X-ray Image• X-ray CCD Camera onboard MAXI --- SSC• Engineering Models of SSC components• Development of Electronics for SSC• Summary

International Space Station

is now constructing

mainly by USA, Russia, ESA, Japan, Canada

will be completed in 2006

go around the Earth in 90 min

International Space Station (ISS)

©NASA/NASDA

MAXI : Monitor of All-Sky X-ray Image

• mission to monitor the all-sky in X-ray wave length from ISS

• selected as an early payload of the JEM Exposed Facility

• will be launched in 2005 by HIIA rocket

• carry two sensors– Gas Slit Camera (GSC)

poster 4497-18– Solid-state Slit Camera

(SSC)• mission life ~ 2yr

Grapple Fixture for a robot armGrapple Fixture for a robot armRadiator for X-ray CCDsRadiator for X-ray CCDs

Optical Star SensorOptical Star Sensor

Solid-state SlitSolid-state SlitCameras (SSC)Cameras (SSC)= X-ray CCD= X-ray CCD camerascamerasGas Slit Cameras (GSC)Gas Slit Cameras (GSC)

= X-ray gas counter cameras= X-ray gas counter cameras

ElectronicsElectronics

180180cmcm

8080cmcm

100100cmcm

Total weight: 500 kgTotal weight: 500 kg

SSCSolid-state Slit CameraNo of chip 16chips/SSC

Energy band 　　　 0.5-10 keV

Sensitivity 5.6mCrab/day

Effective area 100cm2/SSC

FOV 1x90

360x90 (1 orbit)

Pointing accuracy 0.1x0.1

Clocking Parallel-summing

(Fast@ASCA)

R3081

Cooling System for SSC

• Two passive radiators• Loop heat pipe is attached

– function as a heat switch

• Operating temperature of CCD:– —100~ — 70 oC at BOL– —85~ — 50 oC at EOL (Peltier cooler is also

used)

EM of AE for SSC• There are several techniques to process the CCD video signal• We have developed

– correlated double sampling– delay circuit (used in ASCA/SIS)– integration circuit (used in Chandra/ACIS, HETE2/SXC,

Astro-E/XIS)• We selected the integration circuit for the flight model

EM of SSC Camera

EM of CCD• fabricated by Hamamatsu Photonics

K.K.• 1024x1024 pixels of 24 µm• two phase gate structure• 3-side buttable• single stage Peltier cooler

– same size as the CCD– reduce the shock stress

• coated by 2000Å Al• fabricated sample chips both from

– high-resistivity epitaxial wafer– bulk wafer (+ n+ layer)

• To improve the radiation hardness– using Si3N4 gate– having notch structure– having charge injection gate

Radiation Damage Test with Proton

• We are now performing the radiation damage test using the Van-de-Graaff accelerator in our faculty• We will verify our improvements and test the charge injection method to recover

100 keV 2MeV 4MeV

To Evaluate & Maximizethe CCD Performance

We need to optimize

clocking pattern and clocking voltages

(high energy resolution, high Q.E. etc.)

clocking pattern

to recover the performance for

a degraded chip due to radiation damage

(charge injection method etc.)

We need highly flexible CCD driver system !

Previous Driver System

D I/O

AnalogSwitch

CCD

Use DAC to determine high & low levels for each clock

Use analog switch to select the voltage levels

DACAnalogSwitch

AnalogSwitch

AnalogSwitch

OPamp

OPamp

OPamp

OPamp

X Low flexibility

Δ Relatively complex circuit

O Small number of digital I/O pins

high

highlow

low

AnalogSwitch

New Concept: Fast DAC & Fast FPGA

o High flexibilities

o Relatively simple circuit

x Large number of digital I/O pins

CCD

512 KbyteSram

FPGA

DACOPamp

New Generation Driver System

E. Miyata et al. NIM (2001)

Sample Waveform

E-NA System with SSCE Integration Board

55Fe Spectrum (ASCA grades 02346)

Energy [keV]

Counts

readout noise 3e- rms

55Fe Spectrum (Log Scaled)

Energy [keV]

Counts

Summary of EM CCDs

• Achieve 40 µm for epitaxial CCD and bulk CCDs in low dark current mode (voltage of vertical transfer gate is 4 V)

• To achieve thick depletion layer and good energy resolution,epitaxial4 or bulk3 chips will be selected for flight devices

Q.E. (grade02346) @5.9 keV [%]

DepletionLayer [µm]

ΔE (grade 02346) [eV]

@5.9keV

epitaxial1

12±0.7 4 142±5.8

epitaxial2

37±0.8 14 152±3.1

epitaxial3

56±1.0 25 143±2.2

epitaxial4

73±1.5 42 149±1.9

bulk1 79±1.6 48 208±4.7bulk2 57±1.2 27 143±3.2bulk3 71±1.5 40 162±2.5

Summary• We have developed the engineering models for

– SSC CCDs– SSC analog electronics– SSC digital electronics– SSC cooling systemAll components function well.We are now ready to construct the flight models.

• We have developed the DAQ system with low-noise, high flexible, high speed– achieve 3e- rms readout noise including CCD– achieve ~40 µm depletion layer in low dark

mode

Near Future Plan

• Radiation damage test is now performing

• Flight design will be fixed in this summer

• Thermal and mechanical test will be performed in the end of this year

SSC… First X-ray CCD Camera

All Fabricated in Japan• We, the Japanese X-ray CCD team, have developed (just started to construct) X-ray CCD camera onboard– ASCA (SIS)– ((( Astro-E ))) ((((( XIS )))))– Astro-E II ( XIS II )

• We developed neither CCD chip nor analog electronics• We like and need to develop all for X-ray CCD for the

future mission (carry CCD, I do hope !)

• This is the first time to develop all for X-ray CCD camera

• For success of our mission, we need to developCCDs having high Q.E. and high E/EAE having low noise capabilityAE to maximize the CCD performance