Development of a Directional Definite-Time …868398/FULLTEXT01.pdfDEGREE PROJECT, IN ELECTRIC POWER...

DEGREE PROJECT, IN , SECOND LEVELELECTRIC POWER ENGINEERINGSTOCKHOLM, SWEDEN 2015

Development of a DirectionalDefinite-Time Overcurrent and EarthFault Protection based on COTSComponents

FABIAN HOHN

KTH ROYAL INSTITUTE OF TECHNOLOGY

ELECTRICAL ENGINEERING

Abstract

Manufactures of power system products face an increased pressure to reduce the time to

market of their development process without compromising quality. Moreover the oper-

ation of power systems needs to be performed in a secure and reliable manner. One of

the key systems to guarantee those stringent requirements is the protection system. The

objective of this Master’s thesis is the development of a protection system, which solidly

relies on Commerciall-o↵-the-Shelf (COTS) components as well as on the developed pro-

tection functions. Thereby it is shown that the tight cost requirements can be fulfilled

without jeopardising the reliability and security performance.

This project comprises the development of a definite-time directional overcurrent and

earth fault protection. The applied development process is based on a model-based-design

approach, which comprises the definition of the requirements, the design phase, the im-

plementation on the target system and the test phase. As part of this thesis each stage

is described and executed. Moreover MATLAB/Simulink was used as development en-

vironment, since it perfectly supports the model-based-design approach. The considered

functional requirements are mostly based on the standard IEC 60255-151. The developed

protection algorithm runs on a realtime linux system and the interface to the process is

based on the EtherCAT protocol and their corresponding I/O modules. Lastly, the test

phase is based on a functional performance test, a type test according to IEC 60255-151,

a longterm test and an evaluation of the EMC performance of the used I/O modules.

The results of the type tests showed that a IEC 60255-151 compliant solution is yield.

Moreover the functional performance test proofed that the developed protection function

operate as intended for various fault scenarios. Lastly, the realtime performance of pro-

tection system has to be further analysed and adapted in order to achieve satisfactory

behaviour.

i

Abstrakt

Tillverkare av elkraftskomponenter star infor okade utmaningar for att minska tiden for

produktutveckling utan att kompromissa med kvaliten.

Utmaningen blir storre nar ett sakert och tillforlitligt elkraftsystem maste uppfyllas. Ett

av de viktigaste systemen for att garantera dessa krav ar skyddssystemet. Syftet med

detta examensarbete kommer foljaktligen bli att utveckla ett skyddssystem som forlitar

sig pa Commerciall-o↵-the-Shelf (COTS) komponenter och som dessutom tar hansyn till

skyddssystems funktioner. Fran detta skyddssystem kan det pavisas att det ar mojligt att

under ett begransat tidsspann uppfylla marknadens krav utan att aventyra tillforlitligheten

och sakerheten.

Detta projekt innefattar utvecklingen av ett riktat overstromsskydd och ett jordfelsskydd.

Utvecklingsprocess bygger paen modellbaserad design, som omfattar faserna prestandakrav,

konstruktionsfas, implementering och prestandatest av systemet. Som en del av detta ar-

bete kommer varje steg beskrivas utforligt och genomforas. MATLAB/Simulink anvandes

som utvecklingsverktyg, eftersom den har stod for modellbaserad design. De prestandakrav

som anses ar for det mesta baserad pa IEC 60255-151 standarden. Den utvecklade sky-

ddsalgoritmen implementerat i ett Linux system i realtid, granssnittet for processen ar

baserad pa EtherCAT protokollet och deras korresponderade I/O moduler. Testfasen A¤r

indelat i fyra olika tester kallade prestandatest, typtest enligt IEC 60255-151, realtidstest

och utvardering av EMC prestandan av de anvanda I/O modulerna.

Resultatet av prestandatest visar att en IEC 60255-151 kompatibel losningen gar att

uppna. Dessutom visar prestandatestet att de utvecklade skyddsfunktionerna funger-

ade som planerat for olika fel scenarion. Realtidsprestanda av skyddssystemet behover

emellertid ytterligare analyseras och anpassas for att uppnatillfredsstallande resultat.

ii

Acknowledgements

There were many people, which have been of great support to me during the planning

and execution of this Master’s thesis project. Therefore I would like to express my sincere

gratitude to them. The thesis has been conducted in collaboration with ABB Substation

Automation Products in Vasteras as well as with the Industrial Information and Control

Systems department at KTH in Stockholm.

Johan Salj has been my supervisor at ABB. He has supported me with technical guidance

throughout the project. In addition, I am very thankful to him for sharing his broad ex-

pertise. Moreover, I want to thank Henrik Backstrand. In his capacity as a line manager

he help me with all administration matters as well as with the arranging of the required

technical equipment.

Furthermore, my supervisor from KTH Nicholas Honeth has been of superb help to me.

Due to his extraordinary commitment to the course ”Advanced Computer Applications in

Power Systems”, I became very well acquainted with the Linux operating system. During

my thesis he has been given me useful guidance for the execution of the project. My

professor Lars Nordstrom was acting as the responsible examiner of the thesis. I would

like to thank him for given me this great opportunity to conduct the thesis with ABB and

for his valuable advice and support.

Lastly, I would like to thank all my colleagues from ABB and the sta↵ from the ICS

department for supporting and encouraging me.

iii

Contents

Abstract i

Abstract ii

Acknowledgements iii

List of Figures viii

List of Tables x

Nomenclature xi

1 Introduction 1

1.1 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Background 3

2.1 Commercial-o↵-the-shelf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Power System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2.1 General objectives of protection systems . . . . . . . . . . . . . . . . 4

2.2.2 Setups of Protection Systems . . . . . . . . . . . . . . . . . . . . . . 5

2.2.3 Fault current calculation . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.4 System Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Real-Time Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.2 Process, Thread & Task . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 Scheduling policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.4 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.1 EtherCAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.4.2 IEC 61850-9-2 & 61850-9-2LE . . . . . . . . . . . . . . . . . . . . . . 20

2.5 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

iv

3 Methodology 24

3.1 Model-based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2 Requirements for protection relays . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.1 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.2 Environmental requirements . . . . . . . . . . . . . . . . . . . . . . . 28

3.3 Selection of communication solution . . . . . . . . . . . . . . . . . . . . . . 32

3.4 Selection of real-time system . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.2 Runtime Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5 Specified development procedure . . . . . . . . . . . . . . . . . . . . . . . . 37

4 Implementation 39

4.1 Architecture of Protection System . . . . . . . . . . . . . . . . . . . . . . . 39

4.2 Protection Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2.2 Signal Processing Element . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.3 Definite-time Directional Overcurrent Protection - PDOC . . . . . . 45

4.2.4 Definite-time Directional Earth Fault Protection - PDEF . . . . . . 50

4.2.5 Phase Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.6 Trip Element - PTRC . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.7 EtherCAT-Communication . . . . . . . . . . . . . . . . . . . . . . . 58

4.3 Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.3.1 Kernel configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.3.2 EtherCAT-Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Evaluation 63

5.1 Evaluation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 Functional Performance Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.2.1 Model- & Software-in-the-Loop . . . . . . . . . . . . . . . . . . . . . 64

5.2.2 Hardware-in-the-Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3 Type Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.3.1 Accuracy of pick-up and drop-o↵ value . . . . . . . . . . . . . . . . . 83

5.3.2 Determination of reset ratio . . . . . . . . . . . . . . . . . . . . . . . 84

5.3.3 Steady state errors of start and operate time . . . . . . . . . . . . . 85

5.3.4 Steady state errors of disengaging and reset time . . . . . . . . . . . 87

5.3.5 Transient overreach . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.3.6 Overshoot time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3.7 Accuracy of directional element . . . . . . . . . . . . . . . . . . . . . 91

5.4 Evaluation of realtime performance . . . . . . . . . . . . . . . . . . . . . . . 92

5.4.1 Distribution of start time . . . . . . . . . . . . . . . . . . . . . . . . 93

v

5.4.2 Distribution of operate time . . . . . . . . . . . . . . . . . . . . . . . 94

5.5 Environmental compatibility of I/O modules . . . . . . . . . . . . . . . . . 96

6 Conclusion and Discussion 100

6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Bibliography 101

Appendix 106

vi

List of Figures

2.1 Three important knowledge domains for this thesis . . . . . . . . . . . . . . 3

2.2 Simplified protection function block diagram . . . . . . . . . . . . . . . . . 5

2.3 Process interface: hard-wired vs. communication network . . . . . . . . . . 6

2.4 Short-circuit current of a far-from-generator fault . . . . . . . . . . . . . . . 7

2.5 Equivalent circuit digram for a single-phase to earth fault for low-impedance

earthing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6 Equivalent circuit digram for a single-phase to earth fault for resonance

earthing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Equivalent circuit digram for a single-phase to earth fault for a isolated

neutral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.8 Parameters of a real-time task . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.9 Logical versus temporal concurrency . . . . . . . . . . . . . . . . . . . . . . 16

2.10 Feasibility of EDF versus RMS . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.11 Protocol processing within EtherCAT Slaves . . . . . . . . . . . . . . . . . . 19

2.12 EtherCAT Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.13 Communication protocols defined in IEC 61850 . . . . . . . . . . . . . . . . 21

2.14 Structure of modelled SV APDU/ASDU & its encapsulation in Ethernet . . 22

3.1 Model-based design is applicable to V-model . . . . . . . . . . . . . . . . . 24

3.2 Number of defects found shifts to earlier stage of development process . . . 26

3.3 Independent time characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.4 Definite time reset characteristic . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5 Di↵erent EMC requirements for corresponding areas within a substation . . 31

3.6 Quad-core architecture without hyper-threading . . . . . . . . . . . . . . . . 34

3.7 Overview of Linux distribution . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.8 Specified development procedure . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1 Centralised architecture of protection system . . . . . . . . . . . . . . . . . 40

4.2 Overview of protection algorithm . . . . . . . . . . . . . . . . . . . . . . . . 41

4.3 Implemented signal processing algorithm . . . . . . . . . . . . . . . . . . . . 43

4.4 Developed signal processing block and mask . . . . . . . . . . . . . . . . . . 45

4.5 Developed PDOC block and mask . . . . . . . . . . . . . . . . . . . . . . . 46

vii

4.6 Characteristic of directional element . . . . . . . . . . . . . . . . . . . . . . 47

4.7 Definite-time curve of PDOC with 4 stages . . . . . . . . . . . . . . . . . . 49

4.8 Developed PDEF block and mask . . . . . . . . . . . . . . . . . . . . . . . . 50

4.9 Voltage profiles of V2 and 3V0 for ground faults . . . . . . . . . . . . . . . . 52

4.10 Developed phase selector block and mask . . . . . . . . . . . . . . . . . . . 55

4.11 Fault pattern: (a) Positive vs. negative sequence (b) Negative vs. zero-

sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.12 Scheme of voltage-based phase selector for weak-infeed conditions . . . . . . 56

4.13 Developed PTRC block and corresponding mask . . . . . . . . . . . . . . . 57

4.14 Etherlab library developed by IgH . . . . . . . . . . . . . . . . . . . . . . . 59

4.15 Concurrent access of EtherCAT master . . . . . . . . . . . . . . . . . . . . 61

4.16 Architecture of IgH EtherCAT master . . . . . . . . . . . . . . . . . . . . . 62

5.1 Functional performance test . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.2 Single-line-diagram of first network . . . . . . . . . . . . . . . . . . . . . . . 65

5.3 Single-line-diagram of second network with parallel lines . . . . . . . . . . . 65

5.4 Fault situation of case 1 for MiL . . . . . . . . . . . . . . . . . . . . . . . . 67

5.5 Fault situation of case 1 for SiL . . . . . . . . . . . . . . . . . . . . . . . . . 68











5.16 Laboratory setup for the Hardware-in-the-loop test . . . . . . . . . . . . . . 81

5.17 Distribution of start time for di↵erentIfault

Iset

ratios . . . . . . . . . . . . . . 86

5.18 Measured operate time for a setting of (a) instantaneous & (b) 600 ms . . . 87

5.19 Measured operate time for a setting of 3 s . . . . . . . . . . . . . . . . . . . 87

5.20 Distribution of disengaging time for di↵erentIpostFault

Iset

ratios . . . . . . . . . 88

5.21 Measured operate time for a setting of (a) 50 ms & (b) 600 ms . . . . . . . 89

5.22 Measured operate time for a setting of 3 s . . . . . . . . . . . . . . . . . . . 89

5.23 Typical test waveform for transient overreach . . . . . . . . . . . . . . . . . 90

5.24 Ports of equipment under test . . . . . . . . . . . . . . . . . . . . . . . . . . 96

viii

List of Tables

2.1 Used COTS components and their corresponding licenses . . . . . . . . . . 4

2.2 Voltage factor according to IEC 60909-0 . . . . . . . . . . . . . . . . . . . . 9

2.3 Characteristic of di↵erent neutral point treatments . . . . . . . . . . . . . . 13

2.4 Logical nodes and functional numbers for the protection functions . . . . . 21

3.1 Characterisation of the electromagnetic phenomena . . . . . . . . . . . . . . 30

3.2 Normal environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Hardware configuration of target system . . . . . . . . . . . . . . . . . . . . 34

4.1 Settings for signal processing element . . . . . . . . . . . . . . . . . . . . . . 45

4.2 Available sequence components during di↵erent fault scenarios . . . . . . . 47

4.3 Settings for directional element of PDOC . . . . . . . . . . . . . . . . . . . 48

4.4 Settings for the definite-time curve of PDOC . . . . . . . . . . . . . . . . . 49

4.5 Available sequence components during ground faults . . . . . . . . . . . . . 51

4.6 Di↵erent cases for virtual polarisation . . . . . . . . . . . . . . . . . . . . . 52

4.7 Settings for directional element of PDEF . . . . . . . . . . . . . . . . . . . . 53

4.8 Settings for the definite-time curve of PDEF . . . . . . . . . . . . . . . . . . 54

4.9 Settings for the phase selector block . . . . . . . . . . . . . . . . . . . . . . 57

4.10 Settings for the PTRC block . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.11 Configuration of the communication driver blocks and supervision . . . . . 59

5.1 General configuration for the functional performance test . . . . . . . . . . 66

5.2 Configuration of application for case 1 . . . . . . . . . . . . . . . . . . . . . 69






5.8 Comparison between Hil and Sil results (PDOC) . . . . . . . . . . . . . . . 82

5.9 Comparison between Hil and Sil results (PDEF) . . . . . . . . . . . . . . . 82

5.10 Type test results of common relays on the market for PDOC function . . . 83

5.11 Average & maximum error of pick-up/drop-o↵ for 10 di↵erent test points . 84

5.12 Average and minimum value of reset ratio . . . . . . . . . . . . . . . . . . . 85

ix

5.13 Results of the transient overreach test acc. to IEC 60255-151 . . . . . . . . 90

5.14 Results of overshoot time test acc. to IEC 60255-151 . . . . . . . . . . . . . 91

5.15 Ramping test to determine the accuracy of the directional elements . . . . . 92

5.16 Distribution of start time for di↵erent setups of runtime environment . . . . 94

5.17 Worst-case start time for di↵erent setups of runtime environment . . . . . . 94

5.18 Distribution of operate time for di↵erent setups of runtime environment . . 95

5.19 Worst-case operate time for di↵erent setups of runtime environment . . . . 96

5.20 Comparison between IEC 61000-6-5 and IEC 61000-6-2 for enclosure port . 97

5.21 Comparison between IEC 61000-6-5 and IEC 61000-6-2 for d.c. power ports 98

5.22 Comparison between IEC 61000-6-5 and IEC 61000-6-2 for signal ports . . . 99

x

Nomenclature

ANSI American National Standards Institute

APDU Application Protocol Data Unit

ASDU Application Service Data Unit

COMTRADE Common format for Transient Data Exchange for power systems

COTS Commercial O↵-the-Shelf

CPU Central Processing Unit

EDF Earliest Deadline First

EMC Electromagnetic Compatibility

ESC EtherCAT Slave Controller

DC Distributed Clock (EtherCAT domain)

DFT Discret Fourier Transformation

DMS Direct Memory Access

FIFO First-in-First-out

GNU General Public License

GOOSE Generic Object Oriented Substation Event

GSSE Generic Substation Status Event

GUI Graphical User Interface

HiL Hardware-in-the-Loop

HMI Human-Machine-Interface

IEC International Electrotechnical Commission

IED Intelligent Electronic Device

xi

IEEE Institute of Electrical and Electronics Engineers

IRQ Interrupt Request

LVDS Low Voltage Di↵erential Signaling

MiL Model-in-the-Loop

MTA Maximum Torque Angle

NIC Network Interface Card

OEM Original Equipment Manufacturer

PDO Process Data Object

RMS Root Mean Square (Electrical domain)

RMS Rate Monotonic Scheduling (Real-Time domain)

RR Round-Robin

SEI Software Engineering Institute

SiL Software-in-the-Loop

SV Sampled Value

Electrical nomenclature

u: small letters are used for instantaneous values

U : capital letters are used for RMS values

U : underline capital letter is used for complex numbers

Ua, U b, U c: phase values are indicted by the subscript a,b,c

U1, U2, U0: symmetrical components are indicted by the subscript 1,2,0

Linux nomenclature

Typewriter font is used for command line output

Bold typewriter font is used for command line inputs

0xFFFF: hexadecimal values are used for data values and addresses

$: the dollar sign is used for shell commands, which require user privileges

#: the mesh sign is used for shell commands, which require superuser privileges

xii

Chapter 1

Introduction

1.1 Problem Definition

Today’s power systems face dramatically changes and challenges. The conventional design

of the power system is based on a controllable and bulk generation of power, which is then

transmitted over the transmission and distribution grid to the consumers. Based on these

characteristics of the grid, various power system stability studies have been performed as

well as the protection systems have been designed. Nevertheless these assumptions have

started to change and for some systems they have already changed. This development

is mainly driven by the replacement of centralised large-scale power generation with dis-

tributed medium- to small-scale power generation, based on renewable energy sources like

wind or solar. A high penetration of distributed generation leads to an altered behaviour

of the power system. This change of generation has a major impact on several di↵erent

energy fields, such as energy markets and regulations, power system planning, power sys-

tem operation or power system stability and protection. The thesis focuses on the latter.

At the same time utilities have to deal with an increased pressure to reduce costs. This

is especially true for operators of distribution grids. Moreover the distribution grid is the

part of network, which is influenced the most by the changes of the power system described

above. Having tight cost restraints on the one side and on the other side an increased

demand for new protection systems in order to handle the high penetration of distributed

generation, the market requires a cost-e�cient protection system, which performs in a

reliable and stable manner.

1.2 Objectives

The objective of the Master’s thesis is to develop a protection system, which relies entirely

on Commercially-o↵-the-Shelf (COTS) components. Thereby it is shown that the time to

market of the development process can be reduced without jeopardising the reliability and

security performance. A directional overcurrent function as well as a directional earth fault

1

protection is developed in order to show the performance of the COTS based protection

system. Its performance is compared to proven IEDs on the market. The directional over-

current and earth fault protection are two types of functions, which are widely employed

in the distribution grids and therefore seen as justifiable choice as the preferred protection

function for this thesis. Moreover the directional element will be of greater importance in

the future due to the bidirectional power flow caused by the distributed generation.

In order to fulfil the demanding environmental constraints in terms of electromagnetic

compatibility (EMC), vibration, shock, moisture and temperature, the I/O modules are

separated from the computing unit. This approach has the advantage that only the mea-

suring units have to be compliant to the harsh environmental constraints, where as the

computing unit is located in a location with less stringent requirements. This setup re-

quires a fast and a deterministic communication solution between the I/O modules and

the computing unit. Moreover, the described design of the protection system leads to a

centralised architecture.

The thesis is seen as a proof of concept and therefore has certain limitations. Firstly,

the current inputs are limited to a maximum current of 1 A (RMS). Normally, secondary

short-circuit currents can rise above 50 A. In addition, the EMC performance of I/O mod-

ules is analysed based on data sheets and EMC standards. Thus no actual EMC tests are

performed due to the lack of suitable equipment. Moreover the functional performance

tests of the implemented protection functions are restricted to six di↵erent fault scenarios

due to time constraints. None the less, the fault scenarios have been carefully selected in

order to represent real-case scenarios.

1.3 Outline of the Thesis

The Master’s thesis is mainly divided into five di↵erent parts. First the necessary back-

ground knowledge is given in order to better understand the developed protection system.

This part also consists of some references to related work, which has already been per-

formed by other entities. Then the applied methodology of development is explained as

well as the requirements of a directional overcurrent and earth fault protection according

the corresponding IEC standards are described. In the third part of the thesis the actual

implementation of the protection algorithm is explained as well as the overall setup. The

fourth part evaluates the performance of the COTS-based protection system and compares

it with conventional IEDs. In particular a type test is performed in order to check, if the

protection system behaves according to the IEC standard, as well as a functional test is

executed. Moreover a stability test is carried out in order to investigate the long-term

performance. In the last part a discussion on future work is given as well as a conclusion

is stated, which comprised the results of this thesis.

2

Chapter 2

Background

The developed protection system is based on commercial-o↵-the-shelf components. There-

fore a definition of these type of components is given. Moreover, for a better understanding

of the later explained protection function, a brief introduction is given to the field of power

system protection. In addition, the protection function eventually requires to run on a

target system and to fetch measurements via a communication network. Therefore these

fields of research are concisely introduced as well. The figure 2.1 depicts those three im-

portant domains, which are considered throughout the thesis. Lastly the related work to

those domains is analysed.

Figure 2.1: Three important knowledge domains for this thesis

2.1 Commercial-o↵-the-shelf

Commercial-o↵-the-shelf (COTS) components can be considered as either hardware or soft-

ware. These components are ready-made and available to the general public. COTS-based

hardware and software can be directly used in large system, without any own develop-

ment e↵orts. COTS-based systems are seen as a convenient approach for a reduced time

3

to market and a competitive approach compared to developing everything from scratch.

In general COTS components can be bought directly, leased or they are licensed to the

general public. Especially the first and the last case will be of importance in this project

[42].

The table 2.1 below depicts the COTS software components, which are used in this project,

as well as their corresponding licenses.

COTS components License

Vanilla kernel GNU General Public License, version 2

Preeempt-rt patch GNU General Public License, version 2

Ubuntu desktop GNU General Public License

EtherLAB library GNU General Public License, version 3

IgH EtherCAT-Master GNU General Public License, version 2

PdCom library GNU Lesser General Public License, version 3

PdServ library GNU Lesser General Public License, version 3

Matlab/Simulink Di↵erent commercial licenses

Table 2.1: Used COTS components and their corresponding licenses

2.2 Power System Protection

Power system protection is a key issue to ensure a reliable and secure operation. Therefore

the general requirements of a protection system are described below. Since the imple-

mented function is a directional overcurrent as well as an earth fault protection, di↵erent

system grounding designs are explained below. The influence of various grounding tech-

niques on the fault characteristic is essential when developing an earth fault protection.

2.2.1 General objectives of protection systems

Each protection system in the power system has to fulfil certain general objectives. Those

are selectivity, reliability, sensitivity and speed. Selectivity is achieved, if only the faulty

part of the power system is isolated. There are di↵erent techniques in order to obtain

selectivity [41].

• Magnitude of the fault current

• Time grading

• Direction of fault power flow

Reliability refers to the ability of the protective device to operate, when it is supposed

to operate, and otherwise to remain una↵ected. There are two other terms found in the

4

literature, which refer to the same requirement. Dependability describes that the relay

operates in a selective manner in case of a fault. On the other hand security is the re-

quirement, that the protection system does not trip its protected unit for external faults.

External faults are regarded as faults, which lie outside of the corresponding protection

zone [41].

Sensitivity is the ability of the protection device to pick up small deviations of the system

parameters and react to them. Lastly speed refers to the operating speed, which is the

time between the occurrence of the fault and the trip command. Nevertheless the total

clearing time is longer, since it includes operating time of the circuit breaker as well as

the process of arc extinguishing [41].

2.2.2 Setups of Protection Systems

All protection system have the same general procedure of operation. First the input

energising quantities are obtained, which usually consist of currents and voltages. These

quantities are provided either directly by the voltage and current transformers (VT/CT)

or by a data packet via a communication network. According to IEC 60255-1 the preferred

rated RMS secondary voltages are 100 V, 110 V, 115 V, 120 V, 200 V, 230 V and the

preferred rated RMS secondary currents are either 1A or 5A. Lower current values can

also be used according to IEC 60044-8. Secondly the input quantities need to be run

through a measurement element, which extracts the required type of measurement (e.g.

True RMS, RMS of 50Hz component, phasors etc.). Thirdly these measured values are

compared to thresholds or other characteristics. If the logic is fulfilled, the time delays

are added and finally the trip command is issued. The figure 2.2 below is taken from the

overcurrent function standard IEC 60255-151 and illustrates the described procedure [2].

Figure 2.2: Simplified protection function block diagram [2]

In general there are two di↵erent setups to connect the protection system to the process.

5

The conventional approach is to connect the instrument transformers directly to an ana-

log input module of the relay. This has the advantage that the protection application is

located rather close to process and therefore is able to react with only small delays. The

disadvantages of this approach are the increased wiring e↵orts and engineering costs. In

the recent years a new setup has become popular, which involves a process bus between the

protection relay and the instrument transformers and circuit breakers. The current and

voltage transformers are interfaced via a merging unit, which will send the measurements

via a sampled value stream to the protection relay. This approach has the advantage, that

the protection device is able to receive not only measurements from its respective bay,

but also from other bays within the substation. Another advantage is the substantially

decreased wiring e↵orts. Nevertheless replacing wires with a network infrastructure re-

quires stringent latency and synchronisation requirements in order to operate in a correct

manner. The figure 2.3 depicts those two protection system setups.

Switch'

MU' MU'

POWER SYSTEM

COPPER WIRES

COMMUNICATION NETWORK

IED IED IED IED

Figure 2.3: Process interface: hard-wired vs. communication network

2.2.3 Fault current calculation

The expected short-circuit currents in the power system are one of the most important

design parameters for almost all primary equipments. This is due to the fact that the

current is directly correlated to the magnetic forces exposed on the equipment as well as

the generated thermal energy [43]. Usually the maximum as well as the minimum possible

short-circuit currents are calculated for the corresponding power system. The maximum

short-circuit current is the design parameter for the primary equipment as explained above.

Nevertheless the minimum short-circuit current is of importance for the protection sys-

tem, since this is the current, which defines the minimum setting of the protection relay.

This minimum short-circuit parameter defines the sensitivity requirement for protection

6

systems, as described in section 2.2.1.

There are two main standards, which describe the short-circuit calculations for three-phase

a.c. systems. The ANSI C37 and the IEC 60909. The following description focuses on

the IEC standard [43]. At this point it is mentioned that transmission lines of 550 kV

and higher need special consideration, which are not defined in IEC 60909. In general a

short-circuit is described by being either close to a generator or far-away. The di↵erence

is that a short-circuit close to a generator consists of a decaying a.c. and d.c compo-

nent, where as a short-circuit far-away from the generator only consists of a decaying d.c

component and a constant a.c component. In the figure 2.4 a typical characteristic of a

far-from-generator-short-circuit is depicted, which is described by the equation (2.1).

Figure 2.4: Short-circuit current of a far-from-generator fault [1]

In the figure above I 00k refers to the initial (symmetrical) short-circuit current, ip equals

the peak short-circuit current, A is the initial dc component and Ik is the steady-state

short-circuit current. Moreover it can be seen that the a.c. component is constant, as

characterised for a far-from-generator fault.

i(t) = is(t) + it(t)

=

p2 U

Zksin(!t + � � ✓) +

hp2 U

Zksin(✓ � �) + i(0)+

ie(�t/⌧)

(2.1)

Where

7

U : Equivalent voltage source⇣c Unp

3

⌘

c : Voltage factor acc. to table 2.2

Zk : Short-circuit impedance⇣p

R2 + X2⌘

� : Angle of voltage, when fault occurs

✓ : Angle of Zk

⇣tan�1

⇣! L

R

⌘⌘

⌧ : Time constant⇣L

R=

X/R

!

⌘

i(0)+ : Initial load current

One can see that the depicted short-circuit consists of a steady-state component is(t) as

well as a transient component it(t). This far-from-generator short-circuit can be described

by a sinusoidal current with a decaying d.c component. The highest instantaneous value

of the short-circuit current depends on the time constant as well as the angle �. It can be

shown that the maximum value is reached, when � equals �max, if the initial load current

i(0)+ is neglected. From equation (2.2) and assuming a purely inductive short-circuit

impedance Zk, the highest o↵set occurs at the zero-crossing of the voltage [7].

�max = ✓ � ⇡

2(2.2)

The standard IEC 60909 is based on some assumptions, which are stated below [1].

• Type of fault remains constant during fault duration (e.g. initial single-phase-to-

earth fault does not evolve to line-line-to-earth fault)

• No change of network topology and parameters occurs during time of short-circuit

• No arc resistance are considered

• Shunt capacitances and shunt admittances (loads) are neglected for the positive- and

negative sequence network.

• Shunt capacitance are only omitted for e↵ectively grounded systems, that means

that the earth fault factor � is smaller than 1.4

The general procedure for the calculation of short-circuit current is given by the following

steps [43].

1. Obtain one-line diagram with the following information of all primary equipment:

base MVA Sbase, base voltage Un, positive-, negative-, zero-sequence-impedance

(Z1, Z2, Z0) as well as the neutral connection of each transformer and generator

2. Derive the positive, negative and zero-sequence network as seen from the faulty bus

8

3. Connect sequence networks according to type of fault (e.g. for single-phase to ground

fault, all sequence networks are connected in series)

4. Obtain equivalent voltage source at faulty bus according to c Unp3

, where c is a voltage

factor found in table 2.2

5. Calculate initial symmetrical short-circuit current I 00k

From the above steps it can be seen that an equivalent voltage source at the fault location

is used together with a correction factor c. This approach is applied in the IEC 60909 in

order to avoid to run a large number of load flow calculations, which then yield the pre-fault

voltage. The voltage factor c considers various aspects, such as voltage variations due to

time and place of the fault or subtransient behaviour of generators or motors. Calculations

of c are found in IEC 60909-1. The IEC standard 60909-0 considers a symmetrical three-

phase fault as well as the following unbalance faults [1].

• line-to-line short circuit

• line-to-line short circuit with earth connection

• line-to-earth short circuit

Nominal Voltage Maximum short-circuit Minimum short-circuit

currents currents

Un cmax cmin

Low Voltage

100 V to 1 kV 1.05 0.95

IEC 60038, table I 1.10

Medium Voltage

>1 kV to 35 kV

IEC 60038, table III 1.10 1.00

High Voltage

>35 kV

IEC 60038, table IV

Table 2.2: Voltage factor according to IEC 60909-0 [1]

As explained above, the protection systems need to consider the minimum possible short-

circuit current in order to achieve maximum sensitivity. Therefore the following consider-

ations should be applied, when calculating the short-circuit current [1].

• Choose cmin according to table 2.2

9

• Choose network topology with minimum contribution to short-circuit from genera-

tors

• Motors are neglected

• Resistance of line is taken with maximum allowable conductor temperature

A single-line-to-earth fault is by far the most frequent type of faults [26]. Considering

a far-from-generator fault Z1 = Z2 and a high zero-sequence impedance Z0Z1

> 3, the

single-phase-to-earth fault will yield the smallest short-circuit current in comparison to

the other types of faults (e.g. three-phase, line-line). Considering the short-circuit in

figure 2.1, the following formulas are applied to calculate the initial RMS value of the

short-circuit I 00k1 and the breaking current Ib1 of a single-phase-earth fault. The subscript

1 refers to ”single-phase-to-earth”.

I 00k1 =

p3 cUn

Z1 + Z2 + Z0(2.3)

Ib1 = I 00k1 (2.4)

From the equation 2.4 it can be seen, that for a far-from-generator fault the short-circuit

breaking current equals the initial RMS value of the short-circuit current. This is due to

the fact, that the a.c. component of the short-circuit is constant.

Above a brief introduction to the short-circuit calculation of far-away-from-generator faults

is given. An extended short circuit study for near-to-generator short circuits and for dif-

ferent fault types is found in the IEC 60909-0.

2.2.4 System Grounding

In the previous section the general approach of short-circuit calculation is explained. Since

the most frequent faults are earth faults, it is important to understand the influence of

di↵erent grounding techniques on the earth fault current magnitude as well as on the

change in voltage of the healthy lines. In principal there are four di↵erent characteris-

tics of neutral point treatment, which are low-impedance earthing, earthing with current

limitation, resonance earthing and isolated neutral, which are explained below. Power

systems above 132 kV are usually low-impedance earthed. Nevertheless all other types of

system groundings are found in distribution grids. Especially isolated networks are often

found in industrial power systems due to their high availability, as shown below. From the

equations (2.5) and (2.6) it can be seen, that there is a trade-o↵ between low short-circuit

currents and high voltages on the healthy phases [26].

|U b| = |U c| = Un

pk2 + k + 1

2 + k(2.5)

10

I 00k1 =Unp3 Z1

3

2 + k(2.6)

Where

k =Z0

Z1

Un : Nominal system voltage

Ub; Uc : Voltages of healthy phases

I 00k1 : Single-line-to-earth fault of phase a

The type of neutral point treatment is directly related to the zero-sequence impedance.

From the variable k it can be seen, that for higher Z0 the earth fault I 00k1 decreases and

the voltage of the healthy lines increases, and vice versa for lower Z0.

Low-impedance earthing: Neutral points, which are low-impedance earthed, are solidly

earthed without any intentional resistance or reactance. This is the most common earthing

technique for high voltage systems, since the voltage on the healthy lines remains below

1.4 Un at the expense of an increased short-circuit current during a fault. 1.4 is the earth

fault factor � and it is defined as the ratio between the maximum RMS value of the over-

voltage during a fault and the rated voltage of the line. The figure 2.5 shows an equivalent

circuit digram (a) as well as the series connection of the symmetrical components network

(b) in case of a single-phase to earth fault.

100 Short-circuit currents

R

Y

B

Z0; Z1; Z2

IR

UY; UB

(a)

U1

U2

U0

I1

I2

I0

Z1

Z2

Z0

E1 = E 0

01

02

00

(b)

Figure 5.1 Equivalent circuit diagram of a single-phase short-circuit (system withlow-impedance earthing). (a) Diagram in RYB-system, (b) equivalentcircuit diagram in the system of symmetrical components

with voltage factor c according to Table 4.1. If the single-phase short-circuit currentis related to the three-phase short-circuit current

I ′′k3 = c ∗ Un√

3 ∗ Z1(5.2)

it follows that

I ′′k1

I ′′k3

= 3 ∗ Z1

2 ∗ Z1 + Z0(5.3)

The relation of single-phase to three-phase short-circuit current depending on theratio of Z1/Z0 with the difference of phase angles (γ1 − γ0) of the impedancesas parameter is outlined in Figure 5.2. The phase angles γ1 and γ0 are definedby the arcustangens-function γ1 = arctan(X1/R1) in the positive-sequence systemrespectively γ0 = arctan(X0/R0) in the zero-sequence system.

Figure 2.5: Equivalent circuit digram for a single-phase to earth fault for low-impedance

earthing [43]

Current limiting earthing: In case of current limiting earthing, a reactance or resis-

tance is placed between the neutral point and the ground. The objective of this type of

neutral point treatment is the reduction of the earth fault current. Nevertheless this leads

to an increase earth fault factor �. Therefore current limiting earthing is mainly applied

in networks, which have a nominal voltage Un below 20 kV [43].

11

Resonance earthing: Resonance earthing is achieved by placing a controllable reac-

tance between the neutral point and the earth potential. This controllable reactance is

usually a Peterson coil. The reason of resonance earthing is to limit to capacitive fault

current by opposing it with a inductive current through the Peterson coil. The figure 2.6

shows the equivalent circuit (a) and its sequence network (b). The positive and negative se-

quence impedance is neglected, since it is relative small in comparison to the zero-sequence

impedance. From figure 2.6 (b) it can be seen that a parallel resonance circuit is created,

which admittance can be described by the equation (2.7) [43].

Influence of neutral earthing 109

MV-systems having nominal voltages Un = 10–30 kV and nearly 80 per cent of110-kV-systems are operated with resonance earthing (Criteria: Total line lengths).Some MV-systems are operated with a combined scheme of resonance earthingunder normal operating conditions and low-impedance earthing in case of earth-fault. Resonance earthing, therefore, is the dominating type of system earthing inGermany for power systems with voltage 10 kV up to 110 kV. In other countries suchas India, South Africa and China, power systems with resonance earthing have gainedan increasing importance during the last decades, however are still not so commonas systems with low-voltage earthing.

Resonance earthing is realised by earthing of one or several neutrals of trans-formers through reactances (Petersen-coils), normally adjustable, which will be set inresonance to the phase-to-earth capacitances of the system. The principal arrangementof a power system with resonance earthing is outlined in Figure 5.10.

The impedances of transformers and lines of the positive-sequence component canbe neglected compared with those of the zero-sequence component due to the orderof magnitude of the impedances. The admittance of the zero-sequence component is

~

~

~

E Un

U0LD

GE

B (L3)

Y (L2)

R (L1)

CE3

=

~ E1

GE CEU0

01/02

00

(a)

(b)

310

3LD

3RD

Figure 5.10 System with resonance earthing, earth-fault in phase R. (a) Equivalentdiagram in RYB-system and (b) equivalent diagram in the system ofsymmetrical components


MV-systems having nominal voltages Un = 10–30 kV and nearly 80 per cent of110-kV-systems are operated with resonance earthing (Criteria: Total line lengths).Some MV-systems are operated with a combined scheme of resonance earthingunder normal operating conditions and low-impedance earthing in case of earth-fault. Resonance earthing, therefore, is the dominating type of system earthing inGermany for power systems with voltage 10 kV up to 110 kV. In other countries suchas India, South Africa and China, power systems with resonance earthing have gainedan increasing importance during the last decades, however are still not so commonas systems with low-voltage earthing.

Resonance earthing is realised by earthing of one or several neutrals of trans-formers through reactances (Petersen-coils), normally adjustable, which will be set inresonance to the phase-to-earth capacitances of the system. The principal arrangementof a power system with resonance earthing is outlined in Figure 5.10.

The impedances of transformers and lines of the positive-sequence component canbe neglected compared with those of the zero-sequence component due to the orderof magnitude of the impedances. The admittance of the zero-sequence component is

~

~

~

E Un

U0LD

GE

B (L3)

Y (L2)

R (L1)

CE3

=

~ E1

GE CEU0

01/02

00

(a)

(b)

310

3LD

3RD

Figure 5.10 System with resonance earthing, earth-fault in phase R. (a) Equivalentdiagram in RYB-system and (b) equivalent diagram in the system ofsymmetrical components

Figure 2.6: Equivalent circuit digram for a single-phase to earth fault for resonance

earthing [43]

Y 0 = j! CE

⇣1 � 1

3!2 LD CE

⌘+ GE +

1

3 RD(2.7)

In order to yield minimum earth fault currents, maximum impedance need to be obtained.

This is done by minimising the imaginary part of the admittance in equation (2.7) for the

system frequency of 50 Hz in European networks. The tuning of LD is done by changing

the tap position of the Peterson coil. The resonance earthing is widely applied in Central

European power systems. In Nordic countries the resonant earth systems become more

popular due to the increase cable networks and their high capacitive fault currents [28].

Isolated neutral: The forth type of neutral point treatment is the isolated neutral.

In this case the neutral point is floating. The main application of isolated neutrals are

industrial power systems. In case of single-phase to earth fault only capacitive fault cur-

rent flows (neglecting the conductances G). This capacitive fault current ICE is usually

smaller than the nominal load current. In such an event the neutral point rises to the

phase-to-ground voltage of the faulty line and therefore the voltage of the healthy lines

increases byp

3. Thus the insulation requirements for isolated neutral systems are much

higher than for low-impedance earthed networks. The corresponding circuit diagrams for

this described single-phase to earth fault are depicted in the figure 2.7.

12

For low-voltage systems, which require a high availability, isolated neutral systems are

mostly applied. This is due to the fact that if the contact voltage in case of a single-phase

fault is less than 50 V (acc. to IEC 60364), the fault does not have to be cleared right away.

This type of neutral point treatment for low-voltage systems is compulsory for hospitals

in France [27].


of the single-phase short-circuit current to I ′′k1 = 2 kA the ratio X0/X1 = 6.7–19.6

is required. The earth-fault factor in this case will be δ = 1.44–1.61. By this, thesystem is no longer a system with low-impedance earthing.

5.4 Power system with isolated neutral

The operation of power systems with isolated neutrals is applicable to systemswith nominal voltages up to 60 kV, however the main application is seen in powerstation auxiliary installations and industrial power systems with voltages up to 10 kV.In public supply systems, isolated neutrals are not very common.

The analysis of a single-phase earth-fault is based on Figure 5.6.

~

~

~

E Un

GE

B (L3)

Y (L2)

R (L1)

CE3

=

~ E1

GE CE U0

01/02

00

(a)

(b)

Figure 5.6 Power system with isolated neutral with single-phase earth-fault.(a) Equivalent circuit diagram in RYB-system and (b) equivalent circuitdiagram in the system of symmetrical components

Contrary to power systems with low-impedance earthing or earthing withcurrent limitation the capacitances phase-to-earth capacitances in the zero-sequencecomponent cannot be neglected in power systems with isolated neutral as can beseen from Figure 5.6. To determine the respective parameters of the equipment,no-load measurements are necessary. The single-phase earth-fault current, in general,


of the single-phase short-circuit current to I ′′k1 = 2 kA the ratio X0/X1 = 6.7–19.6

is required. The earth-fault factor in this case will be δ = 1.44–1.61. By this, thesystem is no longer a system with low-impedance earthing.

5.4 Power system with isolated neutral

The operation of power systems with isolated neutrals is applicable to systemswith nominal voltages up to 60 kV, however the main application is seen in powerstation auxiliary installations and industrial power systems with voltages up to 10 kV.In public supply systems, isolated neutrals are not very common.

The analysis of a single-phase earth-fault is based on Figure 5.6.

~

~

~

E Un

GE

B (L3)

Y (L2)

R (L1)

CE3

=

~ E1

GE CE U0

01/02

00

(a)

(b)

Figure 5.6 Power system with isolated neutral with single-phase earth-fault.(a) Equivalent circuit diagram in RYB-system and (b) equivalent circuitdiagram in the system of symmetrical components

Contrary to power systems with low-impedance earthing or earthing withcurrent limitation the capacitances phase-to-earth capacitances in the zero-sequencecomponent cannot be neglected in power systems with isolated neutral as can beseen from Figure 5.6. To determine the respective parameters of the equipment,no-load measurements are necessary. The single-phase earth-fault current, in general,

Figure 2.7: Equivalent circuit digram for a single-phase to earth fault for a isolated

neutral [43]

The table 2.3 shows a summarised view of the di↵erent characteristics of the various types

of system groundings, as shown above.

Low-

impedance

earthing

Earthing

with current

limitation

Resonance earth-

ing

Isolated neutral

SP current I 00k1 =cp

(3)Un

2Z1+Z0I 00k1 =

cp

(3)Un

2Z1+Z0IR ⇡ j

p3Un! ⇤

CE(�0 + jv)

ICE ⇡ jp

(3)!CeUn

Earth-fault

fac. �

< 1.38 1.38 �p

3 ⇡p

3 � 1.1p

3 ⇡p

3

k = Z0Z1

High 2 � 4 > 4 Infinite

Repetition

of faults

Double earth-

fault

None None Double earth-fault

Table 2.3: Characteristic of di↵erent neutral point treatments [43]

2.3 Real-Time Systems

The protection system need to run in a reliable and deterministic way. Therefore it

is deployed on a real-time operating system. The characteristics of such a system are

described below.

2.3.1 Description

In the literature a real-time system is described as followed:

13

”A real-time computer system is a computer system in which the correctness of

the system behaviour depends not only on the logical results of the computation,

but also on the physical instant at which these results are produced” ([44])

From the quote above it can be noticed that the timing aspect of real-time systems is

of major concern. Therefore the term real-time does not refer to a fast execution of a

program, but rather to its deterministic behaviour. Moreover a real-time system is a

computer system with the following requirements [45]:

• Time requirements (hard vs. soft)

• Time-triggered and event-triggered events

• Concurrent activities

• Digital and analogue signals

Hard vs. Soft Real-Time: The time requirements are distinguished between hard and

soft real-time. Computer systems, which are not allowed to miss a single deadline, are

regarded as hard real-time. On the other hand, if the system still operates reliable and

securely in case of occasional missed deadlines, it is described as soft real-time.

Events: Moreover a real-time system need to handle events. Events can be either periodic

or aperiodic and internal or external. An example for an external aperiodic event would

be a received ethernet frame by the network interface card (NIC). The computer system

handles those events by the means of tasks (see 2.3.2).

Concurrent activities: Real-time systems are able to react to co-concurrent events.

The required tasks to handle those events are either multiplexed on a single CPU (single-

threading) or run on several CPU cores at the same time (multi-threading). Therefore

some scheduling policies (see 2.3.3) and interrupts (see below) are needed.

Signals: It is obvious that the real-time system need a interface to the process, which its

controls, in order to receive information in the form of digital or analogue measurements.

Those information can either be obtained by a dedicated I/O module or via a network

interface card.

Moreover it is important to understand the function of the kernel. The kernel is the

main entity of the operating system, which represent the interface between the hardware

and the application. The kernel has mainly four important components [8]:

• Scheduler: The role of the scheduler is to allocate processors time to di↵erent task

according to the scheduler policy (see 2.3.3)

• Interrupt handler: The interrupt handler manages requests from hardware, like

network interface card (NIC) or keyboard, or from software directly

14

• Memory manager: The memory manager is responsible of allocating memory

space to each task

• Other services: During operation of the kernel, there are many services running

in the background. For example synchronisation of shared resources, supervision of

task resource allocation, timing synchronisation

2.3.2 Process, Thread & Task

In order to understand how a real-time system behaves and the corresponding scheduler

works, it is important to understand the di↵erence between a process, a thread and a task.

The description given below is mainly based on the Linux environment.

A process is a program, which is executed and has its own allocated memory. Further-

more, a process can consist of multiple of threads, which implement di↵erent part of the

computations. Lastly, a task is either a single-threaded process or a thread as part of

multi-threaded process. The task is the basic unit, which is handled by the scheduler (see

2.3.3) [31]. A task Ji is characterised by the following attributes, as shown in figure 2.8:

[45]

• Arrival time ai, at which the task Ji becomes ready to execute (sometimes referred

as release time ri)

• Computation time Ci, is the CPU time to execute Ji without interruption

• Deadline: The relative deadline di is time, when Ji has to be completed and is

relative to ai. The absolute deadline Di is a time with respect to the global system

time

• Start time si is the actual time, when Ji starts to execute

• Finishing time fi is the actual time, when Ji finishes to execute

Moreover if the task is scheduled periodically, then the task Ji has also the attribute period

Ti. Ti defines the period of time, when the next instance of the task is released.18 HARDWARE-DEPENDENT SOFTWARE

Figure 2.1. Parameters of a real-time task.

under control of the application task. A task which is not known to the RTOSobviously is also not considered by it.

Another parameter that comes with the application task is its computationtime Ci . This is the WCET which has to be determined previously and has tobe known by the RTOS. Of course it is the WCET only under the assumptionthat the task is not interfered by any other task. Interference can happen onlywhen managed by the RTOS. So any influence by interference due to othertasks is known by the RTOS and has to be considered by the RTOS.

The third parameter that comes with the application task is its deadline.Here a distinction has to be made between an absolute deadline, denotedby di and a relative one, denoted by Di . Absolute deadline means a valuewith respect to the global time of the entire system while relative deadlinemeans relative to the arrival time of the respective task. In any case, it hasto be guaranteed by the RTOS that the tasks will be finished not later thanthe deadline, independent from any circumstances, even the worst imaginableones.

The remaining two parameters are under control of the RTOS. It is the RTOSthat decides when to start an application task, i.e. to set the start time si . Ofcourse it can never be earlier than the arrival time ai as before this time the taskis entirely unknown to the RTOS.

In a similar manner it is up to the RTOS when a task reaches its finishingtime fi . It can be calculated to be at least si +Ci . However, Ji may be disturbedby other tasks so that the finishing time fi may be later. Whenever this happens,it happens under control of the RTOS. Therefore it is the responsibility of theRTOS to guarantee that fi is not later than the respective deadline.

Orthogonally to the distinction into soft, firm, and hard real-time two mainclasses of tasks can be identified: periodic and aperiodic ones. Both types aregeneric tasks, i.e. over time a sequence of instances is generated. Usually suchan instance is called job. All instances share the same code and therefore thesame WCET and relative deadline. In case of periodic tasks these instancesshow up with a fixed period, denoted by Ti . This means that once knowing thefirst arrival time, all following arrival times are pre-defined. The first arrival

Figure 2.8: Parameters of a real-time task Ji [45]

As described above, di↵erent task can occur at the same time and therefore need to be

multiplexed on the CPU core. The figure 2.9 shows this behaviour. It can be seen that

15

the current runnable task is preempted and a context switch occurs. Context switch

means that the context of the previously task is saved and the context of the new task

is restored. The decision, which task is executed next, is made by the scheduler of the

operating system, as shown in section 2.3.3.

time

Task A

Task B

Task C

Logical concurrency

time

Task A

Task B

Task C

Temporal concurrency Context switch

Figure 2.9: Logical versus temporal concurrency

2.3.3 Scheduling policies

The scheduler can be distinguished between clock-driven and priority-driven schedul-

ing. In clock-driven systems the scheduling decision are based on time. Therefore the

scheduler is calculated o↵-line and then used during run-time. This approach is very ap-

plicable for hard real-time systems. Nevertheless the drawback is that all tasks and its

resources need to be known before. Moreover only periodic tasks are able to be scheduled

and tasks, which are created during execution, are not considered. On the other hand,

the priority-driven scheduling rests upon the di↵erent priorities of each tasks, which define

the execution order. Thus the scheduling process is performed online during execution.

Therefore periodic as well as aperiodic tasks are able to be scheduled. The drawback of the

online scheduling method is the increased overhead. There are many di↵erent scheduling

strategies based on priorities and this scheduling method is quite popular for commer-

cially available kernels (e.g. WinCE, Free RTOS, VxWorks, Xenomai, RTAI, RT-Preempt

Patch). Therefore priority-driven scheduling is discussed below [8].

The priority-driven scheduling can be further classified between periodic and aperiodic

tasks algorithms. Since the developed protection function is run as multiple periodic

16

tasks, the following description focuses on priority-driven periodic scheduling algorithm.

Within this classification there are two popular algorithms for assigning priorities to tasks,

namely rate monotonic scheduling (RMS) and earliest deadline first (EDF) [45].

• Earliest Deadline First: The EDF algorithm assigns the priorities to the tasks

according to their deadline di. Thus a task with the shortest di obtains the highest

priority and is therefore executed first. Therefore the priority of a task changes

dynamically during its lifetime. This algorithm works also for aperiodic tasks.

• Rate Monotonic Scheduling: The RMS algorithm assigns static priorities to

task according to their period Ti. The task with the smallest Ti yields the highest

priority. This algorithm is only suitable for periodic tasks, since its decision making

is based on Ti.

In order to determine the feasibility of the chosen scheduling algorithm, the utilisation

of the CPU U has to be analysed for a number of tasks n, which is given by equation

(2.8). For the following analysis, it is assumed that the tasks are independent (no data

dependency of other tasks) and periodic. Furthermore preemptive scheduling is applied.

This means that each task is able to be preempted by another task with a higher priority.

All tasks are suppose to run on an uniprocessor [45].

U =nX

k=1

Ci

Ti(2.8)

For both scheduling policies EDF and RMS the equation (2.9) has to be fulfilled. That

means that the utilisation of the CPU must be less than 1.

U 1 (2.9)

Nevertheless this condition is not su�cient for the RMS policy. Therefore equation (2.10)

has to be satisfied for the rate monotonic scheduling.

U n (21/n � 1) (2.10)

If the number of tasks n approaches infinity, the utilisation of the CPU should be less

then 69%. The figure 5.4 depicts the feasibility of the two schedule policies EDF and RMS

for two periodic and independent tasks. It can be seen that the conditions for a feasible

schedule is tighter for RMS than for EDF.

17

U1

U2

RMS

EDF

1 0.83

0.83

1

U ≤ 1

U ≤ 2 (21/2 - 1)

Figure 2.10: Feasibility of EDF versus RMS

2.4 Communication

Concerning the setup with a process bus, described in section 2.2.2, di↵erent communica-

tion protocols are considered. The IEC 61850-9-2 is the ”de-facto” standard for gathering

sampled values in substation. Nevertheless IEC 61850-9-2 is still highly customised. More-

over EtherCAT is an emerging real-time protocol, which is mainly used in the industrial

automation field, and it is considered as a COTS-solution. Therefore both protocols are

described below.

2.4.1 EtherCAT

EtherCAT is a Ethernet fieldbus protocol, which supports real-time performance down to

the I/O level and which is based on the fieldbus standard IEC 61158. This protocol is

based on a master-slave communication. If the EtherCAT protocol is applied, then the

ethernet frame is not longer received, interpreted and resend at every node in the network.

Instead the frame is read and processed by the EtherCAT slaves ”on the fly”. That means

that the data is read and written before the frame has been fully received. This approach

leads to the ability of very short cycle times ( 100 µs). In order to achieve full Ethernet

support down to I/O terminals, the physical layer is changed from 100BASE-TX or -FX

to the E-bus, which signal is based on LVDS [11].

18

Figure 2.11: Protocol processing within EtherCAT Slaves [9]

Furthermore a high synchronisation precision of the EtherCAT slaves ( 1 µs) is achieved

by the usage of the distributed clock (DC) algorithm. Each slave, equipped with the DC

algorithm, has a local clock, which starts from zero once it is powered on. Since the slaves

can be powered at di↵erent time instances and the quarts based clocks have a natural

frequency deviation, these deviations have to be compensated by the distributed clock

mechanism. The propagation delay between two slaves is considered as well [11]. More-

over commercial-o↵-the-shelf components can be used to implement to EtherCAT master

and slaves.

Master: The EtherCAT Master is the head of the communication and consists of a

standard network interface card as well as a dedicated EtherCAT driver. A standard net-

work card is su�cient due to the usage of direct memory access (DMS). Thus the CPU

performance is not needed for the network access. Furthermore the master provides the

bus configuration as well as gathers the process data from the EtherCAT slaves [39].

Slaves: The slaves devices are based on ASIC or FPGA in order to achieve a fast response

time. Those chips implement the EtherCAT Slave Controller (ESC), which is basically

the gateway between the E-bus and the digital I/Os. There are several EtherCAT slaves

for di↵erent applications based on digital inputs/outputs as well as analog inputs/out-

puts. Those inputs and outputs are represented as Process Data Objects (PDO) on the

application layer [39].

Infrastructure: The EtherCAT infrastructure does not require any hubs or switches.

The lack of switches is seen as a step towards a better deterministic behaviour due to

the absence of bu↵ers. Standard CAT5 cable can be used to connect the Master with the

19

slaves. Nevertheless in a substation environment CAT5 cables are not recommended due

to their weak EMC performance. Instead, fiber optic cables should be used.

Process Data: The Process Data Objects (PDO), as described above, represent the

inputs and outputs of the EtherCAT slaves. The total sum of all PDOs is described as

the Process Data Image. This Process Data Image can have an addressable size of up to 4

Gigabyte. Nevertheless not all PDOs have to be exchanged/updated each cycle time and

the Ethernet frame has a limited size as shown below. Therefore Process Data Domains

are introduced to manage the datagram structures as well as the concerned PDOs for

corresponding communication cycle.

EtherCAT-Protocol: The EtherCAT protocol uses the standard Ethernet frame ac-

cording to IEEE 802.3, which indicates the EtherCAT protocol by the EtherType field

(0x88A4) as shown in figure 2.12. Concerning real-time ethernet protocols the Process

Data Domain is usually directly inserted in the payload of the Ethernet frame. Neverthe-

less the option to use IP-packets is still available, but not recommended for time critical

applications. From figure 2.12 it is seen that the maximum payload of the EtherCAT

datagram is 1498 Bytes [11]. The EtherCAT protocol tries to utilise the entire available

space within one Ethernet frame. If the Process Data Domain is larger than 1498 Bytes,

then a second frame is send. This approach leads to a very high bandwidth usage (80 to

97%) in comparison to other ethernet based protocols [3].

EtherCAT is:

- Faster

- Synchronization

- Industrial Ethernet

- Flexible Topology

- Easier to configure

- Cost effective

- Easier to implement

- Well proven

- Open

- Conformance

- Safety

- Redundancy

- Versatile

© EtherCAT Technology Group, 2012

Embedded in Standard Ethernet Frame, EtherType 0x88A4

EtherCAT is Industrial Ethernet!

• EtherCAT uses Standard Ethernet Frames: IEEE 802.3 • Alternatively via UDP/IP (if IP Routing is needed) • no shortened frames

1…n EtherCAT Datagrams

Type Res. Length

1 Bit 4 Bit 11 Bit Or: via UDP/IP UDP Port 0x88A4

Destination EtherType Source

16 Bit

Header EtherCAT Datagrams CRC

48 -1498 Byte

MTU: max. 1514 Byte

48 Bit 48 Bit 16 Bit 32 Bit

16 Bit

IP Header UDP H.

160 Bit 64 Bit

Header EtherCAT Datagrams CRC

48 -1470 Byte

Ethernet H.

3 3

October 2012

Figure 2.12: EtherCAT Frame [3]

2.4.2 IEC 61850-9-2 & 61850-9-2LE

The IEC standard 61850 covers the communication networks between di↵erent intelligent

electronic devices (IED) in a substations of all di↵erent voltage levels. Di↵erent protocols

are defined as part of IEC 61850 depending on its timing requirements as shown in figure

20

2.13. It can be seen that the time critical protocols (SV, GOOSE, GSSE) are directly

mapped to the data link layer. This standard also introduces the concept of logical nodes

(LN) in IEC 61850-7-4. LNs are subfunctions, which communicate with each other in

order to carry out the main function. Some important logical nodes, which are used in

this thesis, are shown in table 2.4. For clarity reasons the ANSI function numbers are

stated as well.

Function Description IEC 61850-7-4 IEEE/ANSI C37.2

Logical Nodes Function Numbers

Time delayed phase overcurrent protection PTOC 51

Time delayed earth fault protection PTOC 51N

Directional overcurrent protection PDOC 67

Directional earth fault protection PDEF 67N

Protection trip condition PTRC -

Current transformer (e.g. Analog Inputs) TCTR -

Voltage transformer (e.g. Analog Inputs) TVTR -

Circuit breaker (e.g. DI/DO) XCBR 52

Human machine interface IHMI -

Data Logging GLOG -

Table 2.4: Logical nodes and functional numbers for the protection functions [20]

One of the main objectives of this IEC standard is the interoperability between IEDs of

di↵erent vendors. For this thesis the part 9.2 is of major importance, since it describes

the implementation of the process bus based on Sampled Values (SV) [20].

Sampled Values GOOSE GSSE Client-Server

MMS

TCP

Time Sync

UDP

IP

Ethernet (ISO/IEC 8802-3)

Physical Medium

GSSE Specific

Application

Transport

Network

Data Link

Physical

OSI stackTime-critical

Directmapping

Fig. 1. Communication services defined in IEC 61850

II. OVERVIEW OF IEC 61850

The first edition of the IEC 61850 standard comprises 12parts in total. Each part describes different aspects of thecommunications taking place within a substation automationsystem. For example, part 7 presents the logical view of thecommunication system, i.e., logical models of devices, abstractcommunication service interface (ACSI), etc., while parts 8and 9 specify how these logical concepts ought to be mappedinto a specific communications infrastructure, i.e., protocolstack.

Throughout this investigation part 9-2 of the standard wasscrutinised in-depth since it describes how Sampled Valuesprotocol should be designed and mapped to Ethernet (ISO/IEC8802-3). Part 9-1 was also analysed, however, in less detailsince it is likely to be withdrawn from the future releases ofthe standard [5].

IEC 61850 defines 5 types of communication services asshown in Fig. 1. The first three types are time-critical andare used in protection and control schemes of the substation.They include Sampled Values (SV) and Generic Object Ori-ented Substation Event (GOOSE) protocols which are mappeddirectly to Data Link layer for reduced protocol overhead andhence increased performance; and Generic Substation StateEvent (GSSE) protocol which features its own custom protocolmapping. The remaining two types of services, i.e., TimeSync and Client-Server Manufacturing Message Specification(MMS), deal with time synchronisation and management ofthe substation devices respectively.

In order to better understand how these services are usedwithin a substation consider the simplified protection & controlsystem shown in Fig. 2. A Merging Unit (MU) accepts multi-ple analogue current and voltage samples coming from currentand voltage transformers which are connected directly to thepower line. It then acts as an analogue-to-digital-converterconverting the samples into digital format and encapsulatingthem along with meta-data to put these measurements incontext as SV packets, and sends them over the switchedEthernet network to Protection & Control (P&C) units [6].The P&C extracts the samples, and examines them to detectevidence of a fault in the protected zone of the network.If the outcome of the examination is positive, it issues aTrip message encapsulated as GOOSE/GSSE packet to theCircuit Breaker (CB) unit which then trips the appropriateswitchgear and isolates the fault [7]. Afterwards, CB advises

HMI – Human-Machine InterfaceP&C – Protection & ControlMU – Merging UnitCB – Circuit Breaker

MU CB

P&C

Powerline

Process bus

Other substationdevices (e.g. HMI)

Gateway to othersubstations

Station bus

Switched Ethernet

Switched Ethernet

Fig. 2. Simplified protection & control system used within a substation

other monitoring units of the action by issuing GOOSE/GSSEpacket. The exchange of time-critical messages describedabove is based on the publisher/subscriber messaging modelin which one or more subscribers subscribe to the publisherstating that they want to be notified of a particular event (inthis case, to act as sinks for SV or GOOSE/GSSE packets).

Time Sync service which was not mentioned in the exampleabove is substation-wide in scope and is used to distributecommon timing information across substation devices whichrequire such information. For instance, MUs in order tocorrectly handle processing of current and voltage samplesneed to be provided with timing information. The two mostpopular methods for time synchronisation in the industryinclude Global Positioning System (GPS) and the more recentIEEE 1588 Precision Time Protocol (PTP).

Client-Server MMS, similarly to Time Sync service, issubstation-wide in scope and is used to manage substation de-vices attached to both process and station buses. In operation,it is quite similar to Simple Network Management Protocol(SNMP), and is also based on the client/server messagingmodel in which the client polls the server for specific data.

The criticality of rigorous assessment and appraisal of inter-operability is inherent to the widespread adoption of this stan-dard within an industry that is risk averse and safety critical.A facility to validate protection and automation functionalitywithin an increasingly integrated ICT system supporting theSmart Grid is essential to its realisation. This work supportsthis ambition.

III. LITERATURE OVERVIEW

Several research investigations looked into the topic ofsimulation modelling of communication services defined in theIEC 61850 standard. Sidhu and Yin produced two publications[8], [9] showing how the OPNET Modeler network simulatorcan be used to model the substation communication networkand analyse the network’s dynamic performance (i.e., packetdelay characteristics of time-critical services). Their model ofSV traffic generator mapped packets directly onto Ethernetand, in their latter publication, included handling of IEEE802.1Q VLAN tags. Moreover, in [9], the model additionallyappended SV-specific header, application service data units(ASDUs), and application protocol data unit (APDU) accord-ing to IEC 61850-9-1.

Figure 2.13: Communication protocols defined in IEC 61850 [24]

The basic parts of the process bus are the merging unit, defined in IEC 60044-8, a time

synchronisation source for multiple SV streams and a Ethernet switch. The merging unit

can be seen as the core of the process bus, since it realises the interface between the process

and the network. The need for Ethernet switches is given by the fact that the process bus

is usually not a point-to-point connection. The principle of publisher-subscriber is used.

The 61850-9-2 is also a Ethernet based protocol, which uses multicast to send its data via

Ethernet switches to the respective IEDs. The EtherType field indicates Sampled Values

with the value 0x88BA. Furthermore priority tagging is used according to IEEE 802.1q in

21

order to separate time critical data for protection purposes from other tra�c. The payload

of the Ethernet frame consists of the SV header, the APDU (Application Protocol Data

Unit) and several ASDUs (Application Service Data Unit) as shown in figure 2.14. [20].

SV Publisher

VLAN Interface

FDEthernet

FDChannel

SV Subscriber

VLAN Interface

FDEthernet

FDChannel

Application Layer

Data Link Layer

Physical Layer

Switched Ethernet

Packet flow

GeneratorNode

SinkNode

Fig. 3. OSI-7 reference model of the SV traffic generator

0x600x800xA2

0x300x800x820x830x850x87

Length1 10

LengthLength

10-34241

64

ValueValue

1Value

Samples (each

8-bytes long)

0x30 Length ASDU 2

0x30 Length ASDU 10

savPdunoASDUSequence of ASDUSequence ASDU 1svIDsmpCntconfRevsmpSynchSequence of Samples

Sequence ASDU 2

Sequence ASDU 10

Type Length Value

Type Length Value

ASDU 1

Fig. 4. Structure of modelled SV APDU/ASDU (ASN.1/BER TLV triplets)

Kanabar et al. [10] presented results of modelling communi-cation networks for distributed automation systems with DERsin the OPNET Modeler. In their investigation, SV protocol wasmapped directly onto Ethernet layer, and included VLAN tags.However, no information was provided whether SV-specificheader, ASDUs and APDU were also appended. Similarly,Ali and Thomas [11] did not specify whether any SV-specificfields were attached to the packet while modelling variouscommunication scenarios within a substation in the OPNETModeler.

Finally, Liang and Campbell [12] concentrated on imple-menting and simulating ACSI in J-Sim open-source simulator.Their goal was to explore security aspects of the standard andin particular of IEC 61850-7.

IV. DESCRIPTION OF THE TRAFFIC GENERATOR

The model of SV traffic generator developed during thisinvestigation is based on part 9-2 of the IEC 61850 standard[13], [14], and on IEC 61850-9-2 LE implementation guide-lines [15]. It was implemented in NS3 open-source networksimulator, version 3.8 [16]. NS3 was chosen out of manyother available simulators for two reasons: 1) it is open-source, hence it is possible to alter the core of the simulator ifnecessary; and 2) it features uniform coding structure, i.e., bothsimulation scripts and its core are written in C++ programminglanguage, hence there is no need to create language bindingsas is the case in NS2 for example (OTcl/C++ bindings).

Fig. 3 depicts a conceptual model of the traffic generatorin the spirit of OSI-7 reference model. The generator nodeis responsible for generating packets carrying SV protocol(or simply SV packets) while the sink node acts as theiraddressee. Both nodes implement 3 out of 7 OSI layers asrequired by [14]: application, data link, and physical layer.The functionality of the application layer is implemented bySV Publisher application in the generator node, and by SVSubscriber application in the sink node. The functionality ofthe data link layer is split into two parts: VLAN Interface andFDEthernet sublayers; while the functionality of the physicallayer is implemented by FDChannel. VLAN Interface andFDEthernet sublayers together with FDChannel model thebehaviour of full-duplex Ethernet with IEEE 802.1Q support,

i.e., payload coming from upper layers is encapsulated insidethe Ethernet-II (EtherType) type framing with VLAN tagging.

All parts of the traffic generator were fully designed andengineered in the simulator in order to gain first-hand experi-ence in working with the standard. Moreover, since the mainaim was to create a realistic traffic generator, as packets goup/down the protocol stack appropriate headers and trailers areappended/removed on a layer basis similarly to show how itoccurs in a real communication scenario.

A. SV Publisher/Subscriber Application

Every SV packet is created by SV Publisher application, andupon creation consists of a series of SV ASDUs encapsulatedinside the SV APDU. The byte structure of SV APDU andSV ASDU implemented in the model is based on the AbstractSyntax Notation One (ASN.1) and Basic Encoding Rules(BER) Type-Length-Value (TLV) triplets specified in [14].The structure is shown in Fig. 4. At present, the model ofSV APDU/ASDU does not include any of the optional TLVtriplets, i.e., datSet, refrTm, smpRate and smpMod. Moreover,the majority of the implemented triplets have their Value fieldsset to 0 or an arbitrary value to simply preserve the struc-ture of SV APDU/ASDU rather than carry any meaningfulinformation. Future work will involve adding optional triplets,and setting Value fields to something more meaningful as theSV traffic generator will be improved, and models of otherprotocols such as GOOSE/GSSE will be added.

SV-specific header is appended to SV APDU before it issent down the protocol stack to lower layers. The headeris 8 bytes long and comprises 4 fields: APPID, Length,Resrv1, and Resrv2 (see Fig. 5, topmost packet structure).The APPID field stands for Application Identifier [14], andis used to select those Ethernet frames which contain SVAPDU, and to distinguish between GOOSE/GSSE and SVprotocols. APPID is always 2 bytes long and in case of SVprotocol has the two most significant bits (MSBs) set to 01,while the remaining 14 bits are the actual ID used within thesubstation communication network. Therefore, the values ofAPPID range from 0x4000 to 0x7FFF. By default, it shouldbe set to 0x4000.

The Length field is also 2 bytes long, and indicates thelength of the packet including the SV-specific header, i.e., if

APPID Length=m+8 Resrv1 Resrv2 APDU Padding

PayloadEtherType= 0x88BA

VLAN TCI

PayloadVLAN TPID= 0x8100

MACSrc

MACDst FCS

2 2 2 2 46-(m+8)m bytes

2 2

6 6 2 4

Applicationlayer

VLAN Interfacesublayer

FDEthernetsublayer

Fig. 5. Encapsulation of SV APDU as it goes down the protocol stack

the length of the APDU is m bytes and since the length ofthe SV-specific header is 8 bytes, Length field shall be set tom + 8.

The Resrv1 field stands for Reserved 1. It is 2 bytes long,and features a set of blocks of bits each serving differentfunction. The MSB, if set to 1, indicates that this SV packethas been issued by a test device. The following 3 bits arereserved for future standardised application, and by default,are set to 0. The remaining 12 bits are reserved for securitypurposes, and by default, should also be set to 0x000. TheResrv2 field stands for Reserved 2. It is 2 bytes long, and isused to denote additional security parameters carried by thisSV packet. By default, it should be set to 0x0000.

In our model, APPID and Resrv2 fields assume their defaultvalues, that is APPID is set to 0x4000 and Resrv2 to 0x0000.Resrv1 field is set to 0x8000 to indicate that packets were gen-erated by a test device. Length field is updated automaticallybased on the actual length of SV APDU. If the total length ofthe packet (SV APDU + SV-specific header) is smaller than 46bytes, SV Publisher application will pad it with zeros in orderto ensure that it conforms with the requirements of Ethernet,i.e., the minimum length of the payload encapsulated insidethe Ethernet frame must not be smaller than 46 bytes.

The SV Subscriber application on the other hand actsas a simple sink for SV packets. It basically removes SV-specific header and padding (if any) from a packet which wasforwarded up to the application by VLAN Interface sublayer.

B. VLAN Interface Sublayer

A VLAN Interface sublayer was designed to imitate thebehaviour of an IEEE 802.1Q VLAN-aware end station/device,i.e., a network node which is capable of explicitly VLANtagging the frame before it is ever sent out [17]. It is clearlystated in [14] that frames carrying SV APDU have to beVLAN tagged explicitly. The main task of this sublayer isto append/remove VLAN Tag Control Information (TCI) andEtherType field to/from the packet received from upper/lowerlayer (see Fig. 5, middle packet structure). The VLAN TCIcomprises three fields [17]: Priority, Canonical format indi-cator (CFI), and VLAN ID.

The Priority field is 3 bits long, and is used to denote thepriority which the frame should be treated with when travellingthrough priority-aware switched Ethernet network. Its value

can range from 0 to 7 according to IEEE 802.1p. There areno strict rules as to how those values should be distributedamong different types of traffic but, by default, for SV-typepayload, priority should be set to 4 [14].

The CFI field is one bit long, and in general, refers to the bitordering format of the bytes within a frame. Its precise mean-ing however depends on the underlying technology (Ethernet,Token Ring, etc.). In Ethernet networks, frames are normallysent with CFI bit set to 0.

The VLAN ID field is 12 bits long, and is used to explicitlyidentify frame’s VLAN association. For SV-type payload, if noVLAN segments were configured, it should be set to 0x000[14]. Otherwise, since SV protocol needs to have potentially itsown bandwidth allocation, it should be set to a value differentfrom the one used by GOOSE/GSSE protocols.

The value of each of the VLAN TCI composite fields isdetermined at the application layer, hence in this case bySV Publisher application, and is passed to VLAN Interfacesublayer together with the pointer to SV packet and the valueof EtherType field. The model assumes the following defaultvalues: Priority set to 4, CFI to 0, and VLAN ID to 0x000. TheEtherType field which uniquely identifies the payload/protocolcarried within the Ethernet frame is set to SV Protocol ID, thatis 0x88BA.

When the packet is received from the lower layer, the VLANInterface sublayer removes VLAN TCI and EtherType field.It then inspects the removed EtherType field and comparesit with the SV Protocol ID. If the two match, the packet isforwarded up the protocol stack to SV Subscriber application.Otherwise, the packet is dropped at this sublayer. This mecha-nism was developed to ensure that only VLAN tagged framescarrying SV-type payload are forwarded up to SV Subscriberapplication.

C. FDEthernet Sublayer

The FDEthernet sublayer was designed to imitate thebehaviour of full-duplex Ethernet network interface card.Therefore, its main functions include: enqueueing/dequeueingframes for transmission over FDChannel; appending/removingdestination and source MAC address fields, and VLAN TagProtocol Identifier (TPID) field to/from the frame goingup/down the protocol stack (see Fig. 5, lowermost packetstructure); and calculating and appending/removing the FrameCheck Sequence (FCS).

The value of VLAN TPID (i.e., VLAN Protocol ID,0x8100) is provided to FDEthernet sublayer by VLAN In-terface together with the pointer to payload. When packetis received from lower layer, i.e., FDChannel, and passeschecksum control, FDEthernet sublayer forwards the frameup the protocol stack only if the third field of the Ethernet-II header (i.e., EtherType field if no VLAN tagging is em-ployed) matches the VLAN Protocol ID. Otherwise, the packetis discarded at this sublayer. This mechanism ensures thatonly VLAN tagged frames are forwarded to VLAN Interfacesublayer.

Figure 2.14: Structure of modelled SV APDU/ASDU & its encapsulation in Ethernet[24]

In order to be able to build the first merging units, a lite edition of IEC 61850-9-2 was

created by UCA International Usersgroup and called IEC 61850-9-2LE. This lite edition,

which is regarded as an implementation guideline, specifies two profiles for the exchange

of sampled values [21].

• Protection: For protection purposes 80 samples per nominal system frequency

(50Hz - Europe) are gathered. A set of samples consists of 4 current (phase A,B,C

& N) and 4 voltage (phase A,B,C & N) samples, which are send at once in one

ASDU within the APDU at a rate of 250 µs.

• Metering: For metering purposes 256 samples per nominal system frequency are

gathered. Each ASDU consists of one set of samples and 8 ASDUs are sent within

one APDU. Thus every 625 µs a Ethernet frame is sent.

2.5 Related Work

Concerning the three fields power system protection, real-time systems and ethernet-based

real-time protocols, in each of those domains quite substantial research has been per-

formed. Before going into detail of those, the author likes to point out that the EPFL in

Switzerland has published a research proposal, which deals with the ”Design of a Reliable

Controller for Smart Grids” [36]. This research proposal involves exactly the above men-

tioned research fields.

For the sake of this thesis the research, performed in the area of directional overcur-

rent and earth fault protection, is of importance. In [46] challenges for directional relays

are stated, which arise under certain power system conditions, and some improvements

are proposed. In [14] the working group D-3 of the IEEE Power System Relay Committee

describes an approach based on virtual polarisation for directional relays. This approach is

22

very applicable for high resistance faults, for which the polarising voltage is usually quite

low in magnitude. Therefore it is partially implemented for the directional element of the

earth fault protection (see 4.2.3). Furthermore in [18] a new algorithm for ground fault

phase selection has been introduced, which is applicable in case of a weak-infeed. This

weak-infeed situation is usually given in case of a high penetration of renewable energies

and therefore will have more and more importance in the future. Thus the described

algorithm is also implemented for the phase selector element (see 4.2.5).

Concerning real-time systems [25] analysis the di↵erent scheduling algorithms and their

benefits and drawbacks. In [29] the importance of detailed schedulability analysis is de-

scribed, in order to achieve a feasible scheduler. Since a power system protection system

has to run stable for long life time (� 20 years), the ageing problematic of linux operating

systems is analysed in [13] and their e↵ects are stated.

In case of Ethernet based real-time protocols there are many IEEE papers found, which

analyse the performance of either EtherCAT [37], [40] or IEC61850-9-2 [16], [35], [32].

In [37] and in [40] the performance of EtherCAT and its application in the industry is

analysed. Moreover in [12] the IgH EtherCAT Master (see [39]), which will be used in this

thesis, is evaluated. [12] states that the IgH EtherCAT Master provides a maximum cycle

time of 250 µs with a jitter of 13 µs. In [16] protection schemes based on Sampled Val-

ues are tested. Moreover [35] deals with performance of IEC 61850-9-2 and its corrective

measure for digital relaying.

A direct comparison between GOOSE protocol, specified in the IEC 61850 standard, and

the EtherCAT fieldbus protocol is made in a conference [15]. This paper claims, that

the EtherCAT protocol outperforms the GOOSE protocol in terms of transfer-time and

deterministic behaviour. None the less, a direct comparison between the IEC 61850-9-2

SV protocol and EtherCAT has not been found.

23

Chapter 3

Methodology

The applied methodology for the development of the directional overcurrent and earth

fault protection is mainly based on a model-based design approach. The input to this

approach are the requirements of the system to be developed. Therefore the model-based

design as well as the requirements of the corresponding protection functions are explained

below. Moreover the selection of specific target system as well as the selection of a suitable

Ethernet based real-time protocol is described.

3.1 Model-based Design

Model-based design is an e�cient and cost-e↵ective development process for embedded

software systems. This process is applicable to the well-known V-model of software devel-

opment as shown in figure 3.1. Model-based design approach starts from the requirements

specification through the design phase, implementation and lastly the testing [34].

Implementa)on+

Tes)ng+Design+Phase+

Define+

Requirements+

Modeling+of+Power+System+

&+IED++

Model@in@the@Loop+

Code+Genera)on+

SoDware@in@the@Loop+

Hardware@in@the@Loop+

Complete+Integra)on+&+

Test+

Figure 3.1: Model-based design is applicable to V-model

Define Requirements: At the beginning of each development process the requirements

24

for the developed product has to be analysed and specified (see 3.2). Those requirements

are usually provided by international standard organisation like IEC or ANSI [30].

Design: Based on the specified requirements the first model is build. There will be plant

(e.g. power system) and controller (e.g. IED) model in order to test the designed pro-

tection function based on model-in-the-loop (MiL) simulation. Testing during the design

phase has the significant advantage that potential defects are found at a very early de-

velopment stage and therefore can be solved in a cost-e↵ective manner (see figure 3.2). [34]

Implementation: Once the model-in-the-loop simulation has been successful completed,

the code for the protection function is generated. In order to generate e�cient and e↵ec-

tive code the architecture of the processor as well as the operating system of the target

system have to be specified (see 3.4). Moreover some recommendations for the usage of

Simulink are given in the appendix in order to obtain e�cient C-code.

Testing: After the implementation phase the comprehensive testing phase begins. This

phase mainly consists of the software-in-the-loop (SiL) and hardware-in-the-loop (HiL)

simulation. During SiL the generated code of the protection function is embedded in the

simulation environment. Thus the inputs (e.g. sampled values) can be provided to protec-

tion function by the simulated power systems. If the SiL simulation is successful, it can

be derived that the code-generation process has been performed correctly as well. This

process is regarded as code verification and validation. The results of the software-in-the-

loop simulations are shown in section 5.2.1. [34]

In the next step the hardware-in-the-loop phase is executed. HiL means that the gen-

erated code has been deployed on the target system and the power system is simulated

on a real-time simulator, which provides its measurements either as analog values or as

Sampled Value stream via the network. Thereby it is important that the simulated envi-

ronment (e.g. power system) runs at least 10 times faster than the controller (e.g. IED).

Nevertheless as part of this thesis the measurements, which are usually provided by the

real-time simulator, are provided by a signal generator (e.g. Omicron). In order to test the

conformance of the protection function to the requirements a type test for the directional

overcurrent as well as earth fault protection is conducted as part of the HiL. The test

results are shown in section 5.3 and 5.2.2.

Considering the model-based design approach, described above, the Matlab/Simulink en-

vironment is chosen to develop the protection function. This decision has been made

based on the fact that Matlab/Simulink can be used to carry out the entire model-based

design process within one application. The design phase is executed by the simulation

environment together with the vast supply of di↵erent libraries. Then the Simulink Coder

takes care of the implementation phase, followed by the testing.

25

Requirements+ Design+ Implementa2on+ Tes2ng+

Model7based+design+ SEI+7+industry+average+

Def

ect D

isco

very

Figure 3.2: Number of defects found shifts to earlier stage of development process [30]

3.2 Requirements for protection relays

As shown above the requirements are the input to the model-based design development

process. Therefore the functional requirements as well as the environmental requirements,

in terms of electromagnetic compatibility as well as vibration and shock resistance of a

protection system are explained. Nevertheless this thesis focuses rather on the functional

performance than on the environmental constraints.

3.2.1 Functional requirements

The IEC technical committee 95, which is responsible for the standard IEC 60255, has

planned to publish the functional requirements for a directional overcurrent relay in the

IEC 60255-167. Nevertheless at the point in time of the thesis, this part of the stan-

dard has not been released yet. Thus the functional requirements are based on a normal

overcurrent protection stated in the IEC 60255-151, which includes earth fault protection

as well. There is also a standard (IEC 60255-12) from 1980 for directional relays in general.

In section 2.2.2 the general setup of a protection system has been evaluated. Consid-

ering the operating characteristic of an overcurrent relay, the standard specifies two types

[2].

• independent time characteristic (i.e. definite time delay)

• dependent time characteristic (i.e. inverse time delay)

The point in time, when the current value crosses the threshold setting value GS until

the trip outputs become true, is regarded as the operate time top and it is given by the

26

time characteristics, which is shown in figure 3.3. The figure shows an independent time

characteristic with a definite time delay, since this is the implemented time characteristic

in this project. In the figure only one stage is shown. In most overcurrent functions two to

four stages are found. The current value is given by the measuring principle (see section

2.2.2). In this thesis it will be the RMS value of the 50 Hz component. Nevertheless the

implementation of the trueRMS value as well as the dependent time characteristic are still

on the author’s to-do-list. Nevertheless the 50 Hz RMS value as well as a definite-time

characteristic is a common approach for a directional overcurrent protection. – 10 – 60255-151 © IEC:2009

t(G)

G Gs

top

Figure 2 – Overcurrent independent time characteristic

For undercurrent relays, t(G) = top when G < GS. The independent time characteristic is presented in Figure 3.

t(G)

G Gs

top

Figure 3 – Undercurrent independent time characteristic

4.4.1.3 Dependent time characteristics

Dependent time characteristics are only defined for overcurrent relays.

For dependent time relays the characteristic curves shall follow a law of the form:

⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢

⎣

⎡

+

−⎟⎟⎠

⎞⎜⎜⎝

⎛= c

GG

kTMSGt

1

)(

S

α (1)

where

t(G) is the theoretical operate time with constant value of G in seconds;

k, c, α are the constants characterizing the selected curve;

G is the measured value of the characteristic quantity;

IEC 1706/09

IEC 1707/09

For ABB use only . Publication provided under IEC subscription agreement 2013 - 2014. This file is copyright of IEC, Geneva, Switzerland. All rights reserved.

Figure 3.3: Independent time characteristic [2]

Next to the operate time, the start time is another important value to consider. The start

time is the duration from the instance the fault occurs the in power system until the start

signal occurs. This value is mainly influenced by the communication solution between the

I/Os and the relay as well as the applied measuring principle (e.g. DFT).

The ”opposite” of the start time is the disengaging time, which is defined as the period

of time between the instance the fault disappears and the operate signal of relay becomes

false. This duration is usually influenced by the same factors as the start time. All those

di↵erent time characteristics are depicted in figure 3.4 for clarity.

Moreover the standard IEC 60255-151 requires not only a definite operating time, but

also a corresponding reset characteristic. This is important in order to be able to assess

the behaviour of the protection system for repetitive faults. The reset time is the du-

ration between the instance the fault disappears in the power system and the point in

time the relay resets its internal time delay counter, as shown in figure 3.4. Similar to

the time characteristics the standard provides di↵erent options for implementing the reset

characteristics [2].

• No intentional delay on reset

• Definite time reset characteristic

• Dependent time resetting

27

The first option with no intentional delay on reset can be used for the definite-time as well

as dependent-time characteristic. Nevertheless the other two reset characteristics must

be used according to their time delay characteristics. Therefore the definite time reset

characteristic, shown in figure 3.4, is chosen for this project.

60255-151 © IEC:2009 – 13 –

The manufacturer shall declare if compensation of the internal measurement time (disengaging time) is included in the reset time.

4.4.2.2 No intentional delay on reset

For G < (reset ratio) × GS, the relay shall return to its reset state with no intentional delay as declared by the manufacturer. This reset option can apply to both dependent and independent time relays.

4.4.2.3 Definite time resetting

Generally, this reset characteristic is applicable to overcurrent protection.

For G < (reset ratio) × GS, the relay shall return to its reset state after a user-defined reset time delay, tr. During the reset time, the element shall retain its state value as defined by

( ) tGt

t

d1P

0∫ with tP being the transient period during which G > GS. If during the reset time period,

the characteristic quantity exceeds GS, the reset timer tr, is immediately reset to zero and the element continues normal operation starting from the retained value.

Following G > GS for a cumulative period causing relay operation, the relay shall maintain its operated state for the reset time period after the operating quantity falls below GS as shown in Figure 5. Alternatively, the relay may return to its reset state with no intentional delay as soon as the operating quantity falls below GS after tripping as shown in Figure 6.

This reset option can apply to both dependent and independent time elements. A graphical representation of this reset characteristic is shown in Figures 5 and 6 for partial and complete operation of the element.

tr

Operatesignal

Start (pick-up)signal

TrippingValue of internal time delay counter

Time delay setting

Energising quantity > Gs

Reset time setting

Start time

Reset time Reset time

Disengaging time

tr tr tr

Figure 5 – Definite time reset characteristic

IEC 1709/09


Figure 3.4: Definite time reset characteristic [2]

Furthermore the standard IEC 60255-151 requires a performance specification of the de-

veloped overcurrent protection. Those specifications comprise the accuracy of the char-

acteristic quantity G (e.g. current 50 Hz RMS value), operate time, reset time as well as

the transient performance. The procedure, on how these tests are performed, as well as

the results are found in section 5.3.

Since the standard IEC 60255-167 for the directional overcurrent function has not been

released yet, there are no suitable requirements on the directional element.

3.2.2 Environmental requirements

The environmental requirements comprise di↵erent aspects, such as electromagnetic com-

patibility, vibration and shock resistance, ambient temperature, solar radiation etc. None

the less this thesis focuses on the EMC performance of the I/O modules. The other aspects

of the environmental requirements are stated, but not evaluated.

The EMC performance can be divided into emission and immunity. The emission as-

pect deals with the radiation of the electro magnetic waves of the equipment under test

itself. From the point of view of immunity the equipment under test is subject the exter-

nally applied electromagnetic force and its performance is evaluated. This thesis focuses

in the latter.

28

The general EMC requirements are tackled by the IEC 61000-6-5 in case of high voltage

substation and power station applications. The more specific EMC requirements for re-

lays and communication equipment in the substation environment are described in the

IEC 60255-26 and IEC 61850-3, respectively. The general EMC requirements, stated in

IEC 61000-6-5, are used in this project due to its better comparability to the IEC 61000-

6-2, which comprises the general electro magnetic compatibility of the used EtherCAT

components.

According to IEC 61000-6-5 there are a couple of important electromagnetic phenomena,

as shown in table 3.1, which are grouped into continuous phenomena, transient phenom-

ena with high occurrence and transient phenomena with low occurrence. Depending on

the implemented function, di↵erent performance levels have to be fulfilled for those three

groups of electromagnetic phenomena [19].

Performance criterion A: The equipment under test (e.g. EtherCAT slaves) must

perform error-free during and after the applied electromagnetic phenomena.

Performance criterion B: The equipment under test must perform error-free after

the applied electromagnetic phenomena.

Performance criterion C: The equipment under test may stop operating as intended

temporarily. None the less the function has to be self-recoverable or restorable by an

operator [19].

In case of protection functions the performance criterion A has to be fulfilled for all

three groups of electromagnetic behaviour. That means that the developed protection

system has to operate during as well as after the test. Only for certain functions, such as

Human-Machine-Interface, lower performance criterion, like B and C, are allowed.

29

Continuous

phenomena

Transient phenomena

with high occurrence

Transient phenomena

with low occurrence

Voltage variations: Voltage dips: 0.02s Voltage dips: > 0.02s

- a.c. power supply - a.c. power supply - a.c. power supply

- d.c. power supply - d.c. power supply - d.c. power supply

Harmonics, interharmonics Voltage fluctuations Voltage interruptions:

Signalling voltages Fast transient/burst - a.c. power supply

Ripple on d.c. power

supply

Damped oscillatory/ring

wave

- d.c. power supply

Power frequency variation Damped oscillatory mag-

netic field

Short duration power fre-

quency variation

Conducted disturbances in

the range 2 kHz to 150 kHz

Electrostatic discharge Surge

Conducted disturbances in

the range 1,6 MHz to 30

MHz


quency voltage

Power frequency magnetic

field (according to IEC

61000-4-8)


quency magnetic fields (ac-

cording to IEC 61000-4-8)

Radiated, radio frequency

electromagnetic field

Radiated pulsed distur-

bances

Conducted disturbances,

induced by radio-frequency

fields

Mains frequency voltage

(according to IEC 61000-4-

16)

Table 3.1: Characterisation of the electromagnetic phenomena [19]

The exact EMC test, which have to be performed in order to satisfy the immunity require-

ments, are stated in the evaluation section 5.5. The magnitude of the applied test values

depend on the intended location of the equipment under test. The figure 3.5 shows those

di↵erent locations, which are found in a substation environment.

30

– 16 – IEC 61000-6-5:2015 © IEC 2015

Process area

Control room area

HV area

Interface area

4

3

3

Outside

area

22

4 4

3

24

Protected area

2

1

IEC

Key

Interface types

1 Inside protected area

2 Inside interface and/or control room area

3 Inside or from process area

4 Connections from outside (HV and external telecommunication)

NOTE

The control room area contains control systems, computers, fire fighting systems, UPS, etc.

The process area contains mainly MV systems (if available) with circuit breakers and MV-bus bars.

The protected area contains for example special sensitive equipment like routers, special computers, etc.

The interface area contains equipment and systems connected to the outside with measures like surge protection

and bonding of cable shields.

The outside area contains for example control centres.

The HV area contains GIS, earthing bus bars, transformers, etc.

Figure 4 – Example of the situation of a gas-insulated substation (GIS)

5 Performance criteria

The performance criteria are closely related to the nature of the electromagnetic phenomena

(types and occurrence), as given in Table 1 and to the applicable representative functions of

the equipment concerned.

Table 2 lists the suggested performance criteria to be applied for the corresponding function

of equipment. A functional description and a definition of performance criteria, during or as a

consequence of the EMC testing, shall be provided by the manufacturer and noted in the test

report, based on one of the following criteria, for each test as specified in Table 3 to Table 10.

a) Performance criterion A: The EUT shall continue to operate as intended during and after

the test. No degradation of performance or loss of function is allowed below a

performance level specified by the manufacturer, when the EUT is used as intended. If the

performance level is not specified by the manufacturer, this may be derived from the


Figure 3.5: Di↵erent EMC requirements for corresponding areas within a substation [19]

Locations:

1. Inside interface and/or control room area

2. Inside interface and/or control room area

3. Inside or from process area

4. Connections from outside (HV �36 kV and external telecommunication)

As stated in the introduction of the thesis, only the I/O modules are placed in the high

voltage environment indicated by the number 4. Moreover the control PC is run in a

”protected” area with less harsh EMC requirements indicated the capital letter 1. There-

fore in section 5.5 only the high voltage location is considered, when evaluating the EMC

performance of the EtherCAT modules.

Moreover the environmental requirements not only cover the electromagnetic compati-

bility, but also the vibration and shock resistance as well as ambient temperature and

altitude. The table 3.2 shows the normal environmental conditions, which are required by

the IEC 61850 standard for communication equipment used in a substation. There are

special environmental conditions stated in the standard for harsher environments. Never-

theless the normal environmental conditions shown below are considered as reference for

this project.

31

Environmental parameters Conditions

Ambient temperatureUpper limit +55�C

Lower limit � �10�C

Solar radiation Negligible

Altitude 2 000m

Air pollution (dust, smoke, vapours, etc.) No significant pollution

Relative humidity (24 h average) From 5 % to 95 %

Vibration, earth tremors According to IEC 60255-21 (class 0 or 1)

Electromagnetic disturbances Defined by specified location (see below)

Table 3.2: Normal environmental conditions [20]

Concerning the vibration and shock requirements the IEC 60255-21 has to be satisfied for

equipment used for protection purposes in substation environments.

3.3 Selection of communication solution

In section 2.4 two important real-time ethernet based protocols have been described,

namely EtherCAT and IEC61850-9-2 (Sampled Values). EtherCAT has mainly been de-

signed for industrial process applications and is characterised by its highly deterministic

behaviour as well as its fast cycle times. The disadvantage of EtherCAT is the single head

of communication, since only one EtherCAT master receives the measurements from the

EtherCAT slaves. On the other hand IEC61850-9-2 is the communication standard for

sampled based measurement values in the substation domain as well as has the advantage

that the sampled value packets can be sent to multiple subscribers via multicast. The

disadvantage of IEC61850-9-2 is the less deterministic behaviour, especially during high

tra�c rates.

Since one important objective of this thesis is, that the developed protection system is

based on COTS components, the EtherCAT communication solution is chosen as the link

between the power system and the protection logic on the target system (PC). At the

point in time of the thesis EtherCAT components are widely available on the market in

comparison to respected merging units, which are needed for IEC 61850-9-2.

Moreover the protocol stack for the EtherCAT master is freely available under the terms

of the GNU General Public License GPL, version 2. The IgH EtherCAT Master 1.5.2 is

used in this project [11]. The detailed features of the chosen EtherCAT Master are found

in section 4.3.2.

32

3.4 Selection of real-time system

The target system, on which the protection algorithm runs as a kernel module, is a real-

time system with the components stated in section 2.3. Therefore the selection of the

corresponding hardware as well as software in terms of kernel, Linux distribution and

EtherCAT Master is discussed.

3.4.1 Hardware

The required hardware for the real-time system can be divided into computer- and communication-

related hardware, as shown below.

Computer: Considering the hardware selection of the target system there is vast va-

riety of di↵erent components to choose from. In order to have a rough guideline to select

proper hardware, some considerations are made. The developed protection function is run

as multi-threaded process. Therefore a multi-core architecture of the processor is proposed

in order to yield the maximum e�ciency due to hardware-based multithreading. Never-

theless the actual benefit of this approach has to be evaluated later, since the increase

in performance is limited by the sequential fraction of the application (Amdahl’s law).

This might be of interest, when it comes to protection of multiple bays. Furthermore

the communication between the di↵erent threads should be performed mainly in the pro-

cessors’ caches rather than in the memory [33]. The bandwidth of reading and writing

in the level 3 cache (used for inter-core communication in case of INTEL processors) is

faster than in the memory. Thus a large level 3 cache is picked (e.g. � 4 MB). Moreover a

bandwidth of 100 Mbit/s (up/down-link) of the NIC for EtherCAT is seen as su�cient [11].

Under consideration of the above circumstances the following hardware for the target

systems has been chosen in table 3.3:

33

Processor Number i7-2760QM

Instruction Set 64-bit

Level 1 cache 32 kByte



Number of cores 4

Processor Base Frequency 2.4 GHz

Memory 4 GB

Network interface card Intel PRO/1000 Gigabit-Ethernet

NIC-Connector RJ-45

PCI-BUS PCI Express chipset

Table 3.3: Hardware configuration of target system

The figure 3.6 shows the used quad-core architecture as schematic overview. It can be

seen that the level 1 and 2 caches are individual for each processor core, whereas the level

3 cache is accessed by all four cores. Furthermore each physical core has only one logical

core due to the fact that hyper-threading is not used. Since hyper-threading introduces

random latency and deterministic behaviour is of major concern, this feature is disabled

in the BIOS. Moreover the NIC is connected via the PCI-bus.

Figure 3.6: Quad-core architecture without hyper-threading

Communication: The communication-related hardware consists of the EtherCAT cou-

pler and slaves as well as the communication medium itself. As described above, a com-

munication medium based on fiber optics (e.g. 100BASE-FX) is recommended for the

34

substation environment. Since this project is regarded as a proof-of-concept, a copper

based communication medium is used, in particular 100BASE-TX with RJ-45 connectors.

Besides the EtherCAT coupler (e.g EK1100), the following EtherCAT slaves are needed

for the application of this project:

• Digital Input: potential-free (e.g EL1034)

• Analog Input: 3xVoltage, 3xCurrent, oversampling (e.g. EL3773)

• Relay Outputs: Circuit breaker contacts (e.g. EL2624)

• Digital Outputs: Tracking di↵erent signals, like Pick-Up (e.g. EL2798)

The EtherCAT components are obtained from Beckho↵ and supplied by a 24 V-DC power

supply. The detailed datasheets are found in the appendix. At this point it is already

mentioned, that the current inputs of the EL3773 are not comparable to the current inputs

of common IEDs. The maximum permitted overcurrent of the EL3773 equals 1.2 A (RMS).

Current inputs of IEDs currently available on the market can handle overcurrent of up to

100 A. This high ratings are needed, since the secondary currents during a short circuit

increase above 50 A and higher. Nevertheless a EtherCAT slaves with those high current

ratings is not found on the market.

3.4.2 Runtime Environment

The most important parts of the runtime system is the kernel as well as the EtherCAT

Master. Also a suitable distribution has to be selected. Moreover there are some libraries,

which have to be available as well. There is guideline in the appendix, which describes

the process of setting up the runtime environment.

Kernel: Linux is chosen as operating system, due to its open-source availability and

its wide support community. In order to achieve the required deterministic behaviour, the

open-source vanilla Linux-Kernel is chosen, which is patched with the preempt-rt patch.

In particular the kernel version 3.4.41 is used due to some constraints imposed by the

chosen EtherCAT master below. The normal mainline kernel has only limited real-time

capabilities. Therefore the rt-patch is used to reduce the non-preemptible sections and

add the following real-time features and to make the standard kernel fully preemptible

[22].

• Usage of mutexes instead of spinlocks

• Implementation of priority inheritance to avoid priority inversion

• Conversion of interrupt handlers into preemptible kernel threads

35

Before the Linux-Kernel is compiled, it has to be configured. The most important con-

figurations are found in the implementation part of the thesis (see section 4.3.1). The

Linux real-time scheduler are First-in-First-Out (FIFO) and Round-Robin (RR). The

FIFO scheduler always schedules the task with the highest priority. This task runs un-

til it completes or until it is preempted by a higher priority task. The RR scheduler is

very similar to the FIFO scheduler. The only di↵erence is that the tasks scheduled by

RR are time-sliced. That means that the running task is preempted after its time-slice

is exhausted and is placed in the expired-queue [22]. For the threads of the developed

protection algorithm the RR scheduler is used. In section 3.4.1 it is stated that a multi-

core architecture is beneficial for application with a high parallisable fraction. In order to

achieve this increase in performance, the corresponding scheduler policy has to support

this multicore approach. Nevertheless research has shown (see [38]) that the scheduler

classes FIFO and RR execute an active push-pull approach between the cores with a load

over 50%. This leads to unpredictability, which is tried to be avoided. Therefore the de-

veloped protection application is run with CPU a�nity, despite the multicore architecture.

Linux distribution: The selection of Linux distribution is made based on its main

function. There are many di↵erent linux distribution on the market. The figure 3.7 shows

a rough classification of the di↵erent linux distributions according to their purposes, such

as server applications, desktop or embedded systems. Since the protection system can

be best characterised by a server and the author is more familiar with Debian-based sys-

tems, Ubuntu Server would be most suitable. None the less some part of the development

process is also executed on the target system. Thus the Ubuntu desktop distribution is

chosen for this project. The server and desktop version mainly di↵er in terms of desktop

packages, such as X or GNOME and server related packages, like Apache2. Thus choosing

Ubuntu desktop over Ubuntu server should not influence the developed protection system.

In particular the The Ubuntu 12.04 LTS (Long Term Support) is picked as distribution,

since it uses kernel version, which are similar to the chosen 3.4 kernel. Therefore potential

integration issues are limited.

36

Figure 3.7: Overview of Linux distribution

EtherCAT Master: The head of the EtherCAT communication is the EtherCAT Mas-

ter, as described above. As part of this project, the open-source IgH EtherCAT Master

is used [39], which runs as a kernel module as well. This specific EtherCAT master in-

cludes a EtherCAT-capable native drivers. That means that the native driver operates

the hardware without the usage of interrupts, which increases the deterministic behaviour.

Currently the IgH EtherCAT Master together with the native driver approach only sup-

ports certain hardware (e.g. Intel PRO/1000 Gigabit-Ethernet chipsets) and linux kernels

(<3.4) [39]. Those constraints are considered during the selection process of the hardware

and the runtime system above.

3.5 Specified development procedure

Under consideration of the model-based design approach as well as the stated require-

ments, the figure 3.8 depicts the specified development procedure of the protection system

based on COTS components. The design and implementation phase is executed in the

development environment. The setup of the runtime and development environment are

described in the appendix. The SiL testing is also performed in the development environ-

ment. Once the target system is set up and communication infrastructure is implemented,

the HiL testing is performed. Moreover a type test is performed, which is required by the

IEC standard. The results of this type test are compared against comparable IEDs from

ABB and Siemens. Lastly, a stability test is performed in order to evaluate the realtime

system in terms of determinism and long-term behaviour.

37

Testing

Proposed Approach

© ABB Group August 12, 2015 | Slide 4

Desktop Environment / Software-in-the-LoopSetup Target System

Power System

ProtectionAlgorithm

- Ubuntu 12.04.5 LTS- RT-Kernel 3.4.41- EtherCAT Master (IgH)

EtherCAT Infrastructure- EtherCAT Coupler- EtherCAT Slaves- Power Supply 24 DC- CAT-5 patch cables

Target Systeminstall on connect to

Protection Algorithm withEtherCAT communication

- Functional Performance Test

- Type Test according to IEC 60255-151

- Stability Test (Schedulability analysis, long-term test)

- Compliance to environmental requirements (EMC, …)

Adjustapplication for

EtherCAT com.

uploadto

OEM IEDscompare to ABB: REL670 2.0

Siemens: 7SJ82

Figure 3.8: Specified development procedure

38

Chapter 4

Implementation

This chapter comprises the design and implementation phase of the model-based design

approach. First the architecture of the protection system is discussed, followed by a detail

description of the implemented protection algorithm itself. Lastly, the configuration of

the target system are evaluated in terms of kernel and EtherCAT master setup.

4.1 Architecture of Protection System

The architecture of the protection system is divided into two levels, namely process and

station level. The approach is that the input/output modules are separated from the

computer executing the protection function. This has the advantage that only the Ether-

CAT couplers and slaves have to fulfil the harsh environmental requirements, described

in section 3.2.2. On the other hand, the computer unit is located at a station level in a

protected area, with less environmental constraints. Nevertheless whether the chosen I/O

modules are complaint to the required EMC and vibration/shock standards is shown in

the evaluation section 5.5. Moreover this described architecture of the protection system

leads inevitably to a centralised approach.

The figure 4.1 depicts the chosen system design from a hardware, functional and logical

nodes perspective. The latter logical nodes perspective is just seen as functional descrip-

tion of the protection system. This does NOT mean that the actual data objects and

attributes, which are defined in the IEC 61850 standard, are implemented. The developed

definite-time directional overcurrent and earth fault protection are described by the logical

nodes PDOC and PDEF, respectively. The logical node PTRC describes the developed

trip element, which combines the trip outputs of the individual protection functions. The

voltage and current inputs are described by TVTR and TCTR respectively, whereas the

circuit breaker, seen by the relay outputs, is shown by XCBR. The logical nodes IHMI and

GLOG represent the human machine interface (HMI) and data logging service respectively.

Those two functions are not developed as part of this thesis. Instead an open-source Test-

manager and Data Logging Service, o↵ered by EtherLab, is used, which interfaces whith

39

the protection application via the protocol-independent PdCom library.

From the functional perspective it can be seen, that the protection function runs in the

kernel space of the RT-Linux system. This is important in order to communicate directly

with the native EtherCAT driver without the usage of system calls. Moreover analog

voltage and current values are provided by the signal generator Omicron in order to test

the system in HiL (see section 5.3 and 5.2.2).

I/OEtherCAT Coupler

EtherCAT Slave

HMIData logging

RT-Linux

NIC NIC

Linux-Kernel

NetworkDriver

NetworkDriver

EtherCAT Master

Kernel Modules

Application Layer

Realtime Modules

100BASE-TX

TCP/IP

Physical

Data LinkEtherCAT

C-FileProtection Function

Omicron

Compile...

Signal Generator

IHMI GLOG

PDEF PDOC

PTRC

TCTR TVTR XCBR

Hardware Perspective Function Perspective Logical Nodes Perspective

Figure 4.1: Centralised architecture of protection system

4.2 Protection Algorithm

4.2.1 Overview

The protection function consists of a definite-time directional overcurrent and earth fault

protection, as described above. In order to build up this functionality, di↵erent elements

are required based on the concept described in section 2.2.2 and depicted in figure 2.2.

Those elements are divided into signal processing elements, directional elements, phase

selector, overcurrent and earth fault protection, trip element and lastly the communication

driver and supervision blocks. Those elements are depicted in figure 4.2.

40

3xI

EL3773

3xV

EL3773

Communicationsupervision

Pre-process

ing

Pre-process

ing

Signal process-

ing

Signal process-

ing

PDOC

PDEF

Phase selector

PTRC

Relay outputs

EL2624

8 ms 1 ms1 msPeriod of task Period of task

Figure 4.2: Overview of protection algorithm

The application has a base sample time of 1 ms, which defines the period T of the task

(see section 2.3.2). At this time interval of 1 ms the scheduler has to run the application.

None the less the individual elements of the application (e.g. signal processing, phase se-

lector, etc...) can run at a multiple of this base sample time. The selection of the sample

time of the individual elements should not be performed randomly. For instance it is not

advisable to run the signal processing block at a slower speed than the protection function

itself. Moreover the tripping unit and the communication driver blocks should run at the

base cycle time in order to archive a high accuracy. In the figure 4.2 the signal processing

and the protection functions (PDOC, PDEF) run at sample time of 8ms.

In order to assure data integrity and determinism between to elements running at dif-

ferent sample times, either transition blocks or bu↵ers are implemented between those.

Depending on transition fast to slow or slow to fast the transition block implements a

Zero-Order-Hold or a Unit Delay, respectively.

In the following sections the implementation of each of the above stated elements are

described in detail. Moreover the configurable parameters, which can be set by the user,

are stated and explained at the end of each section. The base sample time timeBASE of

the application is set at a global level.

41

4.2.2 Signal Processing Element

Since the protection function (PDOC & PDEF) are based on phasor measurements, the

core function of the signal processing element is to calculate those phasors based on sam-

pled values. From a mathematical perspective a discrete Fourier-Transformation (DFT) is

implemented in order to convert the time-based signal into the frequency domain. Based

on the Fourier-Series each periodic signal f(t) can be described by a infinite number of

sin and cos waves as described by equation (4.1).

f(t) =a0

2+

1X

n=1

an cos(n!t) + bn sin(n!t) (4.1)

In the equation above n represents the rank of the harmonics. In this project the signal

f(t) represents the current or voltage signal of the power system. Since the focus lies

on European systems the fundamental component (n = 1) equals 50 Hz. Moreover the

magnitude and the phase of the harmonic n is obtained by the equations (4.2) and (4.3)

respectively.

|Hn| =p

a2n + b2

n (4.2)

\Hn = arctan⇣ bn

an

⌘(4.3)

Where

an =2

T

Z t

t�Tf(t)cos(n!t)dt

bn =2

T

Z t

t�Tf(t)sin(n!t)dt

T =1

f1=

1

50 Hz

(4.4)

The implemented Fourier transformation is based on the above equations. Nevertheless

since the computer environment is a discrete and not a continuous one, the equations are

slightly re-written below. The continuous signal f(t) is sampled at a discrete rate of 250 µs

(see section 4.2.7) using a running window. Thus the required 80 samples per fundamental

period is yield for protection purposes. This window F has a window size T of 80. The

implemented protection function only requires the fundamental 50 Hz component of the

signal. Therefore from now on n = 1. Moreover the continuous sin and cos waves are

represented by two row vectors, S and C respectively, comprising 80 discrete values. Now

the equation (4.4) is re-written in a discrete form below.

42

a1 =2

T

TX

i=1

Fi Ci =2

T

⇣F · C

⌘

b1 =2

T

TX

i=1

Fi Si =2

T

⇣F · S

⌘

T = 80 window size

i = corresponding element of row vector

(4.5)

The calculation in equation (4.5) is performed at each sample time of the signal processing

element psp. The signal processing element needs to run at least as fast as the fastest

implemented protection function. In addition the window F has to be updated with new

sampled values at each psp. Moreover the row vectors S and C have to be circulated by the

amount of new sampled values added to the window F . The number of newly added SV

is determined by the di↵erence in sample time between the signal processing element and

the fundamental sample time (1 ms). The figure 4.3 clarifies the above described process.

SV# SV# SV# SV#

1#

2#

3#

49#

50#

80#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

SV#

4 times oversampled at base cycle time of 1

ms

buffered

8 ms cycle time

1#

2#

3#

49#

50#

80#

1# 2# 3# 80#79#78#4# 5#

discrete cos wave samples

Row vector is circled by 32 samples each 8 ms

1# 2# 3# 80#79#78#4# 5#

discrete sin wave samples

Row vector is circled by 32 samples each 8 ms

Dot#Product#

Dot#Product#

2 80

2 80

Real Part

Imaginary Part

Figure 4.3: Implemented signal processing algorithm

The SV, marked in green, indicate the sample values, which are exchanged each 8 ms

(sample time of the signal processing element). Those updated SVs sum up to 32 (psp · 4).

Once the real and imaginary parts are yield, the phasor is constructed. Moreover the

PDOC and PDEF expect RMS values. Therefore the magnitude of the phasor is divided

43

byp

2. This signal processing implementation is executed on current as well as voltage

measurements for all three phases. Furthermore the symmetrical components of the three-

phase system are calculated based on the equations (4.6). Those components are essential

in the power system protection field, since many functions rely on those quantities.

U0 =1

3(Ua + U b + U c)

U1 =1

3(Ua + a U b + a2 U c)

U2 =1

3(Ua + a2 U b + a U c)

(4.6)

Where a represents the rotation operator of 120� (ej2⇡3 ).

Above implemented DFT is performed in the signal processing element itself. Never-

theless the pre-processing part prepares the running window F and provides it to the

signal processing element each 8 ms. Secondly, since the entire protection algorithm is

based on normalised values, the sampled values are also normalised in the pre-processing

element based on the given ratio of the instrument transformers as well as the base values.

Thirdly, an estimation of lost sampled values is implemented based on second order SV

estimation. Therefore three known sampled values SV0, SV1 and SV2 are used to define

the second order polynomial p2(tk) as shown in equation (4.7). tk is the point in time,

when the sampled value is lost.

SVk,est = p2(tk) = C0 SV0 + C1 SV1 + C2 SV2 (4.7)

Where

C0 =(tk � t1)(tk � t2)

(t0 � t1)(t0 � t2)= 1

C1 =(tk � t0)(tk � t2)

(t1 � t0)(t1 � t2)= �3

C2 =(tk � t0)(tk � t1)

(t2 � t0)(t2 � t1)= 3

The above constants are calculated based on three successful received SVs and a lost forth

SV. This SV estimation is used in case of lost and delayed EtherCAT frames. Nevertheless

a higher order polynomial could also been used in order to achieve a better estimation.

But this leads to a higher computational requirements. Thus there is a trade-o↵ between

accuracy of the estimation and computational demand. In the table 4.1 the configurable

parameters are declared and the developed signal processing block is shown in figure 4.4.

44

Figure 4.4: Developed signal processing block and mask

Name Default Min Max Unit Description

freq 50 50 60 Hz Fundamental frequency

ratio 1000 1 5000 - Ratio of instrument transformers

base 1000 1 106 A or V Base value of input quantity

initial 0 0 100 p.u. Initial output until window is filled

nrSV 4 1 10 - Oversampling factor

timePRE 0.001 0.001 1 s Sample time of input port

timeSP 0.008 0.001 1 s Sample time of signal processing element

Table 4.1: Settings for signal processing element

4.2.3 Definite-time Directional Overcurrent Protection - PDOC

Once the corresponding phasor measurements are calculated, the actual protection func-

tion can start performing its algorithm based on those data. The PDOC is divided into

directional sensing and threshold sensing based on a definite-time curve. The implemen-

tation of both elements is described in the following paragraphs. The developed PDOC

block and mask are shown in figure 4.5.

45

Figure 4.5: Developed PDOC block and mask

Directional element: Both protection function PDOC and PDEF comprise a direc-

tional element, which indicates the fault direction seen from the relay. Directional sensing

is important in order to enhance the selectivity performance of the protection system and

thereby increase the security objective (see section 2.2.1). This is especially important for

ring and meshed networks as well as for feeder protection with bi-directional power flow

due to a high infeed of distributed energy sources.

The directional element for the PDOC performs its directional decision on a per-phase

basis. Most directional sensing is based on the comparison of a polarising quantity with

an operating quantity. In case of the overcurrent protection the phase currents IA, IB and

IC are the respective operating quantities for each phase. Nevertheless the selection of

the polarising quantity is made based on its application. For example for the detection of

transient faults the individual phase voltages UA, UB and Uc would be chosen in order to

detect the direction of the fault. None the less low for low resistive faults UA, UB and Uc

tend to be very small and therefore can not provide any reliable information. Therefore

a common approach is to use the 90� connected phase directional element. That means

that the line-to-line voltages UBC , UCA and UAB are used as polarising quantities. This

has the advantage of reliable polarising measurements during single-phase and multi-phase

faults. None the less in this project a third approach has been implemented, which uses

the positive-sequence component U1 as polarising quantity. Considering table 4.2 below

the positive-sequence component is always available for all types of balance and unbal-

ance faults. The only exception is a three-phase fault in close proximity to the voltage

transformers.

46

3-Phase Faults Phase-Phase Faults SL-Ground

Ground No-Ground Ground No-Ground Ground

Quantity Close Far Close Far Close Far Close Far Close Far

U1 X X X X X X X X

U2 X X X X X X

U0 X o X o

Table 4.2: Available sequence components during di↵erent fault scenarios

In that case also U1 decreases to a very low value (see equation (4.6)) and is therefore not

reliable any more. If this type of fault occurs, then the memory voltage of the pre-fault

state is used to make a directional decision. The memory voltage can be used due to the

fact that the source is best described by a voltage source and therefore the phase of the

voltage changes only slightly during the fault state. The figure 4.6 depicts the operating

area of the directional element for four di↵erent stages.

Figure 4.6: Characteristic of directional element

The coloured areas are the operating areas for the four di↵erent stages, which are normally

+/- 90� from the polarising quantity. If the operating quantity is within this area, the

fault is indicated as forward. Normally this area is shifted by the angle of the positive

impedance of the line, also called maximum torque angle (MTA). The MTA for the above

characteristics is �60�.

The directional algorithm itself does actually not examine the angles directly. Instead

it calculates the active power according to equation (4.8). Therefore it is also regarded

47

as a wattmetric directional element. A forward fault is indicated by a positive sign and

reverse faults, vice versa.

PA = Re(V 1 · I⇤A,adj)

PB = Re(a2 V 1 · I⇤B,adj)

PC = Re(a V 1 · I⇤C,adj)

(4.8)

Where a is the 120� rotational operator, Z1,line is the positive line impedance and IA,adj ,

IB,adj and IC,adj is described by:

IA,adj = IA · 1\Z1,line

IB,adj = IB · 1\Z1,line

IC,adj = IC · 1\Z1,line

The table 4.3 shows the configurable parameters of the directional element.


enableDIR true true false - Enable directional element

angZ1 80 0 90 degree Angle of Z1,line

thresP67 0.5 0 10 p.u. Threshold of active power (PA,PB,PC)

thresV 0.1 0 1 p.u. Minimum polarising voltage (V1)

ringBUF 0.1 0.16 1 s Size of ring bu↵er for pol. quantity

Table 4.3: Settings for directional element of PDOC

Definite-time overcurrent element: Once the directional elements indicates the fault

in forward direction, the operating quantities IA, IB and IC are checked against a threshold

on a per-phase basis. Therefore four di↵erent stages can be set with the according delay

time. For the first stage the directional sensing can also be disabled. Furthermore a reset

time is implemented to reset the delay timer for each stage according to the IEC 60255-

151, as stated in section 3.2.1. Once the operating quantity exceeds the threshold, the

start signal is set to true and the timer starts. After the set time delay has expired, a

trip signal is issued and send to the trip element PTRC, which collects the trip signals

of all implemented protection function. The PDOC itself runs at a sample time of 8 ms.

Nevertheless the time delay function runs at the base sample time in order to achieve a

highly precise trip time. All implemented timer functions are based on 16bit-counters.

Thus the maximum setable time delay is 65 seconds, if the timer function runs at the

recommended base cycle time. The figure 4.7 depicts the characteristic definite-time curve

for the four stage overcurrent protection.

48

Figure 4.7: Definite-time curve of PDOC with 4 stages

The table 4.4 depicts the configurable parameters of the PDOC.


enableST1 true true false - Enable first stage

disableDIRst1 false true false - Disable dir. sensing (1.Stage)

thresIst1 50 0.5 100 p.u. Current threshold of first stage

delayST1 0.05 0 3 s Delay time of first stage

resetST1 0.05 0 3 s Reset time of first stage

enableST2 true true false - Enable second stage

thresIst2 50 0.5 100 p.u. Current threshold of second stage

delayST2 0.05 0 3 s Delay time of second stage

resetST2 0.05 0 3 s Reset time of second stage

enableST3 true true false - Enable third stage

thresIst3 50 0.5 100 p.u. Current threshold of third stage

delayST3 0.05 0 3 s Delay time of third stage

resetST3 0.05 0 3 s Reset time of third stage

enableST4 true true false - Enable forth stage

thresIst4 50 0.5 100 p.u. Current threshold of forth stage

delayST4 0.05 0 3 s Delay time of forth stage

resetST4 0.05 0 3 s Reset time of forth stage

timePDOC 0.008 0.001 1 s Sample time of PDOC element

timeTIMER 0.001 0.001 1 s Sample time of timer element

Table 4.4: Settings for the definite-time curve of PDOC

49

4.2.4 Definite-time Directional Earth Fault Protection - PDEF

The operating principal of the earth fault protection is very alike to the overcurrent pro-

tection. The di↵erence is the selection of the operating quantity. Instead of choosing the

phase currents, the PDEF takes the residual earth current into consideration (see section

2.2.4). There are di↵erent approaches for obtaining this residual earth current. If the

neutral point of the transformer grounding is accessible, a current transformer is placed

at this neutral point. Nevertheless this might not always be the case, therefore another

common approach is to use a current transformer for each phase and then use a Holmgreen

connection in order to obtain the residual current. Both approaches require a forth cur-

rent input for the analog inputs. Since the chosen EL3773 only has three current inputs,

a mathematical approach is used in order to obtain the residual current. Based on the

three-phase measurements the zero-sequence current I0 is calculated (see equation (4.6)).

Thus the residual current equals 3I0. The figure 4.8 depicts the developed PDEF block as

well as its corresponding mask for configurations.

Figure 4.8: Developed PDEF block and mask

Directional element: The principal of the directional element for the PDEF is similar

to the one of the PDOC. Nevertheless the selection of the polarising quantity is a bit

di↵erent. Table 4.5 shows the available symmetrical components during di↵erent ground

faults. It can be seen that all sequence quantities are involved in ground faults. None

the less the positive-sequence quantities should be avoided, since they are highly a↵ected

by normal load current. Thus it would be di�cult to distinguished between a high load

situation and fault situation.

50

Phase-Phase-Ground Faults Single-Line-Ground Faults

Quantity ......Close...... ........Far........ ......Close...... ........Far........

U1 X X X X

U2 X X X X

U0 X o X o

I1 X X X X

I2 X X X X

I0 X X X X

Table 4.5: Available sequence components during ground faults

Therefore the directional element is based on either the zero-sequence or the negative

sequence quantities (configurable by user). Both directional sensing methods use the

wattmetric approach described by the equations (4.9) and (4.10) respectively to distinguish

the fault direction. In case of an isolated star point, the reactive power is examined instead

the active power. This approach is also called sin(�) method and is justified by the fact,

that mainly capacitive fault current flows in case of single-line-to-ground fault. A positive

sign indicates the forward direction and vice versa.

P0 = Re(�3V 0 · 3I⇤0,adj)

Q0 = Im(�3V 0 · 3I⇤0,adj)(4.9)

P2 = Re(�V 2 · I⇤2,adj)

Q2 = Im(�V 2 · I⇤2,adj)(4.10)

Where

I0,adj = I0 · 1\Z0,line

I2,adj = I2 · 1\Z2,line

Z0,line is the zero-sequence line impedance and Z2,line is the negative sequence line impe-

dance. None the less Z2,line = Z1,line due to the fact that the faults are considered far

away from rotating machines (see section 2.2.4). Normally the zero-sequence components

are chosen as operating and polarising quantities for the directional element. None the less

in case of strong zero-sequence mutual coupling between two parallel circuits and isolated

zero-sequence sources at the same time, then the negative sequence components are chosen

in order to avoid miss-operation on the healthy lines.

The table 4.5 shows that the zero-sequence and negative sequence voltage might be very

low for far-away faults as indicated by the ’o’. This phenomenon is clarified in the figure

51

4.9, which shows the voltage profile for the negative-sequence and zero-sequence voltage

during a single-line to ground fault. It can be seen that voltage V2, measured by the relay

at bus G, is higher than 3V0, if a solidly grounded transformer is connected to the same

bus.

With 3V0 maximum at the fault, the value at a ground ing bank may be quitesmall. ZT o f the transf ormer is small becau se of the large bank, and Z0 of thelines is large because of distanc e and the +3Z1 factor . Modern ground relaydirection al units are quite sensit ive, so this may not pose a problem , unle sslong lines or settings are made well into the remot e adja cent lines.

12.22 DUAL POLARIZATION FOR GROUND RELAYING

A common practice is to use current and voltage polari zation jointly . Manyground relays are ‘‘dual polarized.’’ So me use two separ ate dir ectional units,one voltage p olarized and the other current polari zed. They operate in para llel,so that either one can release the overc urrent units. Other designs use a hybridcircuit, with o ne direction al unit that can be energized by current or voltage, orboth. Th ese types offer flexib ility of appl ication to variou s parts of the system.

12.23 GROUND DIRECTIONAL SENSING WITH NEGATIVESEQUENCE

An excell ent alternat ive is the use of negativ e sequence to opera te thedirection al unit. Zero- sequence 3I0 is still used for the fault- detecting over-current elements , with V2 and I2 for the directional unit. It is applicablegenerally, but is particularly useful at autotransformer stations, with prob-lems, as discussed earlier, and where mutual induction is involved, asdiscussed in Sect ion 12.24.

Source

Voltagesat relay

G

G

3V03V0

V2V2

H

H F

F

ZT

ZT

Z0GH

Z0GH Z0HF

Z0HF

FIGURE 12.18 Typical voltage profiles of V2 and 3V0 for ground faults.

! 2006 by Taylor & Francis Group, LLC.

Figure 4.9: Voltage profiles of V2 and 3V0 for ground faults[23]

In such cases either V2 and I2 are chosen as polarising quantities or virtual polarisation is

used as described by the working group D-3 of the IEEE Power System Relay Committee in

[14]. Virtual polarisation means that the faulty phase is not considered, when calculating

the zero-sequence voltage. This approach yields a high magnitude of the virtual zero-

sequence voltage V0,virt, which comprises reliable angle information. The requirement for

this approach is a high sensitive phase selector, which can distinct the faulty phase. The

table 4.6 depicts the di↵erent cases for virtual polarisation.

Phase Selector Virtual pol., 3 V0,virt

Phase A fault V B + V C

Phase B fault V A + V C

Phase C fault V A + V B

No selection V A + V B + V C

Table 4.6: Di↵erent cases for virtual polarisation [14]

The table 4.7 shows the configurable parameters for the directional element.

52


enablePDEFdir true true false - Enable directional element

isolNET false true false - Enable sin � method


thresP67N 0 0 10 p.u. Threshold of power (P0 or Q0)

thresV 0.1 0 1 p.u. Minimum polarising voltage (3 V0)

enableV2 false true false - Enable negative-sequence quant.


thresP67N 0 0 10 p.u. Threshold of power (P2 or Q2)

thresV 0.1 0 1 p.u. Minimum polarising voltage (3 V2)

Table 4.7: Settings for directional element of PDEF

Definite-time earth fault element: The earth fault protection element is based on

the same definite-time principal as described for the PDOC. The characteristic curve has

implemented a 4 stage definite-time curve, whereas the directional sensing can be disabled

for the first stage. The di↵erence to the PDOC is that the PDEF considers the residual

current 3I0 as operating quantity. Moreover the earth fault protection is more sensitive

than the overcurrent protection. Therefore the corresponding thresholds are chosen below

the base current values. The PDEF usually runs at slower sample time than PDOC. None

the less the time delay function runs at the base sample time in order to archive a high

accuracy.

The table 4.8 depicts the configurable parameters of the PDEF.

53


enable67NST1 true true false - Enable first stage

disable67Ndir false true false - Disable dir. sensing (1.Stage)

thres67NIst1 50 0.5 100 p.u. Current threshold of first stage

delay67NST1 0.05 0 3 s Delay time of first stage

reset67NST1 0.05 0 3 s Reset time of first stage

enable67NST2 true true false - Enable second stage

thres67NIst2 50 0.5 100 p.u. Current threshold of second stage

delay67NST2 0.05 0 3 s Delay time of second stage

reset67NST2 0.05 0 3 s Reset time of second stage

enable67NST3 true true false - Enable third stage

thres67NIst3 50 0.5 100 p.u. Current threshold of third stage

delay67NST3 0.05 0 3 s Delay time of third stage

reset67NST3 0.05 0 3 s Reset time of third stage

enable67NST4 true true false - Enable forth stage

thres67NIst4 50 0.5 100 p.u. Current threshold of forth stage

delay67NST4 0.05 0 3 s Delay time of forth stage

reset67NST4 0.05 0 3 s Reset time of forth stage

blockPDEF true true false - Block PDEF after s.p. tripping

thresSP 0.1 0 0.5 p.u. Thres. to indicate s.p. operation

timePDEF 0.008 0.001 1 s Sample time of PDEF element


Table 4.8: Settings for the definite-time curve of PDEF

4.2.5 Phase Selector

The phase selector is mainly needed for two reasons. The virtual polarisation algorithm of

the PDEF directional element has to have information about the faulty phase on order to

calculate the virtual zero-sequence voltage. The second reason is to provide information

about the faulty phase to the trip element during an earth fault and single-pole tripping

enabled. The phase selector is divided into two di↵erent algorithms, which can be selected

by the user. One is based on the di↵erent sequence currents and the other one uses the

sequence voltages. Both of them are described in the following paragraphs. The figure

4.10 depicts the developed phase selector block and its corresponding mask.

54

Figure 4.10: Developed phase selector block and mask

Current-based algorithm: The current based-algorithm of the phase selector uses the

characteristic fault pattern for ground faults, as shown in figure 4.11. It can be seen

from figure 4.11 (a) that one pattern is based on the correlation between the positive

sequence and the negative sequence of the fault current. It should be noticed that single-

line to ground faults (AG, BG and CG) can be distinguished precisely by they angular

relationships. None the less the line-line-faults and the line-line-ground faults share a

common angular pattern and therefore can not be distinguished uniquely.

Phase Selection for Single-Pole Tripping – Weak Infeed Conditions and Cross-Country Faults

Page 8 of 19

The method described in this paper directly checks the angular relationships betweenthe sequence quantities according to the principle pictured in Fig.2. By using the phaseangle information alone, the recognition is made more robust and faster. Additionally,this allows for the application of adaptive techniques.

With reference to Fig.5 six symmetrical “bells” are established to enclose the charac-teristic positions of the negative-sequence current with the positive-sequence current asreference (Fig.5a), and three “bells” to enclose the characteristic positions of the nega-tive-sequence current with the zero-sequence current as reference (Fig.5b).

The maximum limit angle for the negative-to-positive-sequence check is 0.5•60 de-grees = 30 degrees; for the negative-to-positive-sequence check the maximum limit is0.5•120 degrees = 60 degrees. Practically, the limit angles should be smaller than 30 and60 degrees, respectively. Smaller limit angles increase precision of fault type identifica-tion, but slow down the algorithm and create the danger of failure to operate as a givenfault may not fall into any of the angle “bells” due to some angle abnormalities (series-compensation, for example).

The presented algorithm checks consistency between the recognition according toFig.5a and Fig.5b. If the solution is consistent, it becomes the final fault type identified. Ifnot, the algorithm uses the voltages.

The voltage part is identical to the current-based algorithm. The same relations (Fig.2)hold true for voltages. The only difference is the adaptive level check for sequence volt-ages and different values of limit angles.

If only the line-to-line voltages are available, the check shown in Fig.5b cannot be ap-plied because the zero-sequence voltage cannot be estimated and the fault signatureshown in Fig.5a is applied only.If the voltage-based fault type recognition is consistent, it becomes the final fault typeidentified. If not, the VOID flag is set and the algorithm reports its inability to providereliable fault type identification.

I1FI2F

AG

AB, ABGBG

BC, BCG

CG AC, ACG

(a)

I0FI2F

(b)

AG, BCG

CG, ABG

BG, CAG

Θmax

Θmax

Θmax

Θmax

Figure 5. Illustration of the angle comparator limits: negative-sequence vs. positive-sequence faultsignature (a) and negative-sequence vs. zero-sequence fault signature (b).

Figure 4.11: Fault pattern: (a) Positive vs. negative sequence (b) Negative vs. zero-

sequence [10]

The other fault pattern compares the zero-sequence component with the negative-sequence

component of the fault current. It can be seen from figure 4.11 (b) that this algorithm

distinguishes between line-line faults and ground faults. None the less it is not suitable for

55

selection between single-line-ground and line-line-ground faults. Therefore the current-

based phase selector algorithm is based on the positive and negative component of the

fault current, since the single-line to ground faults are of greater importance to the earth

fault protection. Line-line faults and line-line-ground faults are picked up by the PDOC

anyway due to their high magnitude of fault current.

Voltage-based algorithm: In case of a weak-infeed condition the magnitude of the

fault currents are quite small and therefore can not provide reliable information. In this

case a phase selector algorithm is chosen, which uses the symmetrical components of the

voltage values. This principal has been described in [18]. This algorithm uses the angu-

lar relationship between the negative-sequence U2 and zero-sequence voltage U0 as well

as between the superimposed positive-sequence �U1 and superimposed negative-sequence

�U2 voltage. The described phase selector scheme is depicted in figure 4.12.

HUANG et al.: NOVEL METHOD OF GROUND FAULT PHASE SELECTION IN WEAK-INFEED SIDE 2219

Fig. 7. Fault-type identification.

Fig. 8. Scheme of fault phase selection.

where is the fault region obtained from the distinctive

phase region (e.g., for A-G or BC-G faults, is A).

Compared to the sequence current-based fault phase selector,

this principle can be used in the weak-infeed side. The se-

quence current-based fault phase selector utilizes the measured

impedance to distinguish between the single-phase-to-ground

fault and phase-to-phase-to-ground fault, which may be af-

fected by overload. The method using the relative phase-angle

relationship between the superimposed positive- and nega-

tive-sequence voltages can solve this problem.

3) Scheme of the Fault Phase Selection: Finally, combiningthe two steps above, the scheme for the ground fault phase selec-

tion is obtained, as shown in Fig. 8. First, the scheme uses the

relative phase-angle relationship between negative- and zero-

sequence voltages to indicate the probable fault phase. Then,

the scheme uses the relative phase-angle relationship between

the superimposed positive- and negative-sequence voltages to

identify the fault type.

IV. SIMULATION VERIFICATION

In order to verify and evaluate the proposed method of fault

phase selection, a series of faults under different conditions

along the transmission line is simulated in this chapter, and

Fig. 9. Simulation model. (a) IEEE 39-bus system and the (b) transmission linebetween Buses 16 and 21.

the simulation is carried out in the IEEE 39-bus system [15]

(shown in Fig. 9) by using the PSCAD/EMTDC package.

The fault types include a single-phase-to-ground fault and

phase-to-phase-to-ground fault. The relay utilizes full-cycle

Fourier correlation analysis to extract the fundamental fre-

quency components. It takes a transient fault period of a cycle

(0.0167 ms) to extract the 60-Hz fundamental frequency com-

ponents. The sample rate of the relay is 1440 Hz.

Define

where is the fault region number obtained from Fig. 6.

In the IEEE 39-bus system, when the transmission line con-

necting Bus 21 to Bus 22 is out of operation, the relay at Bus 21

is under the weak-infeed condition. The fault point k1 is at the

beginning of the line between Bus 16 and Bus 21, k2 is at the

middle of the line, and k3 is at the end of the line. Faults occur

at 0.05 s.

Under the weak-infeed condition, the voltage waveforms and

sequence current magnitudes measured by the relay at Bus 21

are shown in Fig. 10 when an A-G fault with 50 occurs

at k3. The negative- and zero-sequence voltages are nearly equal

in phase.Meanwhile, the phase-angle difference between the su-

perimposed positive- and negative-sequence voltages is nearly

0 . According to the proposed scheme, the result of the fault

phase selection is phase A. Besides, the sequence current-based

fault phase selector cannot be used in such a situation because

Figure 4.12: Scheme of voltage-based phase selector for weak-infeed conditions [18]

The algorithm shows that it is separated into two parts, namely distinctive phase region

and fault-type identification. The distinctive phase region is divided into 3 zones, from

-90� to 30�, from -210� to -90� and from 30� to 150�. This part of the schema uses U0

as reference to identify the most probable faulty phase. Then the fault-type identification

part di↵erentiates between a single-line-ground fault and a line-line-ground fault based on

the superimposed voltages �U1 and �U2.

The table 4.9 shows the configurable parameters for the phase selector element.

56


timePS 0.008 0.001 1 s Sample time of phase selector block

delayPS 0.016 0 1 s Delay time for stable operation

enableI120 true true false - Enable current-based algorithm

thresI2 0.05 0 1 p.u. Thres. of negative-sequence current I2

angLim 10 0 30 degree Angle tolerance (±)

ringI1 0.80 0 1 s Size of ring bu↵er for load current I1

enableV120 false true false - Enable voltage-based algorithm

thresV0 0.1 0 1 p.u. Thres. of zero-sequence voltage 3 V0

ringV1 0.80 0 1 s Size of ring bu↵er for voltage V1

Table 4.9: Settings for the phase selector block

4.2.6 Trip Element - PTRC

The trip element is described by the logical node PTRC, which is supposed to be used to

gather the trip signals of all implemented protection functions (PDOC, PDEF) according

to IEC 61850. Moreover the single pole tripping is implemented in the PTRC based on the

information provided by the phase selector. If a single phase has been tripped, the PDEF

usually has to be block due to the high earth fault current in solidly grounded systems.

Lastly once a trip has been issued, the trip relay contact has to remain active for a given

amount of time (e.g >150 ms). This value is also set by the user. The figure 4.13 shows

the developed PTRC block and its corresponding mask.

Figure 4.13: Developed PTRC block and corresponding mask

The table 4.10 shows the configurable parameters.

57


outputACTIVE 0.15 0.001 3 s Duration of time for trip outputs

activeSP true true false - Enable single pole tripping

delay3P 0.5 0 3 s Delay time for 3-Phase Trip


Table 4.10: Settings for the PTRC block

4.2.7 EtherCAT-Communication

Above the implementation of the core functionalities of the protection system has been

explained, starting from the sampled values until the trip signal. None the less the com-

munication interface to the process has not been described yet and is done in the following

paragraphs. The communication part of the application is divided into two parts. The

first part consists of the communication driver blocks, which interface with the EtherCAT

master and the corresponding EtherCAT slaves (see section 3.4.1). The second part com-

prises the communication supervision functionality.

EtherCAT driver blocks: The EtherCAT driver blocks are developed by IgH [39]

and provided by the EtherLAB library. This library provides Simulink blocks for the

EtherCAT coupler EK1100 and the EtherCAT slaves EL2624 (relay output) and EL2798

(digital output). The communication block EL2624 can be seen as the logical node XCBR,

which controls the circuit breaker. None the less there is a generic driver block, which

is used for the EtherCAT slaves not covered by the EtherLAB library. In this case the

EtherCAT slaves EL3773 for the current and voltage inputs is not directly provided by

EtherLAB and therefore the generic block is used. In order to setup the EL3773, a Matlab

structure has to be created, which defines the configuration of the given slave, and this

then given as a parameter to the generic block. The structure is similar the EtherCAT

slaves information (ESI) XML file, provided by the manufacture. The driver block EL3773

can be seen as the logical node TVTR and TCTR, which interface with the voltage and

current transformer respectively. All driver blocks run at the base cycle time. Thus there

is only one domain (see section 2.4.1). The figure 4.14 depicts the used Etherlab library,

which is developed by IgH [4].

58

Figure 4.14: Etherlab library developed by IgH [4]

Communication supervision: The second part consists of the supervision of the com-

munication. Each communication cycle time the working counter of the EtherCAT frame

is checked for consistency. If the working counter deviates from its expected value, which

is an indication for lost or corrupt values, then the value estimation algorithm is triggered

in the signal processing block (see section 4.2.2). If the working counter keeps deviating

from its expected value for a adjustable number of frames in a row, then the protection

function is blocked, since its reliability and security can not be guaranteed anymore.

The tunable parameters of the implemented EtherCAT communication is found in the

table 4.11.


masterID 0 0 3 - ID of EtherCAT master to connect to

domainID 0 0 3 - ID of domain to supervise

lostSV 3 1 5 - # of lost frames, function is blocked

SIek1100 0 0 1000 - Slave index of EtherCAT coupler

timeEL1034 0.001 0.001 3 s Sample time of digital input

SIel1034 1 0 1000 - Slave index of digital input

timeEL3773 0.001 0.001 3 s Sample time of analog input

SIel3773 2 0 1000 - Slave index of analog input

filter 200 200 15000 Hz Cuto↵ frequency of low pass filter

timeEL2624 0.001 0.001 3 s Sample time of relay output

SIel2624 3 0 1000 - Slave index of relay output

timeEL2798 0.001 0.001 3 s Sample time of digital output

SIel2798 4 0 1000 - Slave index of digital output

Table 4.11: Configuration of the communication driver blocks and supervision

4.3 Target System

In section 3.4.2 the selection of the runtime environment has been described in terms of

kernel, distribution and EtherCAT master. The following section deals with the configu-

59

ration of the target system. A guideline to setup the runtime environment is found in the

appendix as well as a detail list of the kernel configuration.

4.3.1 Kernel configurations

In order to evaluate the performance impact of the realtime linux kernel, two di↵erent

kernels are build and compared in section 5.4. All kernels are based on the kernel version

3.4.41. One kernel remains the standard vanilla kernel and the other one is patched with

the preempt-rt patch 3.4.41-rt55-feat3.

The proper configuration of the realtime linux kernel is of importance in order to guaran-

tee real-time capabilities. There are many di↵erent options to tune, before building the

kernel. Below the most important configurations are explained.

Proc types and features -> Preemption Model -> FULL RT

In order to build a fully preemptible kernel, the above option needs to be enabled.

Proc types and features -> Timer Frequency -> Timer Freq 1000

The timer frequency should be set to 1 kHz in order to assure a high scheduling frequency.

This frequency is also called tick rate, defining the resolution of the timer interrupt.

Power Management and ACPI option -> ACPI enable

Power Management and ACPI option -> ACPI -> enable only Power Management Timer

Support

Power Management and ACPI option -> CPU Freq scaling disable

Power Management and ACPI option -> CPU Idle disable

In general power management (e.g. ACPI) should be disabled, since they can decrease

the deterministic behaviour. None the less ACPI is need for the high resolution timer.

Therefore it is enabled above, whereas frequency scaling as well as CPU idle are disabled.

4.3.2 EtherCAT-Master

The IgH EtherCAT master has been implemented according to the Industrial Ethernet

standard IEC 61158-4-12 (Data-link protocol specification) and the 61158-6-12 (Applica-

tion Layer protocol specification). This EtherCAT master comprises native EtherCAT

drivers for some common Ethernet chips (e.g. e1000, e1000e). Native approach has the

advantage that the NIC writes incoming data directly in the memory (DMA) and the

processors can then just poll the respective memory address. Thus the NIC does not

have to issue an interrupt. None the less the generic linux driver can still be used for

Ethernet chips, which are not supported by the IgH EtherCAT master. None the less this

approach has the disadvantage that the incoming EtherCAT frame has to go through the

lower network stack and therefore issues a soft-interrupt or a hard-interrupt in case of the

60

RT-kernel or the standard vanilla kernel, respectively [39].

Moreover if the target system provides more than one Ethernet device, then multiple

master modules can run in parallel. In order to ensure a deterministic architecture, a

master module can only be controlled by one application. If multiple applications want

to access the same bus, then the respective application, controlling the EtherCAT master,

needs to implement an according locking mechanism [39]. The figure 4.15 clarifies this

procedure.3.5 Distributed Clocks

Task

EoE

Master Module

Master0

Application Module

Applica

tion

Inte

rface

Figure 3.3: Concurrent Master Access

3.5 Distributed Clocks

From version 1.5, the master supports EtherCAT’s “Distributed Clocks” feature. Itis possible to synchronize the slave clocks on the bus to the “reference clock” (whichis the local clock of the first slave with DC support) and to synchronize the referenceclock to the “master clock” (which is the local clock of the master). All other clockson the bus (after the reference clock) are considered as “slave clocks” (see Figure 3.4).

Reference Clock

Master Clock

Slave Clocks

Slave 2 Slave n

Master

Slave 1Slave 0

(No DC)

Figure 3.4: Distributed Clocks

Local Clocks Any EtherCAT slave that supports DC has a local clock register withnanosecond resolution. If the slave is powered, the clock starts from zero, meaningthat when slaves are powered on at di�erent times, their clocks will have di�erentvalues. These “o�sets” have to be compensated by the distributed clocks mechanism.On the other hand, the clocks do not run exactly with the same speed, since theused quarts units have a natural frequency deviation. This deviation is usually verysmall, but over longer periods, the error would accumulate and the di�erence betweenlocal clocks would grow. This clock “drift” has also to be compensated by the DCmechanism.

Application Time The common time base for the bus has to be provided by theapplication. This application time tapp is used

72b61b089625, 2013/12/10 15

Figure 4.15: Concurrent access of EtherCAT master [39]

Furthermore the IgH EtherCAT master provides the capability of domains for di↵erent

task periods as well as of the distributed clock mechanism (see section 2.4.1). The figure

4.16 shows the described architecture of the EtherCAT master.

In consideration of the described hardware in section 3.4.1 and the implemented runtime

environment in section 3.4.2, the following important configurations of the EtherCAT mas-

ter has been chosen:

--enable-generic=yes

The generic linux driver is enabled for testing purposes later.

--enable-8139too=no

The driver 81379too is not needed due to the selected hardware.

--enable-e1000e=yes

Since the target system supports PCI express, the native EtherCAT driver e1000e is se-

lected as well.

--enable-cycles=yes

This option is supported by Intel architectures in order to achieve finer timing calculations.

--enable-debug-if=yes

61

If the native EtherCAT driver is chosen, there won’t be any Ethernet interface, since the

EtherCAT frame does not go through the network stack. None the less a debug interface

should be provided to capture some EtherCAT frames with Wireshark for diagnostic pur-

poses.

--enable-debug-ring=yes

The recorded frames at the debug interface are then stored in a ring bu↵er.

2 Architecture

ecdev_*()

EtherCAT Master Module

EtherCAT Ethernet

NIC NICHardware

ecrt_*()

Application Module

Task

Kernelspace

netif_*()

ApplicationInterface

GenericEthernetDriver Module

StandardEthernet Driver

NIC

RTDMDevice

CharacterDevice

DeviceInterface

Net

wor

k St

ack

net_devicenet_device

Native EtherCAT-capable Ethernet Driver

net_device

EtherCAT

GenericEthernetDevice

Pack

et

Sock

et

Master 0

Master 1

Figure 2.1: Master Architecture

6 72b61b089625, 2013/12/10

Figure 4.16: Architecture of IgH EtherCAT master [39]

62

Chapter 5

Evaluation

After the design and implementation phase of the model-based design approach, the test

phase is conducted. The test phase has the objective of code verification and validation

as well as to guarantee the compliance of the solution to the requirements.

5.1 Evaluation Method

The evaluation process of the protection system consists of di↵erent dimensions. Firstly,

a functional performance test is conducted on three di↵erent levels, as shown in figure 5.1.

On the first level the model-in-the-loop test is executed in order to evaluate the function-

ality of the implemented algorithm. On the second level, the software-in-the-loop test is

performed. The purpose of Sil is the verification and valudation of the the automatic code

generation of the Simulink Coder. This is done by comparing the SiL solution with the

MiL solution (see section 5.2.1). Thirdly, those simulated test results need to be compared

with the hardware-in-the-loop results (see section 5.2.2). The successful deployment of the

protection application on the target system is evaluated by the Hil test.

In addition to the described functional performance test above a type test is conducted as

required in the IEC 60255-151 for overcurrent protection systems (see 5.3). The results of

the type test are compared with comparable IEDs of OEMs like ABB or Siemens. Once

the functionality of the protection system has been proven and its compliance to the IEC

60255-151 has been tested, then the long term stability of the system is evaluated in section

5.4. The stability test is important to evaluate the performance of the realtime operating

system RT-Linux. Lastly, the I/O modules are examined in terms of their environmental

compliances to the requirements for power system environment (see section 5.5 and 3.2.2).

63

Software-in-the-loop

COMTRADE Files

SimulinkModel

S-function(compiled mex-file)

Matlab/Simulink

Matlab/Simulink

feed to test harness

simulate

simulate

check results

check results

compare results

compare results

Model-in-the-loop

Hardware-in-the-loopOmicron

Target Systeminject check results

Figure 5.1: Functional performance test

5.2 Functional Performance Tests

5.2.1 Model- & Software-in-the-Loop

This section has two objects. On the one side the automatic code generation process,

conducted by the Simulink Coder, is verified and validated. This is done by the comparison

between the results of the MiL with the results of SiL. The second object of this part is

to assure the intended functionality of the implemented protection function. Therefore

three di↵erent fault scenarios are tested for the PDOC as well as the PDEF. Those fault

scenarios are provided as COMTRADE files. COMTRADE is the file format for recording

disturbances in power systems. Usually those files a generated by the disturbance recorders

located in the substations. Those files provide the three-phase voltages and currents as

primary values with a sampling frequency of 1 kHz. The time duration lasts from some

multiple 100 ms before the fault until some multiple 100 ms after the fault has been cleared.

Another reason to use COMTRADE files is the possibility to provide those files as input

to the signal generator (Omicron) in the Hardware-in-the-Loop section. Thus it can be

guaranteed to provide the same fault scenario as in MiL and SiL without the usage of a

real-time simulator until the trip signal occurs.

64

Figure 5.2: Single-line-diagram of first network

The figures 5.2.1 and 5.3 depict the two networks, which have been used for generating

the fault scenarios in section 5.2.1 and 5.2.1.

Figure 5.3: Single-line-diagram of second network with parallel lines

Moreover the table 5.1 shows the configuration of the protection system, which is used for

all di↵erent fault scenarios described below. It can bee seen that the communication driver

blocks and trip element run at the base sample time of 1 ms. The other protection elements

like signal processing element, PDOC, PDEF and the phase selector run at a sample time

of 8 ms. Another important setting is the angle of the positive- and zero-sequence line

impedance. Those parameters are set to 80 degrees and 60 degrees, respectively, in order

to assure correct operating directional elements. In addition, only the first stage of the

definite-time curve of the PDOC and of the PDEF are activated for the cases 1-3 and 4-6

respectively. Lastly, the trip contact remains active for 100 ms, as well. The configuration

of the definite-time curve is specified for each case individually.

65


freq 50 50 60 Hz Fundamental frequency

nrSV 1 1 10 - Oversampling factor

timePRE 0.001 0.001 1 s Sample time of input port

timeSP 0.008 0.001 1 s Sample time of signal proc. element


thresP67 0.1 0 10 p.u. Threshold of active power

thresV 0.1 0 1 p.u. Minimum polarising voltage (V1)


thresP67N 0.1 0 10 p.u. Threshold of power (P0 or Q0)

thresV 0.2 0 1 p.u. Minimum pol. voltage (3 V0)


delayPS 0.016 0 1 s Delay time for stable operation

enableI120 true true false - Enable current-based algorithm

outputACTIVE 0.15 0.001 3 s Duration of time for trip outputs

activeSP true true false - Enable single pole tripping

delay3P 0.5 0 3 s Delay time for 3-Phase Trip


timeEL3773 0.001 0.001 3 s Sample time of analog input

filter 200 200 15000 Hz Cuto↵ frequency of low pass filter

timeEL2624 0.001 0.001 3 s Sample time of relay output

Table 5.1: General configuration for the functional performance test

Directional Overcurrent Protection - PDOC

By the means of the following three test scenarios the functionality of the PDOC is eval-

uated as well as the automatic code generation is validated. This is done by comparing

the results from the MiL and SiL tests with each other.

Case 1: forward single-phase-to-earth fault (phase A)

This test scenario represents a single-phase-to-ground fault at the fault location F 5 in

figure 5.2.1. Thus the general functionality of the PDOC is tested. Moreover the correct

directional sensing and phase selection is proven. The voltage measurements are taken

from bus A and the current measurements are yield from line A to B.

The figure 5.4 shows the condition for a single-phase-to-ground fault for the MiL test.

In total there are five di↵erent points in time indicated by fault occurrence tf , appearance

of start signal tstr, appearance of trip signal ttr, disappearance of start signal tdis and

disappearance of trip signal tres. The time durations between tf and tstr and between

66

tstr and ttr are called start time and trip time, respectively. In addition, the disengaging

time and reset time is the time duration between ttr and tdis and between tdis and tres,

respectively. Those times need to be evaluated as part of the type test in section 5.3.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−6

−4

−2

0

2

4

6

8

10

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]Fault situation in case 1 for MiL

SVMagni tudeStartTripD i rec t i on√

2 x Thre s.

Figure 5.4: Fault situation of case 1 for MiL

In case 1, the following times have been measured for the MiL test:

start time : tstr � tf = 17 ms

trip time : ttr � tstr = 100 ms

disengaging time : tdis � ttr = 12 ms

reset time : tres � tdis = 100 ms

Moreover from the figure 5.4 it can be seen that the directional sensing works correctly as

well as the phase selection of phase A has been performed as expected. In addition the

protection system needs a certain amount of time (start time) to detect the fault. This is

mainly caused by the fact that the signal processing element uses a running window, which

has to be filled with sampled values of the fault current (see section 4.2.2). Therefore a

time delay occurs from the injection of the fault until the start signal occurs. The same

phenomena occurs once the trip signal occurs. The time from fault clearance until the

start signal vanishes is regarded as disengaging time.

67

The same fault situation, represented by the COMTRADE file, is tested in the SiL con-

text as depicted in figure 5.5 below. Examining the curves, the SiL test shows the same

behaviour as the MiL test, which is a good indication for a successful code generation

process. None the less a closer look at the exact characteristic times has to be conducted.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−6

−4

−2

0

2

4

6

8

10

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]

Fault situation in case 1 for SiL


2 x Thre s.

Figure 5.5: Fault situation of case 1 for SiL

In case 1, the following times have been measured for the SiL test:





It can be seen that the MiL and the SiL test yield exactly the same results. Therefore the

conclusion is drawn that the automatic code generation process has been successful.

The table 5.2 show the configuration of the protection application for case 1.

68




thresIst1 3.5 0.5 100 p.u. Current threshold of first stage





Table 5.2: Configuration of application for case 1

Case 2: Forward single-phase-to-earth fault, 44.5 Hz system frequency

For case 2 the same fault scenario is applied as for case 1. None the less the system

frequency has a quite low value of 44.5 Hz instead of 50. A frequency of 44.5 Hz is not

a realistic case for the operation of power systems. None the less it is interesting to see

how the signal processing element, which is designed to extract the 50 Hz component, can

handle such a large deviation from the nominal frequency. Thereby the reliability of the

signal processing element is tested.

The figure 5.6 shows the measurements for the MiL test. First of all the correct oper-

ation of the protection system can be noted. None the less there are also di↵erence in

comparison to case 1. The calculated magnitude of the 44.5 Hz varies during the steady-

state conditions. In addition the start time is longer, since the calculated magnitude of the

signal processing element rises slower than in case 1. The same phenomena is witnessed

for the disengaging time.

69

0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8−10

−8

−6

−4

−2

0

2

4

6

8

10

tstr

tdis

tf

tres

ttr

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]

Fault situation in case 2 for MiL


2 x Thre s.







In case of the Sil test the results are shown in figure 5.7 below. Exact the same behaviour

is noted as for the Mil case. This can be clearly seen when comparing the di↵erent time

durations start-, trip-, disengaging- and reset time of Mil and Sil with each other.

70

0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8−10

−8

−6

−4

−2

0

2

4

6

8

10

tstr

tdis

tf

tres

ttr

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]



2 x Thre s.







In conlusion it can be said, that the signal processing element also works reliable for large

frequency deviations from its nominal value. The table 5.3 show the configuration of the

protection application for case 2.

71










Case 3: Reverse 3-phase fault (close-by)

In the last case for the PDOC element a reversed three-phase fault is applied at position

F 11 in figure 5.2.1, which is in close proximity of the bus A in figure 5.3. This scenario

represents are switch-on fault, meaning that the circuit breakers are closed onto a faulty

line at the time instance of 200 ms. Moreover the magnitudes of the voltages are almost

zero due to the close-by fault. The objective of this case is to test the correct operation

of the directional element based on the memory voltage (see section 4.2.3).

The figure 5.8 shows the measurements for the MiL test. It can be seen that there no

currents flowing up to time instance of 200 ms due to the opened lines. Once the fault

is applied the current magnitude rises quickly over the set threshold. None the less no

start signal occurs, since the directional element senses the fault correctly in the reverse

direction.

72

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−8

−6

−4

−2

0

2

4

6

8

10

12

tf

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]



2 x Thre s.


The same situation is depicted in figure 5.9 for the Sil test. Exactly the same behaviour

is noticed and therefore the code generation process is seen as verified.

73

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−8

−6

−4

−2

0

2

4

6

8

10

12

tf

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]



2 x Thre s.












Directional Earth Fault Protection - PDEF

The following test cases 4 to 6 are performed in order to verify the correct operation of

the PDEF function.

Case 4: High resistive forward SGL-fault (phase A)

In case 4 a high resistive single-line-to-ground fault is applied in forward direction on phase

A at the position F 5 in figure 5.2.1. Due to the nature of low residual currents in case of

74

a high resistive fault the zero-sequence voltage, measured at bus A, is below 0.1 p.u. and

therefore the implemented virtual polarisation algorithm is used (see section 4.2.4).

The figure 5.10 shows the described situation for the MiL test. In spite of the very

low zero-sequence voltage (3xV0) during the fault, the directional sensing is performed

correctly and the fault is cleared. Furthermore the residual fault current (3xI0) has a

RMS value of 0.4 p.u. Thus it would not be possible to detect this fault with the PDOC

function.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

−0.5

0

0.5

1

1.5

2

2.5

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]


3xV03xI0StartTripDirectionThreshold


The following duration of times are yield in case 4 for the Mil test.





The same high-resistive fault situation is tested for the Sil test. The figure 5.11 shows the

result of this corresponing case. Comparing the figures 5.10 and 5.11 shows that they are

identical. This becomes even clearer, when comparing the start- , trip- , disengaging- and

reset time of Mil and Sil with each other.

75

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

−0.5

0

0.5

1

1.5

2

2.5

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]













thres67NIst1 0.3 0.5 100 p.u. Current threshold of first stage




Case 5: Forward SGL-fault (phase A), single pole tripping

In case 5 the successful blocking of the PDEF function after single pole tripping is evalu-

ated. This is important in order to prevent miss-operation during an unbalance operation

76

of the power system with only two phases. The fault is applied at position F 5 in figure .

The figure 5.12 shows the behaviour of the protection system for the MiL test. It can

be seen that the PDEF function operates correctly, in spite of the presents of very low

zero-sequence voltage. Additionally, there is no second trip during the two-pole operation

of the network. The directional elements senses a residual power flow in forward direction.

None the less the start signal is blocked for this situation.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]









In figure 5.13 the Sil test is depicted for the given fault scenario above. Comparing both

figures it is verified that the compiled function works in the same way as the designed

model.

77

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

tf

tstr

tdis

ttr

tres

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]

















Case 6: Changing direction of power flow

The case 6 is simulated with the single-line diagram in figure 5.3. The fault location is at

78

F18 closer to bus B than to A and the voltage measurements are taken from bus A and

the current measurements from line A1 to B1.

Examining figure 5.14, a forward power flow is detected during fault inception. At the

time instance of 0.31 ms circuit breaker B2 opens and the fault current flows in the reverse

direction as seen from circuit breaker A1. Then at the time instance of roughly 0.38 ms the

the circuit breaker A2 opens and the fault is cleared (single pole tripping). Thereby one

of the main objectives of a protection system, namely selectivity, is provided by PDEF, if

the time delay is set accordingly. In this cases the time delay is set to 150 ms. Since the

fault duration in forward direction only occurs for 88 ms, the protection system does not

operate.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

0

1

2

3

4

5

6

7

tf

tstr

tdis

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]






duration of start : tdis � tstr = 88 ms

The figure 5.14 and 5.15 depict the same behaviour of the protection system as well as

the start time are exactly the same in both cases.

79

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

0

1

2

3

4

5

6

7

tf

tstr

tdis

time [s]

Cur

rent

[p.u

.] &

Boo

lean

[0,1

]






duration of start : tdis � tstr = 88 ms









5.2.2 Hardware-in-the-Loop

In the previous section it has been shown that the protection application operates as

expected. In the Hil test the same fault scenarios are applied as for the Sil test in order

to evaluate the overall system performance and to prove the successful integration on the

target system. The figure 5.16 shows the setup in the laboratory.

80

Figure 5.16: Laboratory setup for the Hardware-in-the-loop test

The 24 DC power supply supplies the EtherCAT coupler and slaves. The generated ana-

log current and voltage values, corresponding to the fault scenarios in section 5.2.1, are

provided by the signal generator OMICRON to the current and voltage inputs (EL3773),

respectively. In addition, the relay outputs (EL2624) are linked back to the binary inputs

of the OMICRON for time tracking purposes. The EtherCAT coupler is connected via a

CAT-5 patch cable to the computer running the protection function as a kernel module in

RT-Linux.

The tables 5.8 and 5.9 depict the comparison between the Hil results and the Sil re-

sults. It can be seen that only the start and trip time is given. The reason for that is that

the software, which runs the OMICRON, can only replay the entire COMTRADE file and

can not change the current and voltage values during the playback time. Therefore the

same situation as in Mil and Sil can only be recreated, until the trip signal occurs.

Directional Overcurrent Protection - PDOC

The table 5.8 shows the case 1 to 3 for the PDOC function. The protection function

behaves in the same manner as for the Mil and Sil scenario. It operates for case 1 and 2

and not for case 3. None the less it can be seen that the start time di↵ers. This is due to the

fact that the signal processing element runs at sample time of 8 ms and the application

is not synchronised to the signal generator OMICRON. Once the fault is applied, it is

unknown when the signal processing element is executed the next time. Thus there is an

algorithmic jitter of 8 ms. None the less the trip time is quite deterministic, since the

timer functions run at a sample time of 1 ms. The maximum time resolution of the used

signal generator in this project is 100 µs.

81

Hil SiL

CASE 1

start time 23.3 ms 17 ms

trip time 99.8 ms 100 ms

CASE 2



CASE 3

start time - ms - ms

trip time - ms - ms

Table 5.8: Comparison between Hil and Sil results (PDOC)

Directional Earth Fault Protection - PDEF

In table 5.9 the results of case 4 to 6 are shown for the PDEF function. The same behaviour

is witnessed for the Hil as well as Sil scenario. The trip times are deterministic, having a

jitter of 200 µs.

Hil SiL

CASE 4



CASE 5



CASE 6


trip time - ms - ms

duration of start 86.7 88ms

Table 5.9: Comparison between Hil and Sil results (PDEF)

5.3 Type Tests

In this section the performed type test is evaluated, which is described in the standard IEC

60255-151. The obtained results are compared with an ABB and Siemens relay, described

in table 5.10 below. The values below can not be compared directly, since both OEMs use

di↵erent settings in order to calculate those accuracy levels. The data below is based on

the technical manuals provided by the corresponding manufactures [5] [6].

82

ABB: REL670 2.0 Siemens: 7SJ82

Quantity Accuracy Accuracy

Pick-up value± 1.0 % of In

± 1.0 % of Iset

Drop-o↵ value or 5 mA

Reset ratio >95 % config. 90 % to 99 %

start timeMin: 15 ms

Approx. 37 ms + OOTMax: 30 ms

operate time ± 0.2 % or ± 35 ms ± 1 % or ± 10 ms

disengaging timeMin: 15 ms

Approx. 20 ms + OOTMax: 30 ms

reset time - 1 % or ± 10 ms

Overshoot time 10 ms -

Transient overreach - < 5 %

Angle error ± 2 degrees ± 1 degrees

Table 5.10: Type test results of common relays on the market for PDOC function

In in the table above is usually 1 A or 5 A. Iset in the table above can be set from 30

mA to 35 A for the Siemens relay. OOT means output operating time and described the

additional time due to the output medium. For fast relays this value is usually 5 ms.

5.3.1 Accuracy of pick-up and drop-o↵ value

The accuracy of the pick-up and drop-o↵ values are tested by the means of ramping test.

The initial value is set to 20 mA below the given threshold in case of the pick-up value

testing and the ramping steps are 10 times smaller than the given accuracy for the element

EL3773, which is given by 7.5 mA. Thus the ramping steps are set to 750 µA. In addition

the step time of the ramping function shall be between 2 and 5 times of the start time,

which is given in section 5.3.3. Thus the step time is set to 50 ms. In case of drop-o↵

value testing, the same ramping function is applied just with a negative slope.

Considering the ramping function described above, ten di↵erent test points have been

selected along the entire available range from 50 mA to 1 A. Each of the test points has

been tested for the individual phases 5 times. The table 5.11 shows the average and

maximum error for each of those test points.

83

Pick-up Drop-o↵

Threshold Average Maximum Average Maximum

50 mA 0.25 mA 0.25 mA 0.33 mA 0.5 mA

54.75 mA 0.5 mA 0.5 mA 0.5 mA 0.5 mA

59.5 mA 0.5 mA 0.5 mA 0.5 mA 0.5 mA

69 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA

78.5 mA 0.5 mA 0.5 mA 0.5 mA 0.5 mA

97.5 mA 0.25 mA 0.25 mA 0.25 mA 0.25 mA

145 mA 0.5 mA 0.5 mA 0.5 mA 0.75 mA

335 mA 0.5 mA 0.5 mA 0.54 mA 0.75 mA

620 mA 0.25 mA 0.25 mA 0.46 mA 1.0 mA

1000 mA 0.25 mA 0.25 mA 0.75 mA 1.0 mA

Average 0.5 mA 0.75 mA

Maximum 0.5 mA 1 mA

Table 5.11: Average & maximum error of pick-up/drop-o↵ for 10 di↵erent test points

The maximum errors are 0.5 mA and 1 mA for the pick-up and drop-o↵ value, respectively.

Those level of accuracy is really good in comparison to other relays. None the less the

operating range of the analog input (EL3773) is not su�ciant (max 1.2 A RMS) to operate

in a power system environment. The ABB relay REL670 2.0 above states an accuracy

of ±1 % of In for the pick-up and drop-o↵ value, where In is usually 1 A or 5 A. The

Siemens relay 7SJ82 of the SIPROTEC 5 series states an accuracy of ±1 % of Iset or 5

mA, depending which is greater, for the pick-up and drop-o↵ value.

5.3.2 Determination of reset ratio

In table 5.12 the reset ratio is depicted. The reset ratio is given by the ratio of the actual

pick-value and the actual drop-o↵ value. For this test the same ten test points are selected

as for the accuracy of the pick-up/drop-o↵ value. The average and minimum values are

shown for each test point, which has been tested five times on a individual phase basis.

84

Reset ratio

Threshold Average Minimum

50 mA 99.50 % 99.00 %

54.75 mA 98.19 % 98.19 %

59.5 mA 98.33 % 98.33 %

69 mA 99.28 % 99.28 %

78.5 mA 98.73 % 98.73 %

97.5 mA 99.49 % 99.49 %

145 mA 99.31 % 99.14 %

335 mA 99.69 % 99.63 %

620 mA 99.89 % 99.80 %

1000 mA 99.90 % 99.88 %

Average 99.23 %

Minimum 98.19 %

Table 5.12: Average and minimum value of reset ratio

The average and minimum reset ratio of the implemented protection system is given by

99.23 % and 98.19 %, respectively. The ABB relay shows a reset ratio of greater than

95 % and the Siemens relay has the option to configure the reset ratio from 90 % to 99

%. Comparing those results against reset ratios of common relays on the market, it can

be seen that the obtained results are competitive. None the less the described narrow

operating range of the analog input is a limiting factor.

5.3.3 Steady state errors of start and operate time

In this section the accuracy of the start and operate time is evaluated. This test has been

performed with di↵erent ratios ofIfault

Iset

, as shown in figure 5.17. It should be kept in mind

that the time resolution of the OMICRON device is 100 µs. The accuracy test below has

been conducted for 360 test points.

Start time:

The figure 5.17 shows the distribution of the start time for di↵erentIfault

Iset

ratios. The

start time is measured from the point in time of fault occurrence until the pick-up signal

appears. The first thing, that should be noticed, is that the recorded start time is always

a multiple of 8 ms. This is due to the fact that the application has been synchronised to

the OMICRON. That means, when the fault is applied exactly, when the signal processing

element is executed, which runs at a sample time of 8 ms. Moreover the start time tends

to decrease with an increase of theIfault

Iset

ratio. This phenomenon is caused by the fact,

that only few sampled values of the fault current are needed to calculate a RMS value

above the threshold value.

85

0 0.005 0.01 0.015 0.02 0.025 0.030

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time in [s]

Pro

babili

ty

Distribution of start time for different (Ifault

/Iset

) ratios

Ratio 1.2Ratio 2Ratio 5Ratio 10Ratio 20

Figure 5.17: Distribution of start time for di↵erentIfault

Iset

ratios

The worst-case start time, which is measured above, equals 32.4 ms. ABB states for its

relay a minimum start time of 15 ms and a maximum start time of 30 ms. Siemens claims

to achieve a start time of approximately 37 ms plus some additional operating time (ap-

prox. 5 ms) for the relay operation. Considering those values, the start times, obtained for

the developed protection function based on COTS components, are considered as su�cient.

Operate time:

The accuracy of the operate time is measured for di↵erent delay times 0 s, 600 ms and 3 s.

The operate time is defined by the duration from the appearance of the pick-up value until

the trip signal occurs. Therefore the operate time should not be dependent on theIfault

Iset

ratio, but rather on the deterministic behaviour of the operating system. The figures 5.18

(a), (b) and 5.19 show the distribution of the recorded operate time for the delay times 0

s, 600 ms and 3 s, respectively. It can be seen that the deviation from the expected value

is very small.

86

−3 −2.5 −2 −1.5 −1

x 10−4

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Operate Time in [s]

Pro

ba

bili

ty

Distribution of accuracy of operate time

Set time delay: 0s

0.5996 0.5996 0.5997 0.5997 0.5998 0.5998 0.59990

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Operate Time in [s]

Pro

ba

bili

ty


Set time delay: 0.6s

Figure 5.18: Measured operate time for a setting of (a) instantaneous & (b) 600 ms

2.9996 2.9996 2.9997 2.9997 2.9998 2.9998 2.9999 2.99990

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Operate Time in [s]

Pro

ba

bili

ty


Set time delay: 3s

Figure 5.19: Measured operate time for a setting of 3 s

The worst-case deviation shown above is 400 µs. Comparing this result with the selected

ABB and Siemens relay shows that the results are very competitive with OEM solutions.

ABB claims an accuracy of ± 0.2 % of the delay time or ± 35 ms, depending which of them

is greater. The stated accuracy by ABB includes the measurement time and therefore is

not directly comparable to the recorded operate times above. Siemens states ± 1 % of the

delay time or ± 10 ms, depending which of them is greater.

5.3.4 Steady state errors of disengaging and reset time

This section analysis the accuracy of the disengaging and reset time. The disengaging

time is measured from fault clearance until pick-up signal disappears. On the other hand,

the reset time is defined as the duration from the disappearance of the pick-up signal until

the trip output releases (see section 3.2.1).

Disengaging time:

87

The figure 5.20 shows the disengaging time for di↵erentIpostFault

Iset

ratios. The disengaging

time decreases with an decrease of the given ratio. This phenomenon is caused by the fact

that only few sampled values of the post fault are need to obtain a RMS value below the

threshold.

0 0.005 0.01 0.015 0.02 0.025 0.030

0.1

0.2

0.3

0.4

0.5

Disengaging time in [s]

Pro

babili

ty

Distribution of disengaging time for different (IpostFault

/Iset

) ratios

Ratio 0.8Ratio 0.4Ratio 0.2Ratio 0.1Ratio 0

Figure 5.20: Distribution of disengaging time for di↵erentIpostFault

Iset

ratios

The worst-case disengaging time above is 30.1 ms. ABB states a disengaging time of

minimum 15 ms and maximum 30 ms. Siemens, on the other hand, claims to yield a

disengaging time of approximately 20 ms plus OOT. Thus the obtained results of the

developed protection function are in the same range as the results of the two big OEMs.

Reset time:

The distribution of the reset time is plotted in the figures 5.21 (a), (b) and 5.22. As

stated above, the reset time is measured from the disappearance of the pick-up signal

until the disappearance of the trip signal. Since this function mainly involves a timer

function, running at 1 ms, the results should be highly deterministic and mostly depend-

ing on the operating system behaviour. The figure show the accuracy of reset times for

the configurable values of 50 ms, 600 ms and 3 s.

88

0.0498 0.0498 0.0499 0.05 0.05 0.05 0.0501 0.05020

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Rest Time in [s]

Pro

ba

bili

ty

Distribution of accuracy of reset time


0.5998 0.5999 0.6 0.60010

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Rest Time in [s]

Pro

ba

bili

ty



Figure 5.21: Measured operate time for a setting of (a) 50 ms & (b) 600 ms

2.9999 2.9999 3 3 3.00010

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Reset Time in [s]

Pro

ba

bili

ty


Set time delay: 3s

Figure 5.22: Measured operate time for a setting of 3 s

The largest deviation from the expected value is 200 µs. Siemens claims to achieve an

accuracy of ± 1 % or ± 10 ms, similar to the claimed operate time. ABB does not state

the corresponding quantity. None the less, the obtained worst-case deviation of 200 µs is

a su�cient level of accuracy.

5.3.5 Transient overreach

The intention of the transient overreach test is to determine the impact of a dc o↵set on

the protection performance. The set value for the trip command Iset is set to 1 p.u. In

the first step the actual trip threshold is determined for a waveform without any dc o↵set.

This is done by applying a current of 0.9x Iset, which is constantly increased until the trip

occurs. This determined value is then reduced by 2% and is called test current INOdc.

Then the test is conducted with the maximum d.c o↵set and three di↵erent time constants,

defined by the X/R ratio (10, 40, 120, see section 2.2.3). If the protection system operates,

then Iset is increased until no start signal occurs five times in a row. This set value is then

called IsetDC . The table 5.13 shows the results of the transient overreach test.

89

Iset 1.00

INOdc 0.98

X/R Ratio 10 40 120

IsetDC 1.1 1.03 1.02

Transient Overreach 12.24% 5.10% 4.08%

Table 5.13: Results of the transient overreach test acc. to IEC 60255-151

The worst-case transient overreach of the developed protection system is 12.24 %. More-

over the transient overreach decreases with an increase of the time constant. This due to

the fact that the protection function are based on the 50 Hz component and the signals,

having a lower X/R ratio, have an higher ratio of the 50 Hz component. The measured

value is rather high in comparison to the transient overreach of Siemens solution of < 5

%. None the less, this quantity of the Siemens relay is measured at time constant of 100

ms, which corresponds to a X/R ratio of 31.4 for a 50 Hz system.

The IEC 60255-151 defines the transient overreach according to the equation below. The

figure 5.23 depicts the typical test waveform.

Transient overreach =⇣ Setting at which no operation occurs for o↵set waveform

Setting at which no operation occurs for waveform without o↵set� 1

�

=IsetDC � INOdc

IsetDC

60255-151 © IEC:2009 – 25 –

With the test current magnitude established, tests shall be performed with the maximum d.c. offset present and with a constant X/R ratio up to 120 (preferred test points are for X/R ratios of 10, 40 and 120). Typical test waveform is shown in Figure 11 for a 50 Hz nominal frequency. During the tests, current shall be stepped from 0 A to the test current magnitude with no intentional delay, and relay operation shall be monitored for at least the duration of the time constant of the current waveform. If the element starts to operate, the test shall be re-performed with a higher setting for GS until application of the offset waveform does not cause relay starting. Five successive non-operations for a given setting value indicate that the transient overreach stability point has been reached.

The transient overreach at each X/R value is given by:

1001offset without waveformfor occurs operation no whichat Setting

waveformoffset for occurs operation no whichat Setting %) (in overreach Transient ×⎟⎟⎠⎞

⎜⎜⎝⎛

−=

0 0,05 0,1 0,15 0,2

Figure 11 – Typical test waveform for transient overreach

6.5.3 Overshoot time

Overshoot time is relevant for overcurrent relay and it is not applicable for undercurrent relay.

With the relay setting at reference conditions (setting value of In), current shall be switched from an initial value of zero to 5 × GS and the relay operate time shall be measured as a maximum value out of five attempts. With this known operating time, the same current of 5 × GS shall be applied for a period of time 5 ms less than the maximum operate time and then reduced to zero with no intentional delay. If relay operation occurs, the period of time for which the current is injected shall be reduced by a further 5 ms, and the test shall be performed again. The injection time shall be decreased further until five successive injections of current do not cause the relay to operate.

The difference in time between the current injection period and the measured relay operate time is the relay overshoot time.

For an independent time overcurrent relay, a current of 2 × GS shall be used instead of 5 × GS and a time delay of 200 ms shall be used for this test. Overshoot time test is not required for an instantaneous overcurrent function.

IEC 1715/09


Figure 5.23: Typical test waveform for transient overreach [2]

90

5.3.6 Overshoot time

The test for overshoot time is performed at a set trip value of 1 p.u. and a time delay

of 200 ms. Then a fault current of 2 p.u. is applied and the time from fault inception

to trip occurrence is measured. This is done five times in a row and the maximum time

measured is denoted as tmax. Then the injection period is decreased by 5 ms (tmax�5 ms).

If the protection system operates, then then the injection period is reduced by another

5 ms, until no trip occurs for five successive tries. This yield injection period, for which

no trip occurs, is denoted as tnoTRIP . The di↵erence in time between tmax and tnoTRIP

is described as the overshoot time. The overshoot time for the implemented protection

system is 6.4 ms, as seen in table 5.14 below.

top1 221 ms

top2 221.1 ms

top3 221.1 ms

top4 221.3 ms

top5 221.4 ms

tmax 221.4 ms

tnoTRIP 215 ms

overshoot time 6.4 ms

Table 5.14: Results of overshoot time test acc. to IEC 60255-151

ABB claims to obtain an overshoot time of 10 ms for the corresponding PDOC function

of the REL670 2.0 relay. Siemens does not state this quantity.

5.3.7 Accuracy of directional element

The accuracy of the directional element is not required in the IEC 60255-151, since this

standard only refers to overcurrent protection without directional sensing. The IEC 60255-

167 actually covers the directional current protection, but it has not been released yet.

Therefore the accuracy of the directional element has been tested according to in a similar

approach as the accuracy of the start value.

91

PDOC PDEF

MTA 60� 50�

Upper limit 30� 40�

Lower limit -150� -140�

Initial value -151� 31� -141� 41�

Ramping steps 0.01� 0.01� 0.01� 0.01�

Step time 500 ms 500 ms 500 ms 500 ms

Measured angle 1 -150.46� 30.05� -140.95� 40.05�

Measured angle 2 -149.99� 30.05� -140.04� 40.05�

Measured angle 3 -150.00� 30.05� -140.08� 40.05�

Measured angle 4 -150.16� 30.13� -140.47� 40.53�

Measured angle 5 -150.47� 30.29� -140.41� 40.88�

Absolute error 1 0.46� 0.05� 0.95� 0.05�

Absolute error 2 0.01� 0.05� 0.04� 0.05�

Absolute error 3 0.00� 0.05� 0.08� 0.05�

Absolute error 4 0.16� 0.13� 0.47� 0.53�

Absolute error 5 0.47� 0.29� 0.41� 0.88�

Average error 0.22� 0.11� 0.39� 0.31�

Maximum error 0.47� 0.29� 0.95� 0.88�

Table 5.15: Ramping test to determine the accuracy of the directional elements

From the table above shows that the maximum error of the angle measurement is roughly

±1�. Since the tested protection system does not involve any instrument transformers, this

value is likely to increases for the overall implementation. Therefore blinders should be

implemented for the upper and lower angle limit for future approaches. The ABB solution

states an accuracy of the angle of ± 2� and the Siemens solution claims an accuracy of ±1�.

5.4 Evaluation of realtime performance

Above the functional performance test as well as the required type test has been performed.

This section comprises the evaluation of the realtime performance of the used operating

system. Due to practical reasons for longterm testing and the requirement to rebuild the

protection system at the facilities of the university, the test setup above has been changed.

Instead of using the OMICRON as signal generator to the EtherCAT slaves, a realtime

simulator (OPAL-RT OP5600) has been connected to the corresponding analog inputs and

digital outputs. Since the analog outputs of the OP5600 provide voltage measurements

in the range of ± 10 V and amplifiers has not been available during the project execu-

tion, the EtherCAT module EL3773 (current/voltage input) has been replaced with the

92

module EL3104 (voltage input ± 10 V). In addition the runtime environment has been

implemented on a di↵erent hardware (dual-core 2.4 GHz, 2048 MB memory). This change

of setup is seen as justifiable, since the evaluation of the realtime performance focuses on

the behaviour of the operating system.

Di↵erent setups of the runtime environment are analysed. Thus the influence of the

preempt-rt patch on the worst-case trip time is determined. The reduction of the worst-

case trip time is the overall objective of the usage of a realtime system. There are four

di↵erent setups in total, which di↵er in terms of the used kernel (mainline vs. rt-kernel)

as well as in terms of the driver usage (native vs. generic). The following configuration is

applied for all four setups of the runtime environment.

• CPU a�nity of threads are set to single core (taskset)

• Generic driver: NIC interrupts with same CPU a�nity as threads

• All threads run with realtime priority 99 (chrt)

• All threads are scheduled with First-in-First-out scheduler policy (chrt)

• irqbalance is disabled

• Load on CPU is generated by the Linux program stress

The fault scenario runs 24 hours for each setup of the runtime environment. The fault

scenario itself consists of a single-phase forward fault and is applied every second, which

yields roughly 86400 (60x60x24) test points. The PDOC function is used as protection

function with a configured time delay of 100 ms. In order to evaluate the realtime perfor-

mance of the protection system, the start time as well as the operate time (from start to

trip) are recorded for each test point.

5.4.1 Distribution of start time

The worst-case start time should not exceed 24 ms for a short-circuit fault. The thread,

comprising the signal processing element and protection function (PDOC), has task period

of 8 ms. Thus 24 ms is the smallest multiple of 8 ms, which is higher than the fundamental

period of the signal (20 ms - 50 Hz system). At this point in time the entire moving win-

dow of the signal processing element consists of samples of the fault current (see section

4.2.2).

The figures in table 5.16 show the distribution of the start time for each setup of the

runtime environment. The second table 5.17 shows the exact worst-case start time of the

roughly 86400 test points.

93

RT-kernel Mainline

Native

driver

0 0.005 0.01 0.015 0.02 0.0250

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]P

rob

ab

ility

RT−preempt and Native driver

0 0.005 0.01 0.015 0.02 0.0250

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]

Pro

ba

bili

ty

Mainline and Native driver

Generic

driver

0 0.1 0.2 0.3 0.4 0.50

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]

Pro

ba

bili

ty

RT−preempt and Generic driver

0 0.02 0.04 0.06 0.08 0.1 0.12 0.140

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]

Pro

ba

bili

ty

Mainline and Generic driver

Table 5.16: Distribution of start time for di↵erent setups of runtime environment

The dashed line in the above figures indicates the worst-case start time. It can be seen

that the native driver approach yields satisfactory results for the rt-kernel as well as for

the mainline kernel, since the start time is below 24 ms for all test points. None the less,

the worst-case start times are quite long in case of the generic driver. Those performance

di↵erences between the two drivers could be explained by the usage of direct memory

access in case of the native driver approach.

RT-kernel Mainline

Nativetstr = 18.2 ms tstr = 18.4 ms

driver

Generictstr = 426.1 ms tstr = 134.1 ms

driver

Table 5.17: Worst-case start time for di↵erent setups of runtime environment

5.4.2 Distribution of operate time

In order to evaluate the realtime performance of the protection system, the worst-case

operate time is more applicable than the start time, since the counter functions run at

task period of 1 ms instead of 8 ms. Thus the resolution is higher. The figures in table

5.18 show the distribution of the operate time for the four di↵erent setups of the run-

time environment. The second table 5.19 shows the exact worst-case operate time of the

94

roughly 86400 test points. It should be mentioned that the operate time is measured from

occurrence of start signal until the trip signal appears.

RT-kernel Mainline

Native

driver

0.0996 0.0998 0.1 0.1002 0.1004 0.1006 0.10080

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]

Pro

ba

bili

ty

RT−preempt and Native driver

0.095 0.1 0.105 0.11 0.115 0.12 0.1250

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Start time [s]

Pro

ba

bili

ty

Mainline and Native driver

Generic

driver

0.098 0.1 0.102 0.104 0.106 0.1080

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Start time [s]

Pro

ba

bili

ty

RT−preempt and Generic driver

0.0996 0.0998 0.1 0.1002 0.1004 0.1006 0.10080

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Start time [s]

Pro

ba

bili

ty

Mainline and Generic driver

Table 5.18: Distribution of operate time for di↵erent setups of runtime environment

The dashed line in the above figures indicates the worst-case operate time. The setup

of the runtime environment, based on the native driver and rt-kernel, yields satisfactory

results. The deviation from the expected value of 100 ms (configured time delay) is 100

µs, which is considered as appropriate for AC protection applications. This phenomena

is as expected, since the preempt-rt patch converts the standard kernel into a fully pre-

emmptible kernel. Thus the threads, which are created by the program stress and are

not running with realtime priorities, are preempted by the RT-kernel and the protection

application is able to be executed.

The larger deviations from the expected value were expected in case of the mainline ker-

nel. Nevertheless a deviation of 200 µs has been measured for the setup with the mainline

kernel and the generic driver. Combining the results from the subsections 5.4.1 and 5.4.2,

only the setup with the rt-kernel and the native driver yields stable results. The large

deviations for all other setups are very rare events (1 to 6 out of 86400). Therefore, an

in-depth study on the realtime operating system has to be performed in future in order to

find the root-cause for this odd behaviour above.

95

RT-kernel Mainline

Nativettr = 100.1 ms ttr = 124 ms

driver

Genericttr = 106.1 ms ttr = 100.2 ms

driver

Table 5.19: Worst-case operate time for di↵erent setups of runtime environment

5.5 Environmental compatibility of I/O modules

This section compares the required electromagnetic compatibility in terms in immunity,

which is defined in section 3.2.2, with the given electromagnetic compatibility of the used

EtherCAT modules in this project. In addition the IEC standards for vibration and shock

resistance, which the I/O modules are compliant to, are stated. None the less this evalu-

ation is left for future investigations.

EMC

The required electromagnetic immunity for substation applications is given by IEC 61000-

6-5. Nevertheless the used EtherCAT modules in this project are only compliant to the

industrial standard 61000-6-2. Therefore this EMC evaluation is based on a comparison

of those two standards. Both standards define test procedures in order to test the per-

formance during and after the electromagnetic phenomena stated in table 3.1. The tests

are carried out on a port-by-port basis. Therefore the corresponding standards define four

di↵erent ports for the equipment under test, as shown in figure 5.24.

– 10 – IEC 61000-6-5:2015 © IEC 2015

3.1.6 high voltage HV set of voltage levels in excess of medium voltage

Note 1 to entry: In the context of this standard the following terms for system voltage are used (see also 3.1.9):

– low voltage (LV) refers to Un ≤ 1 kV;

– medium voltage (MV) refers to 1 kV < Un ≤ 36 kV;

– high voltage (HV) refers to voltage above 36 kV and includes EHV and UHV.

3.1.7 installation several combined items of equipment (including cables) put together at a given place to fulfil a specific task

3.1.8 low voltage set of voltage levels used for the distribution of electricity and whose upper limit is generally accepted to be 1 000 V a.c.

[SOURCE: IEC 60050-601:1985, 601-01-26]

3.1.9 medium voltage MV any set of voltage levels lying between low and high voltage

Note 1 to entry: The boundaries between medium and high voltage levels overlap and depend on local circumstances and history or common usage. Nevertheless the band 30 kV to 100 kV frequently contains the accepted boundary.

Note 2 to entry: In the context of this standard, medium voltage is defined as the voltage range of 1 Kv < Un ≤ 36 kV.

[SOURCE: IEC 60050-601:1985, 601-01-28, modified – a note to entry 2 has been added.]

3.1.10 port particular interface of the equipment which couples this equipment with, or is influenced by, the external electromagnetic environment

Note 1 to entry: Examples of ports of interest are shown in Figure 1. The enclosure port is the physical boundary of the equipment (e.g. enclosure). The enclosure port provides for radiated and electrostatic discharge (ESD) energy transfer, whereas the other ports provide for conducted energy transfer.

Figure 1 – Equipment ports

IEC

AC power port Enclosure port Signal/control port

EQUIPMENT

DC power port


Figure 5.24: Ports of equipment under test [19]

The enclosure port, signal/control port and the AC and DC power ports are defined above.

The following three tables (5.20, 5.21, 5.22) compare the standard 61000-6-5 with 61000-

6-2. The AC power port is not evaluated, since the EtherCAT modules are supplied by

direct current. In the first column of the tables the electromagnetic phenomena is stated.

The second and third column specifies the standard, which describes the performed test

procedure, and states the magnitude of the test values, respectively. The fourth and

fifth column shows the performance criteria, which have to be fulfilled according to the

two respective standards. As stated in section 3.2.2, the performance criteria A has to

be satisfied for protection applications. The last column shows the compliancy of the

EtherCAT modules to the required substation environment.

96

Performance criteria

Environmental

phenomena

Basic

standard

Test

specifications

61000-6-5 61000-6-2 Comp.

Power frequency

magnetic field

61000-4-8 100 A/m (cont.)

1 kA/m for 1 s

A - -

Radiated, radio

frequency

electromag. field

61000-4-3 80 MHz to 1 GHz

10 V/m (rms)

80 % AM (1 kHz)

A A yes

Radiated, radio

frequency

electromag. field

61000-4-3 1 GHz to 2.7 GHz

3 V/m (rms)

80 % AM (1 kHz)

A - -

Radiated, radio

frequency

electromag. field

61000-4-3 2.7 GHz - 6 GHz

1 V/m (rms)

80 % AM (1 kHz)

A - -

Electrostatic

discharge

61000-4-2 6 kV (contact)

8 kV (air)

A B no

Table 5.20: Comparison between IEC 61000-6-5 and IEC 61000-6-2 for enclosure port

At a first glance it can be seen that a lot of compliance statements are not made. This

is due to the reason that the industrial standard IEC 61000-6-2 requires that most of

the stated tests are performed with lower magnitudes of test values in comparison to the

substation standard IEC 61000-6-5. Therefore the author didn’t give any indication of

compliance.

In case that both standards require the performance criteria A for the same test with

the same test specifications, then the compliance is said to be true. None the less it can

be seen that this is only true for some radio frequency tests. The electrostatic discharge

test for the enclosure port shows that the same test specifications are applied in both

standards. Nevertheless the performance criteria, required by the industrial standard, is

B. That means that the equipment under test is allowed to maloperate during the test.

This is not compliant to the required performance criteria A for protection applications

in high-voltage substation environments.

In the end it is concluded that the used EtherCAT couplers and slaves are not com-

pliant for the substation environment. None the less this project has only evaluated one

particular EtherCAT module of one vendor. Therefore the author suggest to perform an

extended market research for commercial-o↵-the-shelf and suitable EtherCAT modules as

part of future investigations.

97


Environmental

phenomena

Basic

standard

Test

specifications

61000-6-5 61000-6-2 Comp.

Fast transient 61000-4-4 4 kV

5 kHz or 100 kHz

A - -

Surge 61000-4-5 2 kV

1.2/50 µs

line to ground

A - -

1 kV

1.2/50 µs

line to line

A - -

Conducted

disturbances,

induced by radio-

frequency fields

61000-4-6 150kHz to 80MHz

10 V (rms)

80 %

AM (1 kHz)

A A yes

Mains frequency

voltage

61000-4-16 30 V (cont.)

300 V for 1 s

A - -

Damped

oscillatory wave

61000-4-18 2.5 kV

common mode

1 MHz

A - -

1 kV

di↵erential mode

1 MHz

A - -

1 kV

di↵erential mode

10 MHz

A - -

Voltage dips &

voltage interrup-

tions

61000-4-29 70 % UT , 0.1 s

40 % UT , 0.1 s

0 % UT , 0.05 s

A - -

Table 5.21: Comparison between IEC 61000-6-5 and IEC 61000-6-2 for d.c. power ports

98


Environmental

phenomena

Basic

standard

Test

specifications

61000-6-5 61000-6-2 Comp.

Fast transient 61000-4-4 4 kV

5 kHz or 100 kHz

A - -

Surge 61000-4-5 2 kV

1.2/50 µs

line to ground

A - -

Conducted

disturbances,

induced by radio-

frequency fields

61000-4-6 150kHz to 80MHz

10 V (rms)

80 %

AM (1 kHz)

A A yes

Mains frequency

voltage

61000-4-16 30 V (cont.)

300 V for 1 s

A - -

Damped

oscillatory wave

61000-4-18 2.5 kV

common mode

1 MHz

A - -

1 kV

di↵erential mode

1 MHz

A - -

Table 5.22: Comparison between IEC 61000-6-5 and IEC 61000-6-2 for signal ports

Vibration and shock resistance

The required vibration and shock resistance for protection systems are defined in IEC

60255-21. The used EtherCAT modules are compliant to 60068-2-6 (vibration) and 60068-

2-27 (shock). Thus those standards have to be compare in future work, in order to give a

statement on those environmental requirements.

99

Chapter 6

Conclusion and Discussion

6.1 Conclusion

The project has shown the development of a directional definite-time overcurrent and

earth fault protection based on COTS components. The development process has been

conducted based on a model-based design approach. As part of the evaluation phase the

implemented functionality of the protection system has been attested and code generation

has been verified. Moreover the performed type test showed the compliance to the IEC

60255-151 standard. In addition the obtained type test results are compatible with the

standard IEDs of di↵erent OEMs. As part of a stability analysis, the realtime operating

system has been tested. Lastly, the environmental compatibility of the I/O modules has

been evaluated in terms of electromagnetic compatibility.

The developed protection system, based on COTS components, has been shown to be

compliant to the functional protection standard IEC 60255-151. None the less the envi-

ronmental requirements in terms of EMC immunity could not be fulfilled. In addition the

stability of the realtime performance has not been satisfied. Therefore several suggestions

are made for prospective studies and implementations in the section below.

6.2 Future Work

At the beginning of the thesis a design choice has been made to locate only the I/O mod-

ules close to the process and to keep the standalone-PC, running the protection function,

in surroundings with less stringent environmental requirements. None the less, the envi-

ronmental evaluation of the I/O modules has shown, that the chosen EtherCAT coupler

and slaves only fulfil the industrial standard, but not the power system standard in terms

of EMC immunity. In future either EtherCAT slaves with better EMC performance has

to be used or proper shielding has to be provided by other means. In addition, an analog

input with higher current capabilities (100 A RMS) has to be selected in order to resist

the high secondary short-circuit currents.

100

Lastly, the evaluation of the realtime performance has not been satisfied, as shown during

the longterm test in section 5.4. Thus the author suggests an in-depth analysis of the

realtime behaviour of the operating system.

101

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Appendix

Setting up the runtime environment

This section gives a guideline on how to setup the runtime environment for the protection

system. The Ubuntu 12.04.5 LTS (Long Term Support) is picked as distribution, which

comes with the kernel version 3.13. Therefore the following steps are undertaken to setup

the kernel versions 3.4.41-generic and 3.4.41-rt55-feat3. Furthermore the required steps

to install the EtherCAT master and the required libraries are mentioned. The guideline

is mainly based on the IgH EtherCAT documentation([39]) and the ”LinuxTricksNTips”

website of Autonomous System Lab of the Technical University of Darmstadt.

# apt-get upgrade

# apt-get update

# apt-get install kernel-package fakeroot build-essential libncurses5-dev

Get the kernel source from http://kernel.org/. The main vanilla kernel 3.4.41 is needed as

well as the rt-patch patch-3.4.41-rt55 and patch-3.4.41-rt55-feat3. The patches are found

under http://www.kernel.org/pub/linux/kernel/projects/rt/. Once downloaded, unzip all

packages.

$ cd linux-3.4.41 // Ignore next two commands, if rt-preempt not needed

$ patch -p1 < ../patch-3.4.41-rt55.patch

$ patch -p1 < ../patch-3.4.41-rt55-feat3.patch

$ cp /boot/config-$(uname -r) .config // Copy current config file

$ make oldconfig // Optional

$ make menuconfig // Note section 4.3.1

$ make-kpkg clean

$ CONCURRENCY LEVEL=$(getconf NPROCESSORS ONLN) fakeroot make-kpkg --initrd

--revision=0 kernel image kernel headers // Creates kernel binaries and headers

# cd .. && sudo dpkg -install linux-image* linux-headers*

# reboot // Choose the RT-kernel in the bootloader (e.g GRUB)

# rm /lib/modules/8uname -r8/build //Symbolic link points still to old headers/source

106

# ln -s /usr/src/linux-headers-8uname -r8 /lib/modules/8uname -r8/build

Now the real-time kernel is up and running. Since the realtime application is linked against

the EtherCAT master library and the PdServ library, those libraries have to be installed.

The PdServ library has the following dependencies: Log4plus Library, CommonCpp2 Li-

brary, YAML library.

# apt-get upgrade

# apt-get update

# apt-get install build-essential kernel-package libncurses5-dev bzip2 hfsprogs

fakeroot ia32-libs cmake dh-autoreconf vim udev mercurial git python htop hwloc

sysstat ethtool

# apt-repository ppa:ubuntu-toolchain-r/test

# apt-get update

# apt-get install gcc-4.7 g++-4.7

# rm /usr/bin/gcc && rm /usr/bin/g++ // Current link refers to version 4.6

# ln -s /usr/bin/gcc-4.7 /usr/bin/gcc

# ln -s /usr/bin/g++-4.7 /usr/bin/g++

# apt-get install liblog4cplus-dev libccgnu2-1.7-0 libcommoncpp2-dev libyaml-dev

Download the EtherCAT master and the PdServ library from etherlab.org and unpack

them. There should be folder called ”pdserv-1.1.0” and ”ethercat-1.5.2”. The following

commands are executed starting from the same level as the named folders.

$ mkdir pdserv-1.1.0-build

$ cd pdserv-1.1.0-build

$ cmake -DCMAKE INSTALL PREFIX=/vol/opt/etherlab ../pdserv-1.1.0

$ make

$ make install // Make sure the folder etherlab has user rights

$ cd .. && cd ethercat-1.5.2

$ ./configure --enable-generic=yes --enable-8139too=no --enable-e1000e=yes

--prefix=/vol/opt/etherlab --with-linux-dir=/usr/src/linux-headers-$(uname -r)

--enable-cycles=yes --enable-debug-if=yes --enable-debug-ring=yes

// See section 4.3.2

$ make

$ make modules

# make install

# make modules install

# depmod

# ln -s /vol/opt/etherlab/etc/init.d/ethercat /etc/init.d/ethercat

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# cp /vol/opt/etherlab/etc/sysconfig/ethercat /etc/sysconfig/ethercat

# nano /etc/sysconfig/ethercat

Minimal configuration (see section 4.3.2 for more details):

MASTER DEVICE=<MAC-ADDRESS of used ethernet device>

DEVICE MODULES="generic", or native driver (e.g. e1000e)

# touch /etc/udev/rules.d/99-EtherCAT.rules

# nano /etc/udev/rules.d/99-EtherCAT.rules

Paste in the following lines for automatic device node generation with user read-access

KERNEL=="EtherCAT[0-9]*", MODE="0664"

Setting up the development environment

The development environment can be either setup on the target system as well or on a

separated platform. This environment consists mainly of the EtherLAB library as well as

the Matlab/Simulink software. At this point Matlab and Simulink Coder is assumed to

be already installed. Moreover a linux operating system used for the development envi-

ronment. This guideline describes the installation process of the EtherLAB library, which

is developed by [4].

All EtherLAB components are installed under /vol/opt/etherlab. Therefore the cor-

responding directory is created and user rights are assigned to.

# mkdir -p /vol/opt/etherlab

# chown :username /vol/opt/etherlab

# chmod 775 /vol/opt/etherlab

$ mkdir /vol/opt/etherlab/src

The C compile GCC and the builsystem cmake has to be installed on the development

system. Matlab 2014b is used for this project, which uses the gcc version 4.7. In addi-

tion the source for the EtherLAB library is obtained from etherlab.org and extracted to

/vol/opt/etherlab/src. The name of the folder is etherlab-2.1.0.

# apt-get install gcc-4.7 cmake

Check, if gcc version 4.7 is linked correctly

$ gcc -version

If another gcc version is shown, create new symbolic link

# rm /usr/bin/gcc

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# ln -s /usr/bin/gcc-4.7 /usr/bin/gcc

Now, EtherLAB library is installed

$ cd /vol/opt/etherlab/src

$ mkdir etherlab-2.1.0-build

$ cd etherlab-2.1.0-build

$ cmake -DPREFIX=/vol/opt/etherlab ../etherlab-2.1.0

$ make

$ make install

If a Matlab version later than 2012b is used, then the c-file ec slave3.c under

/vol/opt/etherlab/rtw/blocks/EtherCAT has to be updated. The updated c-file is ob-

tained from www.symbitron.eu

$ cd /vol/opt/etherlab/rtw/blocks/EtherCAT

$ wget http://symbitron.eu/wiki/images/b/b6/Ecslave.c

$ mv ec slave3.c ec slave3.c.bak

$ mv Ecslave.c ec slave3.c

The EtherLAB library is installed under /vol/opt/etherlab/rtw. In order to setup

EtherLAB within Matlab, the pathdef.m file has to be writable for users.

# chown :username $MATLABDIR/toolbox/local/pathdef.m

# chmod 775 $MATLABDIR/toolbox/local/pathdef.m

Open Matlab and execute the following commands in the command window in order to

setup EtherLAB

# cd /vol/opt/etherlab/rtw

# setup etherlab

Simulink Code Generation - Recommendations

As part of this thesis the automatic code generation of Simulink has been used. In order

to obtain e�cient and optimised C code, there are certain steps and rules, which should

be applied, while designing the protection algorithm. The recommendations are mainly

based on [17].

Design stage:

• Use bus creator instead of mux. Bus creator are coded as c structures and therefore

makes the debugging process much easier

• Use unique names for busses

109

• Define the variables types. Simulink uses 64-bit double as the default data type,

which may be a bit oversized for some variables

• In case of implemented MATLAB functions, add %#codegen at the beginning of the

function in order indicate the code generation purpose to Simulink

Code generation:

• Use discrete step solver

• Code interface: Use classic call interface

• Each time step in Simulink is represented by di↵erent period of task

Description of developed Graphical User Interface

As seen from above, there are many di↵erent parameters, which have to be tune ac-

cordingly, in order to guarantee a reliable and secure operation of the protection system.

Therefore a graphical user interface (GUI) has been developed in order to provide a con-

venient approach of setting up the protection system.

Main window

110

Window for System configurations

Window for PDOC configurations

111

Window for phase selector configurations

Window for EtherCAT configurations

112

Datasheets of EtherCAT coupler - EK1100

EtherCAT EK1100

Power LEDs

E-bus

Couplersupply

Input forpower contacts

Power contacts

Link/Act In

Signal input EtherCAT

Link/Act Out

Signal output EtherCAT

EK1100 | EtherCAT Coupler

The EK1100 coupler connects EtherCAT with the EtherCAT Terminals (ELxxxx). One station consists of an EK1100 coupler, any number of EtherCAT Terminals and a bus end terminal. The coupler converts the passing telegrams from Ethernet 100BASE-TX to E-bus signal representation.

The coupler is connected to the network via the upper Ethernet interface. The lower RJ45 socket may be used to connect further EtherCAT devices in the same strand. In the EtherCAT network, the EK1100 coupler can be installed anywhere in the Ethernet signal transfer section (100BASE-TX) – except directly at the switch. The coupler BK9000 (for K-bus components) is suitable for installation at the switch.

Technical data EK1100

Task within EtherCAT system coupling of EtherCAT Terminals (ELxxxx) to 100BASE-TX EtherCAT networks

Data transfer medium Ethernet/EtherCAT cable (min. CAT 5), shielded

Distance between stations max. 100 m (100BASE-TX)

Number of EtherCAT Terminals up to 65,534

Protocol EtherCAT

Delay approx. 1 µs

Data transfer rates 100 Mbaud

Configuration not required

Bus interface 2 x RJ45

Power supply 24 V DC (-15 %/+20 %)

Current consumption from US 70 mA + (Â E-bus current/4)

Current consumption from UP load

Current supply E-bus 2000 mA

Power contacts 24 V DC max./10 A max.

Electrical isolation 500 V (power contact/supply voltage/Ethernet)

Operating/storage temperature -25…+60 °C/-40…+85 °C

Relative humidity 95 %, no condensation

Vibration/shock resistance conforms to EN 60068-2-6/EN 60068-2-27

EMC immunity/emission conforms to EN 61000-6-2/EN 61000-6-4

Protect. class/installation pos. IP 20/variable

Approvals CE, UL, Ex

Accessories

Cordsets cordsets and connectors

System

EtherCAT For further EtherCAT products please see the system overview

EK1100EtherCAT EtherCAT EK1100

Power LEDs

E-bus

Couplersupply

Input forpower contacts

Power contacts

Link/Act In

Signal input EtherCAT

Link/Act Out

Signal output EtherCAT

BECKHOFF New Automation Technology We reserve the right to make technical changes.

113

Datasheets of EtherCAT slave - EL1034

Digital Input EL1034

Signal LED4

Signal LED2

Signal LED3

Signal LED1

Power contact+24 V

Power contact 0 V

Input 1

GND1

GND3

Input 3

Input 2

GND2

GND4

Input 4

Top view

Contact assembly

EL1034 | 4-channel digital input terminal 24 V DC, potential-free inputs The EL1034 digital input terminal acquires the binary 24 V control signals and transmits them, in an electrically isolated form, to the higher-level automation system. The EtherCAT Terminal contains four channels that indicate their signal state by means of light emitting diodes. The EL1034 features electrical isolation of individual channels. The input signal meets the requirements of EN 61131-2, type 1.

Technical data EL1034 | ES1034

Connection technology 2-wire

Specification EN 61131-2, type 1

Number of inputs 4

Nominal voltage 24 V DC (-15 %/+20 %)

“0“ signal voltage -3…+5 V (EN 61131-2, type 1)

“1“ signal voltage 15…30 V (EN 61131-2, type 1)

Input current typ. 3 mA (EN 61131-2, type 1)

Input filter typ. 10 µs

Distributed clocks –

Current consumption power contacts

–

Current consumption E-bus typ. 90 mA

Electrical isolation 500 V (E-bus/field potential)

Bit width in the process image 4 inputs

Configuration no address or configuration setting

Special features 4 electrically isolated fast inputs, potential-free

Weight approx. 50 g

Operating/storage temperature 0…+55 °C/-25…+85 °C





Pluggable wiring for all ESxxxx terminals

Approvals CE, UL, Ex

Digital Input EL1034

EL1034Digital Input

Signal LED4

Signal LED2

Signal LED3

Signal LED1

Power contact+24 V

Power contact 0 V

Input 1

GND1

GND3

Input 3

Input 2

GND2

GND4

Input 4

Top view Contact assembly


114


Analog input EL3773

IL3 error

IL2 error

IL1 error

Meas. error

L3 error

L2 error

L1 error

Run LED

L1

L2

L3

N

IL1

IL2

IL3

IN

Top view

Contact assembly

EL3773 | Power monitoring oversampling terminal The EtherCAT Terminal EL3773 is a power monitoring terminal for state monitoring of a 3-phase AC voltage system. For each phase

voltages up to 288 Veff/410 V DC and currents up to 1 Aeff/1.5 A DC are sampled as instantaneous values with a resolution of 16 bits. The six channels are measured simultaneously based on the EtherCAT oversampling principle with a temporal resolution of up to 100 µs and passed on to the control system. The control system has sufficient computing power for true RMS or performance calculation and complex custom algorithms based on the measured voltages and currents. Through the oversampling principle the terminal is able to measure at significantly shorter intervals than the cycle time of the control system. AC and DC parameters must be connected and measured with a common reference potential. The EL3773 supports distributed clocks and can therefore measure synchronous with other EtherCAT devices.

Technical data EL3773

Number of inputs 3 x current, 3 x voltage

Technology 3-phase power monitoring for alternating/direct voltages

Oversampling factor n = 1…100 selectable

Distributed clocks yes

Conversion time min. 100 µs, all channels simultaneously

Measured values current, voltage as instantaneous values (oversampling)

Measuring voltage max. 500 V AC 3~ (ULX-N: max. 288 V AC), max. 410 V DC

Measuring current max. 1 A (AC)/1.5 A (DC), via measuring transformers x A AC/1 A AC

Resolution 16 bit (incl. sign)

Measuring error 0.5 % relative to full scale value

Electrical isolation 2,500 V


–


Special features oversampling, AC/DC measurement, single-phase operation also possible, adjustable hardware filters

Weight approx. 75 g






Analog input EL3773

EL3773Analog input

IL3 errorIL2 errorIL1 errorMeas. error

L3 error L2 error L1 error Run LED

L1

L2

L3

N

IL1

IL2

IL3

IN



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Digital Output EL2624

Signal LED4

Signal LED2

Signal LED3

Signal LED1

Power contact

Power contact

13

14

33

34

23

24

43

44

Top view

Contact assembly

EL2624 | 4-channel relay output terminal 125 V AC/30 V DC The EL2624 output terminal has four relays each of which has a single contact. The relay contact is suitable for use at up to 125 V AC or 30 V DC. The EtherCAT Terminal indicates its signal state by means of light emitting diodes. The EL2624 has potential-free contacts. The power contacts are looped through.

Technical data EL2624 | ES2624

Connection technology relay output

Number of outputs 4 x make contacts

Rated load voltage 125 V AC/30 V DC

Load type ohmic


Ohmic switching current 0.5 A AC/2 A DC

Inductive switching current no data

Minimum permitted load 10 µA at 10 mV DC with intact contact coating




–

Bit width in the process image 4 outputs

Operating cycles mech. (min.) 1 x 108

Operating cycles electr. (min.) 2 x 105 (1 A/30 V DC)

Configuration no address or configuration setting

Weight approx. 50 g






Pluggable wiring for all ESxxxx terminals

Approvals CE

Digital Output EL2624

EL2624Digital Output

Signal LED4

Signal LED2

Signal LED3

Signal LED1

Power contact

Power contact

13

14

33

34

23

24

43

44



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Digital output EL2798

Signal LEDs1…8

Power contact+24 V

Power contact 0 V

Output 1

Output 2

Output 3

Output 4

Output 5

Output 6

Output 7

Output 8

Output 1'

Output 2'

Output 3'

Output 4'

Output 5'

Output 6'

Output 7'

Output 8'

Top view

Contact assembly

EL2798 | 8-channel digital output terminal 30 V AC/DC, 2 A, solid state The digital EL2798 EtherCAT Terminal provides eight switches that can be used like a relay contact for AC/DC voltages. The electronic switch is realised through high-performance MOSFET transistors with low switch-on resistance. The switch itself is not short-circuit-proof, but due to its high pulse current capability it can cope with current until an external fuse triggers a switch-off. Wear resistance increases the availability of the application. Resistive and light inductive loads can be switched up to a rated voltage of 30 V AC/DC, completely resistive loads also up to a rated voltage of 48 V DC. High peak voltages and electromagnetic interference pulses are prevented.

Technical data EL2798

Connection technology 2-wire

Number of outputs 8 x make contacts

Rated load voltage 0…30 V AC/DC (only ohmic load: 0…48 V DC)


Short circuit current not short-circuit-proof, see peak current

Reverse voltage protection –

Switching times TON: typ. 1.8 ms, TOFF: typ. 30 ms

Output current 2 A (Â 10 A @ 55° C, see documentation)

Breakdown voltage 80 V

Peak current 5 A (100 ms), < 50 A (10 ms)

Isolation voltage (channel/channel)

< 200 V



Switching on speed typ. 1.8 ms, max. 5 ms

Switching off speed typ. 30 ms, max. 50 ms

On-resistance typ. 0.03 Ω

Conductor types solid wire, stranded wire and ferrule

Conductor connection solid wire conductors: direct plug-in technique; stranded wire conductors and ferrules: spring actuation by screwdriver

Rated cross-section solid wire: 0.08…1.5 mm²; stranded wire: 0.25…1.5 mm²; ferrule: 0.14…0.75 mm²

Special features substitute for relay contacts; potential-free






Related products

KL2798 8-channel digital output terminal, 30 V AC/DC, solid-state relay


Signal LEDs1…8

Power contact+24 V

Power contact 0 V

Output 1

Output 2

Output 3

Output 4

Output 5

Output 6

Output 7

Output 8

Output 1'

Output 2'

Output 3'

Output 4'

Output 5'

Output 6'

Output 7'

Output 8'




117

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