Details designASIC test platform development

By: Nadav Mutzafi Vadim Balakhovski

Supervisor: Michael Yampolsky

May 2009 1

DC to DC converterDC to DC converter Level translatorLevel translator PLL configurablePLL configurable FPGA implementation FPGA implementation

May 2009 2

Topic points

May 2009 3

Voltages for I/O(1+2) Umodel 4604 :Umodel 4604 :

◦ ◦ Input voltage – 3.3VInput voltage – 3.3V

◦ ◦ Output voltage - 0.8V to 3.3VOutput voltage - 0.8V to 3.3V

◦ ◦ Set by resistorSet by resistor

◦ ◦ current 4A , 5A peakcurrent 4A , 5A peak

◦ ◦ High efficiency High efficiency

umodel4604

May 2009 4

Voltages for core(3) Umodel 4604 :Umodel 4604 :

◦ ◦ Input voltage – 5VInput voltage – 5V

◦ ◦ Output voltage - 0.8V to 5VOutput voltage - 0.8V to 5V

◦ ◦ Set by resistorSet by resistor

◦ ◦ current 4A , 5A peakcurrent 4A , 5A peak

◦ ◦ High efficiency High efficiency

umodel4604

May 2009 5

Voltages for core(4) LT1931 :LT1931 :

◦ ◦ Input voltage – 5VInput voltage – 5V

◦ ◦ Output voltage – N5VOutput voltage – N5V

◦ ◦ Current – 350mACurrent – 350mA

LDO_N5V

May 2009 6

Voltages summary I/O voltages – two different I/O voltages – two different

voltages from 0.8V-3.3Vvoltages from 0.8V-3.3V Core voltages – negative 5V ,Core voltages – negative 5V ,

adjustable from 0.8V-5Vadjustable from 0.8V-5V Connector for 5V and for anotherConnector for 5V and for another

voltage from pc power supply.voltage from pc power supply.

May 2009 7

Level translator

May 2009 8

Level translator Auto bidirectionalAuto bidirectional Supporting 100MHzSupporting 100MHz Determinist voltages : Determinist voltages :

1.2V, 1.5V , 1.8V , 2.5V , 3.3V1.2V, 1.5V , 1.8V , 2.5V , 3.3V

level translator

May 2009 9

PLL configurable

PLL

I2C

OSC

May 2009 10

PLL configurable Programmable PLL , I2CProgrammable PLL , I2C Crystal Frequencies 8MHz-54 MHzCrystal Frequencies 8MHz-54 MHz Six output clock(3.3V recommend)Six output clock(3.3V recommend) Power supply 3.3VPower supply 3.3V

PLL ,I2C

FPGA Block Diagram

FPGA

Tester IN

Tester OUT

DDRA

DDRB

CONTROLER

PSDB

ASICPLLI2C

Tester IN module

Tester OUT module

Controller module FSMs:FSMs:

◦ ◦ Read – from DDR bank A to Tester INRead – from DDR bank A to Tester IN

◦ ◦ DUT – from tester in to DUT to tester out DUT – from tester in to DUT to tester out

◦ ◦ Write – from Tester OUT to DDR bank BWrite – from Tester OUT to DDR bank B

“ “Differentiator”Differentiator”

Buffering data from Tester INBuffering data from Tester IN

Bi – directional pins allocationBi – directional pins allocation

FSM Read States: zerozero IS PAGE 1 AVAILABLEIS PAGE 1 AVAILABLE READING FROM PAGE 1 READING FROM PAGE 1 START DELAY PAGE 1START DELAY PAGE 1 INIT COUNTER PAGE 1 INIT COUNTER PAGE 1 READ 1READ 1 FINISH READ FROM PAGE 1FINISH READ FROM PAGE 1 WHAT NEXT PAGE 1 WHAT NEXT PAGE 1 LOOP 1LOOP 1

FSM DUT States:

zerozero

Sending VectorsSending Vectors

HoldHold

FSM Write States: zerozero IS PAGE 1 AVAILABLEIS PAGE 1 AVAILABLE WRITING STATE PAGE 1WRITING STATE PAGE 1 START DELAY PAGE 1START DELAY PAGE 1 INIT COUNTER PAGE 1INIT COUNTER PAGE 1 WRITE 1WRITE 1 FINISH WRITE PAGE 1FINISH WRITE PAGE 1

““DifferentiatorDifferentiator””

Buffering input vectorsBuffering input vectors

Tester IN

Fifo IN

Controller

InputBuffer

FFPin 0

FF

Pin 94

Pin 1

Pin 95

Pin 93

Pin 2

ProcStarII

DDRBank A

PC

GUI

MAX (FIFO_IN_CLK) = DDR_CLK

PCI CLK 66MHz

BUFFER_CLK <= FIFO_IN_CLK /3

DDR CLK = 260 MHz

Rates constrainRates constrain Aim: 100Mhz * 96 = 9.6 Gbit/secAim: 100Mhz * 96 = 9.6 Gbit/sec

PCI: 66Mhz * 32 = 2.1 Gbit/secPCI: 66Mhz * 32 = 2.1 Gbit/sec

Multi Port: 260*32 = 8.3 Gbit/secMulti Port: 260*32 = 8.3 Gbit/sec

Bi-directional pins

Controller

InputBuffer

Pin 0

Pin 95

Pin 48

OutputBuffer

Pin 0

Pin 94

Pin 95

PSDB

ASIC

Pinout constrainPinout constrain

Max 96 input pinsMax 96 input pins

Max 48 Bi-directional pinsMax 48 Bi-directional pins

FPGA future tasks Trigger supportTrigger support

Errors definition Errors definition

System self test performanceSystem self test performance

I2C core I2C core