Detailed Syllabus – I Semester€¦ · 3. Introduction To VLSI Circuits And Systems John P....

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M.Tech. (VLSI)

Detailed Syllabus I Semester

Detailed Syllabus – I Semester

SCHOOL OF ENGINEERING & TECHNOLOGY

] POORNIMA UNIVERSITY

PU/2012-13/1st SEMESTER/SYLLABUS/SET/MTECH

DETAILED SYLLABUS: M. Tech. VLSI

1.1 FIRST SEMESTER

1.1.1 ADVANCED MATHEMATICS Code: MT601MA101 4 Credits [LTP: 4-0-0]

A. DETAILED SYLLABUS

B. RECOMMENDED STUDY MATERIAL:

S.No Title of the Book Author 1. Numerical methods in engg. & sc. B.S. Grewal 2. Numerical methods for engg & sc. Iyengar & M.K. Jain 3. Advanced Mathematics for Engineers Chandrika Prasad

1.1.1 VLSI Technology & Design Code: MT601EC102 4 Credits [LTP: 4-0-0]


Unit Contents

Optimization problem-Convex sets and functions. The SIMPLEX Algorithm-Forms of linear programming problem, geometry of linear programming, Organization of Tableau. Computational considerations for SIMPLEX Algorithm. Duality: Dual of linear programming, dual simplex problem, Primal-dual algorithm. Algorithms and Complexity-shortest path, max-flow, Dijkstra’s algorithm, min-cost flow, algorithm for graph search and matching; spanning trees and matroids; Integer Linear programming, Greedy algorithm, approximation algorithms; branch-and-bound; dynamic programming.

Unit Contents

Basic operation of CMOS inverter, detailed analysis of its noise margin propagation delay, power dissipation concept of layout & area, layout optimization & area estimation for a single as well as combinational logic circuits. Design of sequential logic circuits: Static & dynamic latches registers, dynamic transmission gate, CMOS gate, pipelining approach for optimize sequential circuits, NDRA-CMOS pipelined structure, non-bistable sequential circuits, Schmitt trigger. Implementation strategies for digital ICs, introduction of custom and circuit design, hierarchy cell based design array based implementation, building blocks of adder, multiplier, shifter, barrel shifter, algorithmic shifter and other arithmetic operators, power speed tradeoff in data path structure. Design memory & array structure memory architectures & building blocks, address decoder, sense amplifiers, driver/ buffers, timing control, power dissipation in memories, idea of testability and fault detection models.




S.No Title of the Book Author 1. CMOS Digital Integrated Circuits Analysis Sung-Mo (Steve) Kang, TMH 2. Essentials Of VLSI Circuits And Systems Kamran Eshraghian, Eshraghian, PHI 3. Introduction To VLSI Circuits And Systems John P. Uyemura, John Wiley & Sons 4. Modern VLSI Design Wayne Wolf, Pearson

1.1.3 ELECTIVE I Code: MT601EC103

4 Credits [LTP: 4-0-0]

1.1.3.1 EMBEDDED SYSTEM Code: MT601EC103.1 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Readings in Hardware/Software Co-Design G. De Micheli, Rolf Ernst, and Wayne Wolf 2. Embedded System Design: A Unified Hardware/Software

Introduction Frank Vahid and Tony D. Givargis, Addison Wesley

3. Programming Embedded Systems in C and C++ Michael Barr, O'Reilly 4. An Embedded Software Primer David E. Simon, Addison Wesley

1.1.3.2 Digital System Design Code: MT601EC103.2 4 Credits [LTP: 4-0-0]


Unit Contents

The concept of embedded systems design: definitions and constraints, hardware and processor requirements, embedded microcontroller cores, embedded memories. Examples of embedded systems. Technological aspects of embedded systems: special purpose processors; input-output design and I/O communication protocols; design space exploration for constraint satisfaction; co-design approach; example system design, interfacing between analog and digital blocks, signal conditioning, digital signal processing. Sub-system interfacing, interfacing with external systems, user interfacing. Design tradeoffs due to process compatibility, thermal considerations etc. Software aspects of embedded systems: real time programming languages and operating systems for embedded systems. specification refinement and design; design validation; Real Time operating system issues with respect to embedded system applications; time constraints and performance analysis.




S.No Title of the Book Author 1. Digital Design, 3rd edition, Pearson Education M.Morris Mano 2. Fundamentals of Logic Design Charles H.Roth, Jr. 3. Digital Principles and Design, Tata McGraw-Hill Donald D.Givone 4. Cmos Logic Circuit Design Uyemura, John P., Springer

1.1.3.3 ASIC & FPGA Architecture & Applications Code: MT601EC103.3 4 Credits [LTP: 4-0-0]



Unit Contents

Sequential Logic Design-Introduction, Basic Bistable Memory Devices, reduced characteristics and excitation table for bistable devices. Synchronous Sequential Logic Circuit Design: Introduction, Moore, Mealy and Mixed type Synchronous State Machines. Synchronous sequential design of Moore, Mealy Machines, Synchronous Counter Design, Hazards, Duality of sequential circuits, Different methods of minimization. Asynchronous Sequential logic design-Introduction, Primitive flow table and reduction, type of delays, Cycles and races, Excitation Map, Hazards, Essential hazards, Analysis of asynchronous sequential circuits. Symmetric and Iterative circuits-Symmetric functions, iterative functions, realization in tree form. Algorithmic State Machine: An Algorithm with inputs, digital solution, Implementation of traffic light controller, ASM charts, Design Procedure for ASMs. Introduction to programmable logic devices: PALs, PLDs, CPLDs and FPGAs. Introduction to VHDL: Data types, Concurrent statements, sequential statements, behavioral modeling.

Unit Contents

Types of ASICs: Design flow, CMOS transistors CMOS Design rules, Combinational Logic Cell, Sequential logic cell, Data path logic cell, Transistors as Resistors, Transistor Parasitic Capacitance, Logical effort, Library cell design, Library architecture . Programmable Asics, programmable asic logic cells and programmable ASIC i/o cells : Antifuse, static RAM, EPROM and EEPROM technology, PREP benchmarks , Actel ACT , Xilinx LCA , Altera FLEX, Altera MAX DC & AC inputs and outputs, Clock & Power inputs, Xilinx I/O blocks. Programmable asic interconnect, programmable asic design software and low level design entry: actel act, Xilinx lca, Xilinx Epld, Altera max 5000 and 7000, Altera max 9000, Altera flex, Design systems, logic synthesis, Half gate asic, Schematic entry, low level design language, Pla tools, Edif, Cfi design representation. Logic synthesis, simulation and testing: Verilog and logic synthesis, VHDL and logic Synthesis, Types of simulation, Boundary scan test, Fault simulation, Automatic test pattern generation, Introduction to JTAG. Asic construction, floor planning, placement and routing: System partition, Introduction to FPGA Architectures, FPGA design flow, Partitioning methods, Floor planning, Placement, physical design flow, Global routing, Detailed routing, Special routing, Circuit extraction and DRC.



S.No Title of the Book Author 1. Field programmable Gate arrays. Kluwer Brown, S. D., Francis, R. J., Rose, J. and

Vranesic, Z G. 2. Architecture and CAD for Deepsubmicron FPGAs. Kluwer Betz, V., Rose, J. and Marquardt, A. 3. FPGA Technology. Kluwer Trimberger, S. M.

1.1.4 ELECTIVE II 4 Credits [LTP: 4-0-0]

1.1.4.1 VLSI Digital Signal Processing Code: MT601EC104.1 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. VLSI Digital Signal Processing systems, Design and

implementation , Wiley, Inter Science Keshab K.Parhi

2. Practical Low Power Digital VLSI Design, Kluwer Academic Publishers Gary Yeap

3. Analog VLSI Signal and Information Processing , McGraw-Hill Mohammed Ismail and Terri Fiez

4. VLSI and Modern Signal Processing , Prentice Hall S.Y. Kung, H.J. White House, T. Kailath 1.1.4.2 Computer Architecture & Parallel Processing Code: MT601CS104.2


Unit Contents

Introduction To DSP Systems: Typical DSP algorithms; Iteration Bound – data flow graph representations, loop bound and iteration bound, Longest path Matrix algorithm; Pipelining and parallel processing – Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power. Retiming: Definitions and properties, an algorithm for unfolding, properties of unfolding, sample period reduction and parallel processing application, algorithmic strength reduction in filters and transforms – 2-parallel FIR filter, 2-parallel fast FIR filter, DCT algorithm architecture transformation, parallel architectures for rank-order Filters, odd- even merge- sort architecture, parallel rank-order filters. Fast convolution: Cook-Toom algorithm, modified Cook-Took algorithm, pipelined and parallel recursive and adaptive filters – inefficient/efficient single channel interleaving, Look- Ahead pipelining in first- order IIR filters, look-ahead pipelining with power-oftwo decomposition, Clustered Look-Ahead pipelining, parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters, pipelined adaptive digital filters, relaxed look-ahead, pipelined LMS adaptive filter. Bit Level Arithmetic Architectures: Scaling and round off noise- scaling operation, round off noise, state variable description of digital filters, scaling and round off noise computation, round off noise in pipelined first-order filters, bit-Level arithmetic architectures, parallel multipliers with sign extension, parallel carry-ripple array multipliers, parallel carry-save multiplier, 4x 4 bit Baugh-Wooley carry-save multiplication tabular form and implementation, design of Lyon’s bit-serial multipliers using Horner’s rule, bit-serial FIR filter, CSD representation, CSD multiplication using Horner’s rule for precision improvement.





S.No Title of the Book Author 1. Advanced Computer Architecture, TMH Kai Hwang 2. Designing efficient Algorithms for parallel computer, McGraw Hill

International M.J. Quinn

1.1.4.3 Low Power VLSI Design Code: MT601EC104.3 4 Credits [LTP: 4-0-0]


Unit Contents

Multiprocessors and Multicomputers: Multivector and SIMD Computers- PRAM and VLSI Models- Conditions of Parallelism- Program Partitioning and scheduling-program flow mechanisms, parallel processing applications- speed up performance law. Advanced processor technology: Superscalar and vector processors, memory hierarchy technology, virtual memory technology, cache memory organization, shared memory organization. Linear pipeline processors- Non linear pipeline processors- Instruction pipeline design-Arithmetic design- Superscalar and super pipeline design- Multiprocessor system interconnects- Message passing mechanisms. Vector processing principle- Multi vector Multiprocessors- Compound Vector processing-Principles of multithreading-fine grain multi computers- scalable and multithread architectures -Dataflow and hybrid architectures. Parallel programming models: Parallel languages and compilers- parallel programming environments- synchronization and multiprocessing modes- message passing program development- mapping programs onto multi computers- multiprocessor UNIX design goals-MACH/OS kernel architecture- OSF/1 architecture and applications.

Unit Contents

Introduction: Need for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits. Emerging Low power approaches. Physics of power dissipation in CMOS devices. Device & Technology Impact on Low Power Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device innovation. Simulation Power analysis: SPICE circuit simulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems. Monte Carlo simulation. Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic power analysis techniques, signal entropy. Low Power Design Circuit level: Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes, low power digital cells library Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-computation logic. Low power Architecture & Systems: Power & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design. Low power Clock Distribution: Power dissipation in clock distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew, chip and package co-design of clock network Algorithm and architectural level methodologies: Introduction, design flow, algorithmic level analysis and optimization, Architectural level estimation and synthesis.




S.No Title of the Book Author 1. Semiconductor Devices: Modelling And Technology Nandita Dasgupta, Amitava Dasgupta, PHI 2. Fundamentals Of Semiconductor Fabrication Gary S. May, S.M.Sze, John Wiley & Sons 3. Semiconductor Devices: Physics And Technology Simon M. Sze, John Wiley & Sons 4. Introduction To System Design Using Integrated Circuits Sonde, B.S., New Age International 5. Micro-Nano fabrication technologies And Applications Cui, Zheng, Springer

1.1.5 Lab 1 Code: MT601EC205 2 Credits [LTP: 0-0-2]


1.1.6 SEMINAR 1 Code: MT601EC406 2 Credits [LTP: 2-0-0]


Unit Contents

Minimum 3-4 four experiments to be performed in each subject compulsory as well as Electives.

Unit Contents

Students will be grouped in two to three, will have to decide final thesis area, download research papers from IEEE, ACM, Elsevier, Springer etc. Summarizing paper – Reading abstracts and finding ideas, conclusion, Advantages of Their approach, the drawbacks of the papers. Generalize results from a research paper to related research problems. Comparing the approach - Identify weaknesses and strengths in recent research articles in the subject. Practice sessions on how to read, analyze and summarize research papers. Students in group will have to deliver seminar, prepare a report and a review paper based on analysis.

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M.Tech. (VLSI)

Detailed Syllabus II Semester

Detailed Syllabus – II Semester



PU/2012-13/2nd SEMESTER/SYLLABUS/SOC/BCOM Page 2

DETAILED SYLLABUS: M. Tech. VLSI

1.1 SECOND SEMESTER

1.1.1 Algorithms for VLSI Design Automation Code: MT602EC101 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Algorithms for VLSI Design Automation, WILEY Student Edition S.H.Gerez 2. Algorithms for VLSI Physical Design Automation, 3rd

edition, Springer Naveed Sherwani

3. Computer Aided Logical Design with Emphasis on VLSI Hill & Peterson, Wiley

Unit Contents

PRELIMINARIES: Design Cycle, Physical Design, Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Depth First Search, Breadth first Search, Dijkstra & Prim’s Algorithm, Computational complexity. COMBINATORIAL OPTIMIZATION: Combinatorial Optimization Problems, Decision Problems, Complexity Classes, NP-completeness and NP-hardness, Backtracking, Branch and Bound, Local Search, Simulated Annealing, Tabu Search, Genetic Algorithms. VLSI BACKEND DESIGN – I: Placement & Partitioning: Basic Concepts, Problem Formulation, Constructive Placement, Iterative Placement, KL Algorithm for partitioning, Floorplanning: Basic Concepts, Floorplan Representation, Optimization Problems in Floorplanning, Shape Function & Sizing, Pin Assignment. VLSI BACKEND DESIGN –II: Routing: Basic Concepts of Global Routing, Problem Formulation, Efficient Rectilinear Steiner Tree Construction, Local Transformation for Global Routing, Basic Concepts of Local Routing, Area Routing, Channel Routing Models, Horizontal & Vertical Constraint Graphs, Left Edge Algorithm, Layout Compaction: Basic Concepts, Problem Formulation, Longest Path Algorithm for DAG and Cycles, Bellman-Ford Algorithm. MODELLING AND SIMULATION: Gate Level Modeling and Simulation, Switch level Modeling and Simulation. LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis HIGH-LEVEL SYNTHESIS: Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level Transformations. PHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies, Physical Design cycle for FPGA’s, Partitioning and Routing for segmented and staggered Models.



1.1.2 Research Methodology Code: MT602CS102 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Research Methodology R. Panneerselvam, PHI 2. Research Methodology: Methods and Trends Dr. C. R. Kothari 3. Research Methodology: A Step by Step Guide for Beginners Ranjit Kumar

Unit Contents 1. Overview of Research Methodology

Introduction, Mathematical tools for analysis, Research problems in management, Types of research, Research Process

2. Data Collection & Presentation Introduction, Primary data, Secondary data, Data Presentation

3. Review of Basic Statistical Measures Introduction, Measures of Central Tendencies, Measures of Variation, Measures of Skewness

4. Design and Analysis of Experiments

Introduction, Analysis of Variance, Completely Randomized design, Randomized complete block design, Latin square design, Duncan’s multiple Range Test, Functional design, second factorial experiment, Expected Mean Square.

5. Basic Multivariate Analysis Introduction, Correlation analysis, Forecasting, Linear regression & Time series

6. Algorithmic Research Introduction, Algorithmic Research Problems, Types,Types of Solution Procedures, Steps of development,

Steps of Algorithmic Research, Designof Experiments, Meta Heuristics for Combinational Problems. 7. Simulation Introduction, Need for simulation, Types, Simulation Languages, case study. 8. Report Writing and Presentation Introduction, Types of report, Guidelines for review draft, Report format, Typing Instructions, Oral

Presentations



1.1.3 ELECTIVE III 4 Credits [LTP: 4-0-0]

1.1.3.1 High Level System Design & Modeling Code: MT602CS103.1 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Abstract State Machines: A Method for High-Level System Design

and Analysis Egon Boerger, Robert Staerk, Springer

1.1.3.2 Artificial Neural Networks Code: MT602CS103.2 4 Credits [LTP: 4-0-0]


Unit Contents

System level design, description languages-SDL, SpecChart etc. Architectural synthesis for DSP applications. Formal Verification of digital systems-BDD based approaches, functional equivalence, finite state automata, ω-automata, FSM verification. Hardware-software partitioning, interface synthesis, case studies.

Unit Contents

Fundamentals: Introduction & Motivation, Biological Neural Networks and simple models, The Artificial Neuron Model; Hopfield Nets; Energy Functions and Optimization; Neural Network Learning Rules: Hebbian Learning Rule, Perceptron Learning Rule, Delta Learning Rule Widrow-Hoff Rule, Correlation Learning Rule, Winner –Take-All Learning rule, Out Star Learning Rule, summary of Learning rules. Single layer perceptron classifiers: Classification model, features and decision regions, discriminant functions, linear machine and minimum distance classification, nonparametric training concept training and classification using the discrete perceptron: algorithm and example, single layer continuous perceptron network for linearly separable classifications, multicategory Multilayer feed forward networks: Linearly nonseparable pattern classification delta learning rule for multiperceptron layer. Generalized Delta Learning rule. Feed forward Recall and Error Back Propagation Training; Examples of Error Back-Propagation. Training errors: Learning Factors; Initial weights, Cumulative Weight Adjustment versus Incremental Updating, steepness of activation function, learning constant, momentum method, network architecture Versus Data Representation, Necessary number of Hidden Neurons. application of Back propagation Networks in pattern recognition & Image processing, Madaunes: Architecture & Algorithms. Single Layer Feedback Network: Basic concepts of dynamical systems, mathematical foundation of discrete-time hop field networks, mathematical foundation of Gradient-Type Hopfield networks, transient response of continuous time networks. example solution of optimization problems: summing networks with digital outputs,




S.No Title of the Book Author 1. Introduction to Artificial Neural Systems, Jaico Publishers J.M.Zurada 2. Artificial Neural Networks, PHI Dr. B. Yagananarayana 3. Introduction Neural Networks Using MATLAB 6.0 S.N. Shivanandam, S. Sumati

1.1.3.3 VHDL Modeling & Digital System Design Code: MT602EC103.3 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Digital System Design using VHDL, ThomsonLearning Carles H Roth Jr 2. Fundamentals of digital logicdesign with VHDL, TMH Stephen Brown & Zvonko Vranesic 3. Digital design, PHI Jhon F Vakerly 4. VHDL: Analysis and modeling of Digital System, TMH Z. Navabi

minimization of the traveling salesman tour length, solving simultaneous linear equations. Associative Memories I: Basic concepts, linear associator basic concepts of recurrent auto associative memory, retrieval algorithm, storage algorithm, storage algorithms performance considerations, performance concepts of recurrent auto associative memory, energy function reduction capacity of recurrent auto associative memory, memory convergence versus corruption, fixed point concept, modified memory convergence towards fixed points, advantages and limitations.

Unit Contents

Introduction to VHDL: VHDL description, combinational networks, modeling flip flop using VHDL, VHDL model for multiplexer, compilation and simulation of VHDL, codes, modeling asequential machine, variables, signals and constants, mays VHDL operators, VHDL functions, VHDL procedures, packages and libraries, VHDL model for a counter. Advanced VHDL: Attributes, transport and inertial delays, operator over loading, multivalued logic and signal resolution, IEEE-1164, standard logic, generic, generates statements, synthesis of VHDL codes, synthesis exam les, file handling and TEXTIO. Design of Networks for Arithmetic Operations: Design of serial adder with accumulator, state graph for control networks design of binary multiplier, multiplication of signed binary numbers. Digital Design with SM Chart: State machine charts, derivation of SM charts, realization of SM charts, implementation of dice game, State machine Descriptions. Floating Point Arithmetic: Representation of floating point numbers, floating pointmultiplication, other floating point operations. Designing with Programmable Gate Arrays and Complex Programmable Logic Devices: Xlinx 3000 series FPGAs, Xlinx 4000 series FPGAs. Design Examples: Memories model , processor Design



5. A VHDL primer, PHI J. Bhaskar 6. Application Specific Integrated Circuits, PHI M.J.S Smith 7. FPGA Design, PHI Wolf

1.1.4 ELECTIVE IV 4 Credits [LTP: 4-0-0]

1.1.4.1 Pervasive Computing Code: MT602CS104.1 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Parallel Programming with MPI Morgan Kaufmann, Peter Pacheco 2. The Grid: Blueprintf for a New Computing Infrastructure Ian Foster and Carl Kesselman 3. Grid Computing: Making the Global Infrastructure a Reality Fran Berman, Geoffrey Fox, and Anthony G.

Hey (Wiley) 4. Grid Computing: Making The Global Infrastructure a Reality Fran Berman , Geoffrey Fox, Anthony J.G. Hey

Unit Contents

Fundamentals Evolution - Ubiquitous computing -Applied pervasive computing - Pervasive computing. Principles: Decentralization -Diversification -Connectivity Simplification -Pervasive information technology -Scenarios -Roaming Environment -Infrastructure - Personalized services and the virtual pervasive home. ADAPTATION IN MOBILE AND PERVASIVE COMPUTING Adaptability - Mechanisms for adaptation: spectrum of adaptation - Resource monitoring -Characterizing adaptation strategies -Example application architecture: Odyssey -Incorporating adaptations in applications -Support for adaptive applications. DATA DISSEMINATION, MANAGEMENT AND CONTEXT AWARE COMPUTING Publish subscribe mode -Information caching -Challenges for distributed data management -Data dissemination - Mobile data caching - Mobile cache maintenance schemes -Mobile web caching -Context: Definitions - Types -Core capabilities for context awareness - Types of context aware applications. MIDDLEWARE AND DEVICE TECHNOLOGY Middleware support - Mobile middleware - Puppeteer -Adaptation middleware -Agents - Mobile agents - Service discovery - Hardware: Batteries -Displays -Memory - Processor - Human Machine Interface - Operating systems: Palm OS -EPOC -Windows CE -QNX Neutrino -BeOS -Embedded Linux Comparison - Java for pervasive devices. PERVASIVE APPLICATION ARCHITECTURE AND EXAMPLES 9 Background - Scalability and Availability - Application architecture -Securing pervasive computing applications -Overview of classes - Use of the framework Usage examples: Retail -Airline check in and Booking -Sales force automation -Health care -Tracking -Car information systems -E -mail access via WAP and voice.



1.1.4.2 Digital Signal Processing in VLSI Code: MT602EC104.2 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. VLSI Digital Signal Processing systems, Design and

implementation , Wiley Keshab K.Parhi

2. Practical Low Power Digital VLSI Design, Kluwer Academic Publishers Gary Yeap

3. Analog VLSI Signal and Information Processing , McGraw-Hill Mohammed Ismail and Terri Fiez

1.1.4.3 Synthesis of Digital Systems Code: MT602EC104.3 4 Credits [LTP: 4-0-0]


Unit Contents

Introduction To DSP Systems :Typical DSP algorithms; Iteration Bound – data flow graph representations, loop bound and iteration bound, Longest path Matrix algorithm; Pipelining and parallel processing – Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power. Retiming: Definitions and properties, an algorithm for unfolding, properties of unfolding, sample period reduction and parallel processing application, algorithmic strength reduction in filters and transforms – 2-parallel FIR filter, 2-parallel fast FIR filter, DCT algorithm architecture transformation, parallel architectures for rank-order Filters, odd- even merge- sort architecture, parallel rank-order filters. Fast convolution: Cook-Toom algorithm, modified Cook-Took algorithm, pipelined and parallel recursive and adaptive filters – inefficient/efficient single channel interleaving, Look- Ahead pipelining in first- order IIR filters, look-ahead pipelining with power-oftwo decomposition, Clustered Look-Ahead pipelining, parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters, pipelined adaptive digital Filters, relaxed look-ahead, pipelined LMS adaptive filter. Bit Level Arithematic Architectures: Scaling and roundoff noise- scaling operation, roundoff noise, state variable description of digital filters, scaling and roundoff noise computation, roundoff noise in pipelined first-order filters, bit-Level arithmetic architectures, parallel multipliers with sign extension, parallel carry-ripple array multipliers, parallel carry-save multiplier, 4x 4 bit Baugh-Wooley carry-save multiplication tabular form and implementation, design of Lyon’s bit-serial multipliers using Horner’s rule, bit-serial FIR filter, CSD representation, CSD multiplication using Horner’s rule for precision improvement.

Unit Contents

Introduction:- Motivation and perspectives, Role of CAD in digital system design, levels of design, modeling& description and support of languages, Overview of Digital Design with Verilog HDL, Useful Modelling Techniques.

Architectural Level Synthesis:-Circuit specification, synthesis problem, Area and performance evaluation, optimization, Data path synthesis, Control- unit synthesis.

Scheduling:- Scheduling without resource constraints, the integer linear programming model, Hu’s Algorithm,




S.No Title of the Book Author 1. Synthesis and optimization of digital systems G. D. Micheli 2. High level synthesis, Kluwer Dutt, N. D. and Gajski, D. D 3. Introduction to Algorithms, McGraw-Hill T. H. Cormen, C. E. Leiserson and R. L. Rivest

1.1.5 LAB 2 Code: MT602EC205 2 Credits [LTP: 0-0-2]


1.1.6 SEMINAR II Code: MT602EC406 2 Credits [LTP: 2-0-0]


List scheduling, scheduling with pipelined resources, Loop folding.

Resource Sharing and Binding:- register sharing, multiport memory binding,bus sharing and binding, unconstrained minimum-area binding, concurrent binding and scheduling, resource sharing for pipelined circuits

Logic- Level Synthesis:-Two-level combinational logic optimization: Logic optimization principal, operation on two-level logic coners, algorithm for logic minimization.

Multi-level combinational logic optimization: algebraic model, Boolean model, algorithms for delay evaluation and optimization, rule –based system for logic optimization.

Sequential logic optimization: Sequential circuit optimization using state based models, timing issue, retiming, don’t care condition in synchronous, implicit state minimization.

Cell-Library Binding:-problem formulation and analysis, library binding based on structural and Boolean matching, rule- based library binding.

Low power Issue:-Low power issues in high level synthesis and logic synthesis

Unit Contents

Minimum 3-4 four experiments to be performed in each subject compulsory as well as Electives.

Unit Contents

Students grouped in two to three during Semester I, will now continue to download further the research papers in the area, analyze, allocate individually, the set of papers, Literature survey Overview – What is literature survey, Functions of literature survey, maintaining a notebook, developing a Bibliography Methods of data collection – Observation, survey, contact methods, experimental, determining sample design Searching for publications – Publication databases, search engines and patent databases, Find some/all of the references for a given paper, including those that are not on the web



Online tools – google, CiteSeer, ACM Digital Library, IEEE, The on-line Computer Science bibliography, Survey papers, Finding material not on the web, Searching patents Publishing a paper How to write scientific paper Structure of a conference and journal paper, how (and How Not) to write a Good Systems Paper: Abstract writing, chapter writing, discussion, conclusion, references, bibliography, and In-class discussion of technical writing examples, Poster papers, review papers, how to organize thesis Project report, How to write a research proposal? How research is funded? Research ethics – Legal issues, copyright, and plagiarism General advice about writing technical papers in English Tips for writing correct English Practice sessions on above will be conducted. Students will have to deliver seminar, prepare a report and a review paper based on analysis individually.

Page | 1

M.Tech. (VLSI)

Detailed Syllabus III Semester

Detailed Syllabus – III Semester



PU/2012-14/3rd SEMESTER/SYLLABUS/SET/MTECH/VLSI Page 2

M. Tech. VLSI Syllabus – Third Semester

1.1 Algorithms for VLSI Design Automation Code: MVL03101 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. Algorithms for VLSI Design Automation, WILEY Student Edition S.H.Gerez 2. Algorithms for VLSI Physical Design Automation, 3rd

edition, Springer Naveed Sherwani

3. Computer Aided Logical Design with Emphasis on VLSI Hill & Peterson, Wiley

1.2 Testing & testability of VLSI Code: MVL03102 4 Credits [LTP: 4-0-0]


Unit Contents

Unit-1 Unit-2 Unit-3 Unit-4 Unit-5 Unit-6 Unit-7

Algorithms and Complexity-shortest path, max-flow, Dijkstra’s algorithm, min-cost flow, algorithm for graph search and matching; spanning trees and matroids; Integer Linear programming, Greedy algorithm, approximation algorithms; branch-and-bound; dynamic programming. PRELIMINARIES: Introduction to Design Methodologies, Design Automation tools, Algorithmic Graph Theory, Computational complexity, Tractable and Intractable problems. General Purpose Methods For Combinational Optimization: Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming, Local Search, Simulated Annealing, Tabu search, Genetic Algorithms. Layout Compaction, Placement, Floor planning And Routing Problems, Concepts and Algorithms. MODELLING AND SIMULATION: Gate Level Modeling and Simulation, Switch level Modeling and Simulation. High-Level Synthesis: Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aspects of Assignment problem, High-level Transformations. Physical Design Automation Of FPGA’s: FPGA technologies, Physical Design cycle for FPGA’s, partitioning and Routing for segmented and staggered Models. Physical Design Automation Of Mcm’s: MCM technologies, MCM physical design cycle, Partitioning, Placement- Chip Array based and Full Custom Approaches, Routing, Maze routing, Multiple stage routing, Topologic routing, Integrated Pin, Distribution and routing, Routing and Programmable MCM’s.

Unit Contents

Unit-1 Unit-2

INTRODUCTION TO TEST AND DESIGN FOR TESTABILITY (DFT) FUNDAMENTALS: Modeling: Modeling Digital Circuits at Logic Level, Register Level and Structural Models. Levels of Modeling. Logic Simulation: Types of Simulation, Delay Models, Element Evaluation, Hazard Detection, Gate Level Event Driven Simulation. Physical Faults and their modeling: Stuck- at-Faults, Bridging Faults; Fault collapsing, Fault Simulation:




S.No Title of the Book Author 1. Essential of electronic testing for digital memory and mixed signal

VLSI circuits, Springer/BSP Books Michael L. Bushnell , Vishwani D. Agarwal

2. Digital system testing and testable design, jaico publishing house Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman

3. VLSI Test Principles and Architectures, Morgan Kaufmann L. T. Wang, C. W. Wu, and X. Wen 4. Design for Test for Digital ICs & Embedded Core Systems, Prentice

Hall. Alfred Crouch

1.3 ELECTIVE V


1.3.1 Analog & Mixed Signal ICs Code: MVL03103 4 Credits [LTP: 4-0-0]


Unit-3 Unit-4 Unit-5 Unit-6

Deductive, Parallel, and Concurrent Fault Simulation. Critical Path Tracing. ATPG for Combinational Circuits: D-Algorithm, Boolean Differences, PODEM Random, Deterministic and Weighted Random Test Pattern Generation; Aliasing and its effect on Fault Coverage. PLA Testing, Cross Point Fault Model and Test Generation. Memory Testing: Permanent, Intermittent and Pattern Sensitive Faults, Marching Tests: Delay Faults. ATPG for Sequential Circuits: Time Frame Expansion; Controllability and Observability Scan Design, BILBO, Boundary Scan for Board Level Testing, BIST and Totally self checking circuits. System Level Diagnosis & repair: Introduction, Concept of Redundancy, Spatial Redundancy, Time Redundancy, Error Correction Codes. Reconfiguration Techniques: Yield Modeling, Reliability and effective area utilization. BRIEF IDEAS ON EMBEDDED CORE TESTING: Introduction to Automatic in Circuit Testing (ICT), JTAG Testing Features.

Unit Contents Verilog And Logic Synthesis. VHDL And Logic Synthesis, Memory Synthesis,FSMSynthesis,Memory

Synthesis, Performance-Driven Synthesis. Simulation-Types Of Simulation, Logic Systems Working Of Logic Simulation,Cell Models, Delay Models6 State Timing Analysis,Formal Verification, Switch-Level Simulation Transistor-LevelSimulation. CAD Tools For Synthesis And Simulation Modelism And LeonardoSpectrum(Exemplar). TOOLS FOR CIRCUIT DESIGN AND SIMULATION USING PSPICE:Pspice Models For Transistors, A/D & D/A Sample And Hold Circuits Etc, And DigitalSystem Building Blocks, Design And Analysis Of Analog And Digital Circuits UsingPSPICE. AN OVER VIEW OF MIXED SIGNAL VLSI DESIGN:Fundamentals Of Analog And Digitla Simulation,Mixed Signal Simulator Configurations, Understanding Modeling, Integration To CAE Environmets, Analyses Of Analog Circuits Eg.A/D, D/A Converters, Up And Down Converters, Companders Etc. TOOLS FOR PCB DESIGN AND LAYOUT:An Overview Of High Speed PCB Design, Design Entry, Simulation And Layout ToolsFor PCB. Introduction To Orcad PCB Design Tools.




S.No Title of the Book Author 1. A Verilog Primer, BSP, 2003 J.Bhaskar 2. A Verilog HDL SynthesisBSP J.Bhaskar 3. SPICE FOR Circuits And Electronics Using PSPICE(2/E)(1992) Prentice Hall M.H.RASHID

4. ORCAD: Technical Reference Manual ,Orcad, USA

5. SABER: TechnicalReference Manual, Analogy Nic, USA

6. Aplication-SpecificIntegrated Circuits(1997). Addison Wesley M.J.S.SMITH

7. A VHDL SynthesisPrimer, BSP, 2003 J.Bhaskar

1.3.2 Scripting Languages for VLSI Design Automation Code: MT303LN103.1 4 Credits [LTP: 4-0-0]



S.No Title of the Book Author 1. “Learning PERL”, Oreilly Publications, 3rd Edn., 2000 Randal L, Schwartz Tom Phoenix 2. “Programming PERL”, Oreilly Publications, 3rdEdn., 2000. Larry Wall, Tom Christiansen, John Orwant, 3. “PERL Cookbook”, Oreilly Publications, 3rd Edn,2000 Tom Christiansen, Nathan Torkington

1.3.3 Hardware Software Co-design Code: MVL03105 4 Credits [LTP: 4-0-0]


Unit Contents Unit-1

Unit-2

Unit-3

Unit-4

Unit-5

Overview of Scripting Languages – PERL, CGI, VB Script, Java Script. PERL: Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied Variables. Inter process Communication Threads, Compilation & Line Interfacing. Debugger Internal & Externals Portable Functions. Extensive Exercises for Programming in PERL. Other Languages: Broad Details of CGI, VB Script, Java Script with Programming Examples.

Unit Contents Unit-1 Unit-2 Unit-3

CO- DESIGN ISSUES: Co- Design Models, Architectures, Languages, a Generic Co-design Methodology. CO- SYNTHESIS ALGORITHMS: Hardware software synthesis algorithms: hardware-software partitioning distributed system co-synthesis. PROTOTYPING AND EMULATION: Prototyping and emulation techniques, prototyping and emulation




S.No Title of the Book Author 1. Hardware / software co- design Principles and Practice”,2009,

Springer. Jorgen Staunstrup, Wayne Wolf,

2. Hardware / software co- design Principles and Practice, 2002, kluwer academic publishers

J.Staunstrup and W.Wolf

1.4 Lab III Code: MVL03207



1.5 DISSERTATION PART I

Credits [LTP: 0-0-10]

Unit-4 Unit-5 Unit-6 Unit-7 Unit-8

environments, future developments in emulation and prototyping architecture specialization techniques, system communication infrastructure TARGET ARCHITECTURES: Architecture Specialization techniques, System Communication infrastructure, Target Architecture and Application System classes, Architecture for control dominated systems (8051-Architectures for High performance control), Architecture for Data dominated systems (ADSP21060,TMS320C60), Mixed Systems. COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR ARCHITECTURES: Modern embedded architectures, embedded software development needs, compilation technologies practical consideration in a compiler development environment. DESIGN SPECIFICATION AND VERIFICATION: Design, co-design, the co-design computational model, concurrency coordinating concurrent computations, interfacing components, design verification, implementation verification, verification tools, and interface verification LANGUAGES FOR SYSTEM- LEVEL SPECIFICATION AND DESIGN-I: System – level specification, design representation for system level synthesis, system level specification languages. LANGUAGES FOR SYSTEM-LEVEL SPECIFICATION AND DESIGN-II: Heterogeneous specifications and multi language co-simulation the cosyma system and lycos system.

Unit Contents

3-4 Experiments based on each theory subject will have to be carried out.

Unit Contents

Dissertation Part I consist of Finalization of thesis title based on literature review carried out during Semester I and II

Objective finalization & presentation Design & experimentation details Experimentation work (partial) Part I thesis preparation Presentation and submission of research prepare based on experimentation carried out.



School of ENGINEERING & TEchNoloGY

Teaching Schemes – Fourth Semester

Subject Code Subject Name Teaching Scheme (Hrs per week) Credits Lec Tut Prac Dissertation Part II Presentation 4 4 Viva-Voce 16 Total 4 20

DISSERTATION PART II Credits [LTP: 0-0-20]

Unit Contents

Dissertation Part II includes completion of experimentation work final thesis writing, presentation to internal expert committee Research paper publication in some journal/conference Presentation / demonstration to external examiners.

Page | 1

M.Tech. (VLSI)

Detailed Syllabus IV Semester

Detailed Syllabus – IV Semester



PU/2013-15/4th SEMESTER/SYLLABUS/SET/MTECH/VLSI Page 2

M. Tech. VLSI Design Syllabus – Fourth Semester

DISSERTATION PART II Credits [LTP: 0-0-20]

Unit Contents

Dissertation Part II includes completion of experimentation work final thesis writing, presentation to internal expert committee Research paper publication in some journal/conference Presentation / demonstration to external examiners.

Detailed Syllabus – I Semester€¦ · 3. Introduction To VLSI Circuits And Systems John P....

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