Designing MIPS Processor (Single-Cycle) Presentation G
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Transcript of Designing MIPS Processor (Single-Cycle) Presentation G
08/01/2005 Presentation G
Designing
MIPS Processor
(Single-Cycle)
Presentation G
CSE 675.02: Introduction to Computer Architecture
Slides by Gojko Babić
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• We're now ready to look at an implementation of the system that includes MIPS processor and memory.
• The design will include support for execution of only:– memory-reference instructions: lw & sw, – arithmetic-logical instructions: add, sub, and, or, slt &
nor,– control flow instructions: beq & j,– exception handling: illegal instruction & overflow.
• But that design will provide us with principles, so many more instructions could be easily added such as: addu, lb, lbu, lui, addi, adiu, sltu, slti, andi, ori, xor, xori, jal, jr, jalr, bne, beqz, bgtz, bltz, nop, mfhi, mflo, mfepc, mfco, lwc1, swc1, etc.
Introduction
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• We shall first design a simpler processor that executes each instruction in only one clock cycle time.
• This is not efficient from performance point of view, since:– a clock cycle time (i.e. clock rate) must be chosen such that
the longest instruction can be executed in one clock cycle and
– that makes shorter instructions execute in one unnecessary long cycle.
• Additionally, no resource in the design may be used more than once per instruction, thus some resources will be duplicated.
• Because of that, the singe cycle design will require:– two memories (instruction and data),– two additional adders.
Single Cycle Design
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Elements for Datapath Design
16 32Sign
extend
g. Sign-extension unit
32 32
h. Shift left 2
ShiftLeft 2
P C
a . P r o g ra m c o u n te r
32 32
RegWrite
RegistersW riteregister
Readdata 1
Readdata 2
Readregister 1
Readregister 2
W ritedata
Data
Data
Register
numbers
b. Register File
5
5
5
32
32
32
c . A L U
A L U c o n t r o l
A L Ur e s u l t
A L UZ e r o
4
32
32
32
A dd S u m
d. A d d e r
32
32
32
MemRead
MemWrite
Datamemory
Writedata
Readdata
e. Data memory unit
Address
32
32
32
In struc tionm em ory
In struc tio nad dres s
Ins tru c tio n
f . In struc tion m em ory
32
32
MemRead=1MemWrite =0
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• Generic implementation:– use the program counter (PC) to supply instruction address,– get the instruction from memory,– read registers,– use the instruction to decide exactly what to do.
Registers
Register #
Data
Register #
Datamemory
Address
Data
Register #
PC Instruction ALU
Instructionmemory
Address
Abstract /Simplified View (1st look)
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Abstract /Simplified View (2nd look)
Figure 5.1
• PC is incremented by 4, by most instructions, and by 4 + 4×offset, by branch instructions.• Jump instructions change PC differently (not shown).
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• An edge triggered methodology• Typical execution:
– read contents of some state elements at the beginning of the clock cycle,
– send values through some combinational logic,– write results to one or more state elements at the end of the
clock cycle.
Our Implementation
Clock cycle
Stateelement
1Combinational logic
Stateelement
2
• An edge triggered methodology allows a state element to be read and written in the same clock cycle without creating a race that could to indeterminate data.
Figure 5.5
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P C
I n s t r u c t i o n
m e m o r y
R e a d
a d d r e s s
I n s t r u c t i o n
4
A d d
Incrementing PC & Fetching Instruction
Clock Figure 5.6with addition in red
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Datapath for R-type Instructions
R-type 000000 rs rt rd 00000 funct 31 26 25 21 20 16 15 11 10 6 5 0
add = 32sub = 34slt = 42and = 36 or = 37nor = 39
I n s t r u c t i o n
R e g i s t e r s
W r i t e
r e g i s t e r
R e a d
d a t a 1
R e a d
d a t a 2
R e a d
r e g i s t e r 1
R e a d
r e g i s t e r 2
W r i t e
d a t a
A L U
r e s u l t
A L U
Z e r o
R e g W r i t e
4I25-21
I20-16
I15-11
Clock
ALU control
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Complete Datapath for R-type Instructions
PC
Instruction
memory
Read
address
Instruction
4
Add
clock
Based on contents of op-code and funct fields,Control Unit sets ALU control appropriatelyand asserts RegWrite, i.e. RegWrite = 1.
R e g i s t e r s
W r i t e
r e g i s t e r
R e a d
d a t a 1
R e a d
d a t a 2
R e a d
r e g i s t e r 1
R e a d
r e g i s t e r 2
W r i t e
d a t a
A L U
r e s u l t
A L U
Z e r o
R e g W r i t e
4I25-21
I20-16
I15-11
Clock
ALU control
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Datapath for LW and SW Instructions
Control Unit sets: • ALU control = 0010 (add) for address calculation for both lw and sw• MemRead=0, MemWrite=1 and RegWrite=0 for sw• MemRead=1, MemWrite=0 and RegWrite=1 for lw
31 26 25 21 20 16 15 0
sw or lw opcode rs rt offset
In s tru c tio n
1 6 3 2
R e g is te r sW ritere g is te r
R e a dd a ta 1
R e a dd a ta 2
R e a dre g is te r 1
R e a dre g is te r 2
D a ta
m e m o ryW rited a ta
R e a dd a ta
W rited a ta
S ig n
e x te n d
A L Ure s u lt
Z e r o
A L U
A d d re s s
M e m R e a d
M e m W r ite
R e gW rit e
A L U 4I25-21
I20-16
I20-16
I15-0
control
M e m W r iteClock
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Datapath for R-type, LW & SW Instructions
Let us determine setting of control lines for R-type, lw & sw instructions.
P C
In s tru c t io n
m e m o ry
R e a d
a d d r e s s
In s tru c ti o n
1 6 3 2
R e g is te r s
W r ite
re g is te r
W r ite
d a ta
R e a d
d a ta 1
R e a d
d a ta 2
R e a d
re g is te r 1
R e a d
r e g is t e r 2
S ig n
e x te n d
A L Ur e s u l t
Z e r o
D a ta
m e m o ry
A d d r e s s
W r i te
d a ta
R e a d
d a ta
4
A d d
A L U
A L U control 4
M e m R e a d
M e m W r ite
A L U S rc
M e m t o R e g
0
10
1
1
0
RegDstClock
rs
rt
rd
MemRead =1MemWrite =0
Clock
offset
W r iteClock
R e g
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31 26 25 21 20 16 15 0
beq rs rt offset
Datapath for BEQ Instruction
Branch target = [PC] + 4 + 4×offset
1 6 3 2S ig n
e x te n d
Z e roA L U
S u m
S h if t
le ft 2
T o b r a n c h
c o n tro l lo g ic
B ra n c h ta rg e t
P C + 4 fro m in s t ru c tio n d a ta p a th
In s tr u c tio n
A d d
R e g is te rsW r itere g is te r
R e a dd a ta 1
R e a dd a ta 2
R e a dre g is te r 1
R e a dre g is te r 2
W r ited a ta
R e g W r ite
A L U control4
rs
rt
Figure 5.9with additions in red
offset
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Datapath for R-type, LW, SW & BEQ
Figure 5.15with additions in red
M em toR eg
M em R ead
A L U S rc
R eg D st
PC
Ins tru ct io nm em ory
R eadaddress
Ins truction[31– 0]
Instruc tion [20 – 1 6]
Instruc tion [25 – 2 1]
A dd
4
16 32In struc tion [15– 0 ]
0
R egisters
W ritereg iste r
W r ited ata
W riteda ta
R e addata 1
R e addata 2
R eadreg iste r 1
R eadreg iste r 2
S ig nex te nd
ALUresult
Zero
D a tam e m ory
Add ress R eaddata
Mux
1
1
Mux
0
1
Mux
0
1
Mux
0
In struc tion [15– 1 1]
S hift
le ft 2
PC S rc
AL U
A ddA LU
resu lt
ALU control
clock
4MemRead=1MemWrite=0
rs
rt
rd
offset
M e m W r iteClock
W r iteClock R e g
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PC
Instructionm emory
Readaddress
Ins truction[31– 0]
Instruction [20 16]
Instruction [25 21]
A dd
Ins truction [5 0]
M em toReg
A LUO p
M em W rite
R egW rite
M em Read
B ranch
R egDst
A LUS rc
Instruction [31 26]
4
16 32Instruction [15 0 ]
0
0Mux
0
1
Contro l
AddALU
resu lt
Mux
0
1
RegistersW ritereg ister
W ritedata
R eaddata 1
R eaddata 2
R eadreg ister 1
R eadreg ister 2
Signextend
Mux
1
ALUresult
Zero
PCS rc
D atame m ory
W ritedata
R eaddata
Mux
1
Instruction [15 11]
A LUcontrol
Shift
le ft 2
A LU
Address
Control Unit and Datapath
Clock
MemRead=1MemWrite=0
Clock anded
Clock anded
Figure 5.17with additions in red
rs
rt
rd
funct
offset
opcode
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Op-code RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
000000 1 0 0 1 d 0 0 1 0
100011 0 1 1 1 1 0 0 0 0
101011 d 1 d 0 0 1 0 0 0
000100 d 0 d 0 d 0 1 0 1
Truth Table for (Main) Control Unit
• ALUOp[1-0] = 00 signal to ALU Control unit for ALU to perform add function, i.e. set Ainvert = 0, Binvert=0 and Operation=10• ALUOp[1-0] = 01 signal to ALU Control unit for ALU to perform subtract function, i.e. set Ainvert = 0, Binvert=1 and Operation=10• ALUOp[1-0] = 10 signal to ALU Control unit to look at bits I[5-0] and based on its pattern to set Ainvert, Binvert and Operation so that ALU performs appropriate function, i.e. add, sub, slt, and, or & nor
Input Output
R-type
lw
sw
beq
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Truth Table of ALU Control Unit
ALUOp Funct field ALU ControlALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 d d d d d d 0 0 100 1 d d d d d d 0 1 101 0 1 0 0 0 0 0 0 0 101 0 1 0 0 0 1 0 0 1 101 0 1 0 0 1 0 0 0 0 001 0 1 0 0 1 0 1 0 0 011 0 1 0 1 0 1 0 0 1 11
add
sub
add
sub
and
or
slt
nor
Input Output
1 0 1 0 1 0 0 1 1 1 00
Ainvert Bivert Operation
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R -fo r m a t Iw s w b e q
O p 0
O p 1
O p 2
O p 3
O p 4
O p 5
In p u ts
O u tp u ts
R e g D s t
A L U S r c
M e m to R e g
R e g W rite
M e m R e a d
M e m W rite
B ra n c h
A L U O p 1
A L U O p O
Op-codebits
5 4 3 2 1 0 RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
0 0 0 0 0 0 1 0 0 1 d 0 0 1 0
1 0 0 0 1 1 0 1 1 1 1 0 0 0 0
1 0 1 0 1 1 d 1 d 0 0 1 0 0 0
0 0 0 1 0 0 d 0 d 0 d 0 1 0 1
Design of (Main) Control Unit
RegDst =Op5Op4Op3Op2Op1Op0
ALUSrc= Op5Op4Op3Op2Op1Op0
+Op5Op4Op3Op2Op1Op0
0
0
…
0…
0
Figure C.2.5
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PC+4 [31– 28]
Datapath for R-type, LW, SW, BEQ & J
PC PC31-28 || jump_target || 00
31 26 25 0
j jump_target
PC[31-28]
Add 2zeros
Figure 5.24with correction in red
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Datamemory
Readdata
Writedata
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction [15– 11]
Instruction [20– 16]
Instruction [25– 21]
Add
ALUresult
Zero
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
JumpRegDst
ALUSrc
Instruction [31– 26]
4
Mux
Instruction [25– 0] Jump address [31– 0]
Signextend
16 32Instruction [15– 0]
1
Mux
1
0
Mux
0
1
Mux
0
1
ALUcontrol
Control
Add ALUresult
Mux
0
1 0
ALU
Shiftleft 2
26 28
Address
shiftleft 2
g. babic Presentation G 20
Design of Control Unit (J included)
…
0
J 0 0 0 0 1 0 d d d 0 d 0 d d d
Op-codebits
5 4 3 2 1 0 RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
0 0 0 0 0 0 1 0 0 1 d 0 0 1 0
1 0 0 0 1 1 0 1 1 1 1 0 0 0 0
1 0 1 0 1 1 d 1 d 0 0 1 0 0 0
0 0 0 1 0 0 d 0 d 0 d 0 1 0 1
Jump
0
0
0
0
1
R -fo r m a t Iw s w b e q
O p 0
O p 1
O p 2
O p 3
O p 4
O p 5
In p u ts
R e g D s t
A L U S rc
M e m to R e g
R e g W r ite
M e m R e a d
M e m W rite
B ra n c h
A L U O p 1
A L U O p O
Jump
Jump =Op5Op4Op3Op2Op1Op0
No changes in ALU Control unit
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ALUOp Funct field ALU ControlALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0
0 0 d d d d d d 0100 1 d d d d d d 1101 0 1 0 0 0 0 0 0101 0 1 0 0 0 1 0 1101 0 1 0 0 1 0 0 0001 0 1 0 0 1 0 1 0011 0 1 0 1 0 1 0 111
Design of 7-Function ALU Control Unit
add
sub
add
sub
and
or
slt
ALU Control Lines(Binvert & Operation)
Input Output
Figure C.2.3with improvements
Bivert Operation
F 3
F 2
F 1
F 0
A L U O P 1 A L U O P 0
F 5
F 4
g. babic Presentation G 22
• Let us assume that the only delays introduced are by the following tasks:– Memory access (read and write time = 3 nsec)– Register file access (read and write time = 1 nsec)– ALU to perform function (= 2 nsec)
• Under those assumption here are instruction execution times: Instr Reg ALU Data Reg fetch read oper memory write Total R-type 3 + 1 + 2 + 1 = 7 nsec lw 3 + 1 + 2 + 3 + 1 = 10 nsec sw 3 + 1 + 2 + 3 = 9 nsec branch 3 + 1 + 2 = 6 nsec jump 3 = 3 nsec• Thus a clock cycle time has to be 10nsec, and clock rate = 1/10 nsec = 100MHz
Cycle Time Calculation
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• Single Cycle Problems:– what if we had a more complicated instruction like
floating point?– a clock cycle would be much longer, – thus for shorter and more often used instructions, such
as add & lw, wasteful of time.• One Solution:
– use a “smaller” cycle time, and– have different instructions take different numbers of
cycles.• And that is a “multi-cycle” processor.
Single Cycle Processor: Conclusion
Presentation G
Datapath for R-type, LW, SW, BEQ & J
PC[31-28]
Add 2zeros
PC
Instructionmemory
Readaddress
Instruction[31– 0]
Datamemory
Readdata
Writedata
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction [15– 11]
Instruction [20– 16]
Instruction [25– 21]
Add
ALUresult
Zero
Instruction [5– 0]
MemtoReg
ALUOp
MemWrite
RegWrite
MemRead
Branch
JumpRegDst
ALUSrc
Instruction [31– 26]
4
Mux
Instruction [25– 0] Jump address [31– 0]
Signextend
16 32Instruction [15– 0]
1
Mux
1
0
Mux
0
1
Mux
0
1
ALUcontrol
Control
Add ALUresult
Mux
0
1 0
ALU
26 28
Address
shiftleft 2
Control Unit Truth Table and Design
0 0 0 0 1 0 d d d 0 d 0 d d d
Op-codebits
5 4 3 2 1 0 RegDst ALUSrc
Memto-
Reg
Reg
Write
Mem
Read
Mem
Write Branch ALUOp1 ALUp0
0 0 0 0 0 0 1 0 0 1 d 0 0 1 0
1 0 0 0 1 1 0 1 1 1 1 0 0 0 0
1 0 1 0 1 1 d 1 d 0 0 1 0 0 0
0 0 0 1 0 0 d 0 d 0 d 0 1 0 1
Jump
0
0
0
01
R -fo r m a t Iw s w b e q
O p 0
O p 1
O p 2
O p 3
O p 4
O p 5
In p u ts
R e g D s t
A L U S rc
M e m to R e g
R e g W r ite
M e m R e a d
M e m W rite
B ra n c h
A L U O p 1
A L U O p O
Jump