Designing for Uncertainty: Critical Issues for New Nanoelectronic Technologies

Evelyn L. HuCalifornia NanoSystems Institute

UCSB

UNCERTAINTIES• Technologies for post-CMOS?• Architectures for new technologies

–Too early to extract device parameters? Plan large-scale systems?

– Uncertainties in device variability, failure modes

• Where are the sources of errors in system operation, in fabrication?

IC-DFN WorkshopHangzhou, August 15, 2006

A Few Candidate Technologies

Seeds of an architecture with defect tolerance

Beginnings….

Are We Finally at the Limits?

www.intel.com

Challenges to FurtherScaling (CMOS)

• Fundamental Physical Limits?– Leakage through dielectric– Small current drive,

electron statistics– Thermal noise– Interconnect delay

• High densities -> severe power dissipation

• Complexities in design & verification

• Economic Limits: the cost of reliable fabrication

Intel 45 nm Shuttle Test Chip

The Next Technology Generation

Continued faster, better (functional), cheaper• Performance

– Faster access time– Low power– Operates over wide temperatures– Non-volatile

• Manufacturability– Robust process latitude– Low-cost fabrication – Scalability

CHOICES? Benchmarks?

Selecting a post-CMOS Technology:choices

• Limitations of present (scaled) technology– Cross talk– Leakage– Charge modulation: statistical limitations of dopants– Maintaining high noise margins at reasonable

temperatures• Desired scalability

– Scale down in size: fabrication at the nanoscale– Scale up in complexity

Increased alignment accuracy Issues of interconnect delay

• Address limitations– Leakage– Cross talk– Charge modulation: statistical

limitations of dopants– Maintaining high noise

margins at reasonable temperatures• Desired scalability

– Scale down in size: fabrication at the nanoscale

– Scale up in complexity Increased alignment accuracy Issues of interconnect delay

Selecting a post-CMOS Technology:Choices

Spintronics:alternative

‘state variables’

Molecular Electronics

Carbon Nanotubetransistors

Simplify manufacturability

No one technology addresses ALL the challenges, or provide ALLthe desirable features for the next-generation technology

Single Electron Transistors

Quantum Cellular Automata

Limiting Leakage: Single Electron Transistors

EC = Q2/2C; Q = charge, C = capacitance

ETh ~ kT; EC >> kT

electron

For a small enough ‘island’ and very smallcapacitance, C, and for Ec >> Eth, THERE IS AN ENERGY COST TO ADDINGOR REMOVING CHARGE FROM THE ISLAND(no leakage)

Limiting Leakage: Single Electron Transistors

electron

For a small enough ‘island’ and very small capacitance, C, and for Ec >> Eth, THERE IS AN ENERGY COST TO ADDING OR REMOVING CHARGE FROM THE ISLAND (no leakage)

Ea = single-electron addition energy

Room temperature (25 meV) operation onlypossible for island diameter ~ few nanometers

Likharev, Electronics Below 10 nm

QCA Cell:Quantum dots with excess

charge

‘ 0’ ‘ 1’

Charge distributionfrom electrostatic repulsion

Addition of charge -> changed charge distribution, cellular ‘state’;

Truth Table

Amlani et al., Science 284, 280 [1999](Notre Dame)

Majority Gate Device

Nearest-neighbor interaction, local computation

Taking Advantage of Crosstalk: Quantum Cellular Automata

Fabrication & scale-up challenging, room temperature operation unlikely

Operation at Room Temperature:Magnetic Cellular Automata

Cowburn & Welland, Science 287, 1466 [2000]

Larger magnetic quantum dots (110 nm diameter),

Material: Ni80Fe14Mo3X Propagation of information

through exchange interaction between dots

Elongated dot, injector

Applied magnetic field

Input dot = ‘0’

Input dot = ‘1’

Using Spin to Transfer Information

GaMnAs Digital Alloys

Nanoscale-engineeredmaterials

Ferromagnetic spin filter

Semiconductor

Detector (Quantum well)

Spin-based Devices

New device concepts

Spintronic Technology

Powerfulnew information

technologies

David Awschalom, Art Gossard

UCSB

Experiments have shown long spin coherence lifetimes, but… Need to understand best material systems and device configurations Mechanism of control: Magnetic (e.g. MCA) or electronic?

• Address limitations– Leakage– Cross talk– Charge modulation: statistical

limitations of dopants– Maintaining high noise

margins at reasonable temperatures• Desired scalability

– Scale down in size: fabrication at the nanoscale

– Scale up in complexity Increased alignment accuracy Issues of interconnect delay

Selecting a post-CMOS Technology:Choices

Spintronics:alternative

‘state variables’

Single Electron Transistors

Quantum Cellular Automata

Challenges in device fabrication profound

Limited architectures for large scale systems

Incorporating natural nanoscale building blocks:Carbon Nanotubes

Beautiful structural order in carbon nanotubes

Exceptional electrical properties A single carbon nanotube can be made

into a transistor

Can dope single carbon nanotube both n-type and p-type

Enhanced compactness, multi-functionality

or a ring oscillator

Chen et al., Science 311, 1735 [2006]

Challenges: control of conductivity, doping, assembly

wire

wire

With very dense nanowires (20 nm) in cross-bar geometry

Stoddart & Heath, UCLA

Apply electricsignal

HP has taken these concepts tolarger-scale arrays, considered architectures and defect tolerances

Incorporating natural nanoscale building blocks:molecular switches

Developing the Molecular

Crossbar Platform

Cross-bar configuration, with molecular interlayer

Wu et al., Applied Physics A 80, 1173 [2005]

34 x 34 cross-bar memory,30 nm half-pitch, Ti/Pt

wires I-V of single device:

HYSTERETIC SWITCHING On= 1.5 positive bias, top

electrode; Off = negative bias ON/OFF ~ 10

HP has used this architecture for memory (a) and logic (b)

(a) Chen et al., Nanotechnology14, 462 [2003]; (b) G. Snider, Applied Phys.A 80, 1165 [2005]

Sample of ‘defect-tolerant’ nano-architecture

Lay out demultiplexer circuit on crossbar geometry

Demux circuit(not defect-tolerant)

Defect‘stuck open’

address

signal

Defect-tolerant circuit2-bit address passes through CMOS encoder -> 3 bit encoded address6-bit signal vector u -> redundant input address

Kuekes et al, Appl. Phys.A 80, 1161 [2005]

Sample of ‘defect-tolerant’ nano-architecture

Calculated percentage of usable nanowires, versus defect probability for different levels of redundancy, d (address bit)

Summary and Beginnings

Technologies for post-CMOS? A wide variety of candidates, at different levels of

maturity No one technology addresses ALL the challenges, or

provide ALL the desirable features for the next-generation technology

Architectures for new technologies Initial work on cross-bar geometry with molecular

switches Simple architectures, error-tolerant schemes provide

important benchmarks Consideration of appropriate architectures CRITICAL (even

in the face of uncertainty) to help sort and direct progress of technology

• Address limitations– Leakage– Cross talk– Charge modulation: statistical

limitations of dopants– Maintaining high noise

margins at reasonable temperatures• Desired scalability

– Scale down in size: fabrication at the nanoscale

– Scale up in complexity Increased alignment accuracy Issues of interconnect delay

Selecting a post-CMOS Technology:Choices

Spintronics:alternative

‘state variables’

Molecular Electronics

Carbon Nanotubetransistors

Simplify manufacturability

Single Electron Transistors

Quantum Cellular Automata

New Opportunities in Resilient, Manufacturable Information Systems?

The Emergent Integrated Circuit of the CellHanahan & Weinberg, Cell [2000]