Designer6 with HSPICE and HFSS Solver-On … UK/staticassets... · © 2010 ANSYS, Inc. All rights...

© 2010 ANSYS, Inc. All rights reserved. 1 ANSYS, Inc. Proprietary© 2010 ANSYS, Inc. All rights reserved. 1 ANSYS, Inc. Proprietary

Designer6 with

HSPICE and HFSS

Solver-On-Demand

for High-Speed I/O

Authors:

Greg Pitner

Venkatesh Seetharam

Presenters:

Oberdan Donadio

Alain Michel

© 2010 ANSYS, Inc. All rights reserved. 2 ANSYS, Inc. Proprietary

Design Task

• Validate a high-speed I/O channel including an IC

package and PCB design, and transistor-level driver

models

• Requirements and challenges

– Package geometry requires full-wave 3D modeling

– Want to capture the effect of the package-to-PCB

transition, with all the relevant coupling between the two

– Need to incorporate vendor-supplied encrypted driver

models

– Want to minimize model setup effort and simulation time


Solution: Designer 6.1

• Integrated design management

• Powerful hierarchical schematic creation

• State-of-the-art Nexxim circuit simulator

• Dynamic links to EM models

– HFSS, SIwave, Q3D, …

• Direct import PCB/Package designs

– Cadence, ODB++

• HFSS Solver-on-Demand

• HSPICE Solver-on-Demand


First Step: Designer Links For

Design Import

• AnsoftLinks for Cadence APD, Allegro, SiP

– Direct MCM, BRD, SiP import

– Run from either Cadence or Designer

• Must have Cadence installed

– Licensed thru AnsoftLinks option

• AnsoftLinks for ODB++

– Common PCB Manufacturing format

• Supported by Mentor, Zuken, Cadence, Altium


Full PCB Import with Designer

Links

• Complete PCB layout imported into Designer

• Parameterizable layers and stackup editors

Layout View Stackup Editor

Models courtesy of


Process Board

• Cutout region can either be auto generated or determined by user

• Select signal, power and ground nets to create cutout

U1

Package_cutout

Port1:TXPPAD7_pcbPort1:TXNPAD7_pcbPort1:RXPPAD7_pcbPort1:RXNPAD7_pcb

RXNPAD7_DIE

RXPPAD7_DIE

TXPPAD7_DIETXNPAD7_DIE


Process Package

• Cutout region can either be auto generated or determined by user

• Select signal, power and ground nets to create cutout


Add Solderballs to Package

Cutout

1. Layer SBALL_ATTACH added for attaching solderball. The distance between SBALL_ATTACH and

BASE layer determines the solderball height, so set UNNAMED_13 thickness to 0.13mm.

2. Edit BGAPAD definition as follows: Diameter = 0.3mm , Connection to “Below padstack”.

3. The rendered solderballs can be seen in the 3D Layout view

1 2 2

3


Merge PKG onto the PCB

• Copy “Package_cutout” from the project

tree

• Paste into “board_cutout1”

• Select “No copy” from the Synch Design

dialog

• Package and board have independent

stackup

• Package and board layout are

hierarchical

• Position the package relative to the

board


Airbox Dimensions

• Set the HFSS Extents for the “board_cutout” Design as:• Bounding box

• Dielectric padding = 0.1

• Airbox Horizontal = 0.1

• Airbox Vertical= 0.2

• Set the HFSS Extents for the “Package_cutout” Design as:• Bounding box

• Dielectric padding = 0.1

• View the final geometry in the 3D Layout Viewer

U1

Package_cutout

Port1:TXPPAD7_pcbPort1:TXNPAD7_pcbPort1:RXPPAD7_pcbPort1:RXNPAD7_pcb

RXNPAD7_DIERXPPAD7_DIE

TXPPAD7_DIETXNPAD7_DIE


Port Setup

• Configure a waveport for the PCB microstrips

– Select all 4 edges and create a port

• Horizontal factor = 2

• Vertical factor = 5

• Create lumped gap coax ports in the package

– Select the “DP” pad for nets RXNPAD7,

RXPPAD7, TXNPAD7, and TXPPAD7

– Toggle from via to pin

– Choose lumped gap coax port for HFSS port

type

– Set radial factor to 0.5


HFSS-SoD Analysis Setup

• Access HFSS analysis setup within Designer

• Define solution frequency, adaptive mesh settings and

interpolating sweep


Final Model

Dielectrics not rendered


Export to HFSS

• The merged package and board layout can be exported to HFSS


HFSS SoD Results

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00F [GHz]

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

Y1

board_cutout1Single Ended Insertion and Return Loss ANSOFT

0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00F [GHz]

-52.25

-50.00

-40.00

-30.00

-20.00

-10.00

0.00

Y1

Circuit1Differential Insertion and Return Loss ANSOFT

Curve Info

dB(S(Diff1,Diff3))LinearFrequency





Running HSPICE Within Designer

• Many vendor-supplied driver models are available as HSPICE-

encrypted models

• Designer can now integrate HSPICE as the circuit simulation engine

• Both Nexxim and HSPICE run models from Ansoft electromagnetic

model-extraction tools

Designer

Nexxim

HFSS SIwave Q3D PlanarEM

Design management

and schematic creation

Circuit simulation

Electromagnetic

modeling

Nexxim HSPICE


Working With HSPICE Models

• Vendor-supplied buffer

models are often not

provided as fully

encapsulated

subcircuits

.subckt

.ends

sample.inc

.lib

.end

include

file

library

filesubckt

• Instead, they are often embedded in sample

deck with many calls to libraries, include files,

subcircuits, etc.

Encryption may

hide additional

references

?

• Many supporting components and definitions in

an array of text files. Designer supports text

netlists, but how can they be translated to a

graphical schematic?


Building A Graphical Schematic

• HSPICE buffer model can be validated in a schematic environment

with a minimum of modification to the sample spice deck

Import the buffer subcircuit into

the schematic.

Give the schematic nets attached to

the external subcircuit nodes the

same name as the nodes

themselves. A script can largely

automate the process.

Nets are named identically as text

netlist. Add references to libraries

and include files and design runs

with no further changes.


Building A Graphical Schematic

• After building a working schematic equivalent to the vendor text

netlist, control signals can be pulled into the subcircuit and GUI

elements added


Add Package/PCB, Trace Models

• Add HFSS SoD model of package and board transition

• Add trace model from 2D Extractor

– Parameterizable


System Model

Complex transistor-level

models can result in

substantial run times for

long bit patterns.

Can we shorten run times

and maintain acceptable

accuracy?

HSPICE drivers

HFSS SoD model


Fast Transient Analysis:

QuickEyeTM

• Edge reponse of channel is calculated using ordinary transient

analysis

• Edge response is convolved with the time derivative of the bit

pattern to generate the output waveform

• Theory is based on LTI assumption

+ =

Edge Response Time-domain OutputsSpecific bit pattern


Fast Statistical Analysis:

VerifEyeTM

• Statistical (random) model of data pattern is combined with the edge

response to generate statistical eye diagrams and BER plots

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20__UnitInterval

1.00E-016

1.00E-015

1.00E-014

1.00E-013

1.00E-012

1.00E-011

1.00E-010

1.00E-009

1.00E-008

1.00E-007

1.00E-006

1.00E-005

1.00E-004

1.00E-003

1.00E-002

1.00E-001

1.00E+000

BE

R

Ansoft Corporation No_XTalk_wo_FFEXY Plot 1

Curve Info

AEYEPROBE(Vic_FE)VerifEyeAnalysis__Amplitude='-0.001962738042V'

AEYEPROBE(Vic_FE)1Imported__Amplitude='-0.001440603338V'

AEYEPROBE(Vic_FE)2Imported__Amplitude='-0.001440603338V'

Statistical

model of

data pattern+ =

Edge Response

Statistical Outputs

“Bathtub” plots

-0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20__UnitInterval

-100.00

-75.00

-50.00

-25.00

0.00

25.00

50.00

75.00

__

Am

plitu

de

[m

V]

Tx1 40in NON PE QERectangular Contour Plot 1 ANSOFTAEYEPROBE(r

1.0000e-010

1.0481e-009

1.0985e-008

1.1514e-007

1.2068e-006

1.2649e-005

1.3257e-004

1.3895e-003

1.4563e-002

1.5264e-001


What About Nonlinear Elements?

• QuickEye and Verifeye assume linear channels

• If drivers are nonlinear, are QE and VE still useful?

• Simple channel with driver that has a nonlinear self impedance:

Linear 50W resistance

Small nonlinearity

Larger nonlinearity

10 inch microstrip trace

• 3 curves tested for driver

impedance


Transient vs. QuickEye:

Linear Driver

• Compare transient and QuickEye simulations for simple test channel

with 3 different driver impedance characteristics

• For linear impedance, transient and QuickEye are essentially identical

– Numerical errors or bit pattern variations can result in small differences

Transient Eye Height = 618 mV QuickEye Eye Height = 619 mV



Small Nonlinearity

Transient Eye Height = 588 mV QuickEye Height = 587 mV



Larger Nonlinearity

Transient Eye Height = 563 mV QuickEye Height = 560 mV

• Test cases show that even though QuickEye and VerifEye make

an assumption of linearity, accuracy is often excellent for

moderately nonlinear drivers


QuickEye/VerifEye From HSPICE

• QuickEye and VerifEye are Nexxim features, but can be used in

conjuction with HSPICE SoD analysis

• Channel characterization employed by QE/VE is based entirely

on the step response

• Run transient simulations using HSPICE SoD to capture the step

response of the channel

– Separate rising and falling responses can be specified

– Both through and crosstalk responses


QuickEye/VerifEye From HSPICE

• Store step responses in text files

• Run Nexxim QE/VE using these external step responses

• QE/VE results will closely match transient if buffers are

approximately linear


QuickEye Results

• Nexxim QuickEye and HSPICE transient

– After capturing 100ns transient step response for rising, falling,

and crosstalk edges, 100,000 bits run in seconds in QuickEye

– Results consistent with HSPICE transient


VerifEye Results

• Generate statistical eye and “bathtub” plots at very low BER

• Add 20ps Gaussian jitter at the source


Conclusions

• Designer v6.1 is a powerful framework for

signal integrity modeling

• Solver-on-Demand technology enables 3D

HFSS simulation and HSPICE support

completely within the Designer environment– 3D HFSS modeling for unsurpassed accuracy with streamlined

setup within the Designer GUI

– Package-on-PCB simulation

– Runs industry-standard encrypted models for capturing detailed

driver characteristics

– QuickEye/VerifEye analysis available for extremely fast

simulations

Designer6 with HSPICE and HFSS Solver-On … UK/staticassets... · © 2010 ANSYS, Inc. All rights...

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Transcript of Designer6 with HSPICE and HFSS Solver-On … UK/staticassets... · © 2010 ANSYS, Inc. All rights...