DesignCon 2009 Coplanar Study Final - Molex

DesignCon 2009

A Study of Transmission Technology to Support 25-Gbps Serial Signaling For Parallel Architectures in Multi-Board Coplanar PCB Systems

David Brunker, Molex Inc. [email protected] Jason Squire, Molex Inc. [email protected] Tim Gregori, Molex Inc. [email protected] Joe Comerci, Molex Inc. [email protected] Mike Neumann, Molex Inc. [email protected]

Abstract Current I/O functions reflect the need to move high-speed serial information at very high data rates across a number of boards. A solution set is explored incorporating a coplanar interface with multiple parallel lanes operating up to 25-Gbps with NRZ encoding. Coplanar interconnect systems are often characterized by high crosstalk and poor return loss performance. This has regularly limited their use above 6 to 8-Gbps, particularly when simple and economical approaches are considered. This paper explores differential interface geometries using measurement and modeling methods, to define operational limits to 25-Gbps. Both connector and PCB structures are modified to form a decision matrix for performance optimization. Design practices leading to 25-Gbps system solutions and meeting simultaneous crosstalk and return loss targets will be proposed. Authors' Biography David Brunker is a Technical Fellow at Molex. He is involved with high-speed product direction and has developed products including I/O connectors, cabling and backplane transmission links. He has contributed to various Standards and MSA’s including IEEE 1394a and 1394b, DVI, VESA, EVC, SSA and the OIF and holds over 50 U.S. patents. Dave received his BS in Psychology with emphasis in Psychoacoustics from the University of Illinois at Urbana-Champaign. Jason Squire is a Senior Product Engineer working for Molex Commercial Product Division. He is involved in product development and SI analysis, simulation and high speed testing. His current activities include the design and analysis of high-speed connector products for I/O, backplane and socket applications. He received a B.Sc degree in Applied Physics from the University of Hull and an M.phil degree in Electrical Engineering from the Hong Kong University of Science and Technology. Joe Comerci has been working in the electrical connector industry for over 25 years. He is currently an Engineering Manager working for Molex Inc. in the Commercial Products Division. He leads a group of Product Design Engineers in the development of signal and low power interconnect products and holds over 30 patents. BSME, University of Illinois, Chicago. Tim Gregori is a Project Engineer working for Molex Commercial Product Division focused on new product development. His current activities include the design and development of high density board-to-board and high-speed connector products. He received a B.S degree in Industrial Technology from Northern Illinois University. Mike Neumann began his career designing printed circuit boards for a high energy physics lab in Illinois. From there, he's moved on to designing printed circuits for military training aircraft and finally joined Molex Commercial Product Division to create test boards for a majority of Molex' backplane connectors. In all, Mike has been designing printed circuits for nearly 30 years.

Introduction Accelerating needs for computing, storage and signal switching operations are driving novel and complex architectural responses. Economical scaling and expansion options are sought out. High-speed serial information transfer has opened the door for both data relief with the availability of densely packed information streams and data glut for the same reason. Highly dense storage and switching nodes can benefit from local expansion options that can relieve data glut by delivering very high data rates across many parallel lanes. Architectural diversity is extended when these parallel lanes can be realized across a multi-board system. The diversity of the solution is made viable when it can be accomplished simply and directly. While complex and highly redundant interconnect systems are considered for highly sensitive computing and storage applications, a need for intermediate range systems with very high speed signal processing capability that can respond to expansion needs is a compelling answer to data glut situations. This paper considers a solution set that incorporates a direct coplanar interface between boards and is capable of supporting multiple parallel lanes operating up to 25-Gbps NRZ data rates. Direct coplanar interfaces have been plagued by fundamental noise and return loss issues. Single-ended solutions have commonly exhibited over 5% and even more than 10% crosstalk levels with return loss often worse than -5 dB. Differential solutions offer relief but still exhibit non-monotonic insertion loss decay at Nyquist rates that would typically mitigate against 10-Gbps operation let alone advanced data rates to 25-Gbps. Consequently a review of differential contact and interface geometries is considered with an emphasis on limiting elements contributing to high-speed electrical granularity, where a smooth, non-granular electrical response is shown to be related to a progressive refinement in mechanical feature size. Progressive interface changes are characterized through measurement and modeling methods to define the onset of electrical granularity and disruptive non-monotonic insertion loss decay. This paper will demonstrate a firm delineation between well-behaved loss characteristics and the onset of non-linear characteristics that can present signal recovery problems. Elements responsible for the onset of non-linear transmission performance will be identified, modified and re-characterized to demonstrate a progressive response improvement. Both connector and PCB structures are modified with a focus on four core features including:

1) Terminal and contact region features, 2) Interface pad geometry, 3) Via structure and, 4) Ground-return systems.

These core features will be defined and modified to form a decision matrix for performance optimization.

Differential transfer characteristics, SDD11 and SDD21, will be reviewed for relative contribution to signal transfer anomalies. A range of associated ground return options will be defined and added to the response set composing the decision matrix. Progressive changes to the ground support structure to maintain a low inductance and well controlled response characteristic will be discussed. The importance of the ground support structure will be related to electrical response granularity which will be shown to be a key in defining the operational limits of individual transmission lines as well as group response behavior. Finally the components of the decision matrix will be reviewed in detail and composed to demonstrate an overview of a progressive transmission technology to support 25-Gbps serial signaling for parallel architectures in multi-board coplanar PCB systems.

Paper Organization

1. Direct Coplanar Interface Study 2. Electrical Granularity 3. Performance Targets 4. Model Development 5. PCB Development 6. Empirical Results (to metric targets) 7. Decision Matrix 8. Performance to IEEE KR 9. Conclusions

Direct Coplanar Interface Study

This paper considers a solution set that incorporates a direct coplanar interface between boards and has a development target to support multiple parallel lanes operating up to 25-Gbps NRZ data rates. The CoEdgeTM connector platform was the development vehicle for this project. The CoEdgeTM connector employs a single-piece connector configuration that interfaces directly to a PCB through edge contacts formed on the PCB. Contact pitch progression is 0.8mm using straightforward blanked contacts. In this design study all contacts across the connector were of exactly the same geometry. The impedance target was 100-Ohms differential although alternate design impedances such as 85-ohms differential and 50-Ohms single-ended have been reviewed. The design approach for these alternate system impedances was the same as the design approach discussed here.

Figure 1: CoEdgeTM board–to–board transmission structure The unique aspect of the CoEdgeTM board-to-board transmission structure is the absence of through-hole or SMT fixing features. The terminals interface to PCB edge contacts on both sides of the connector as shown in figure 1. In this manner any two PCB’s with contact edge pads can be joined. This unique contact configuration is versatile and can be used in a wide range of system architectures.

The transmission structure is wholly contained on one side of the board, either within the upper row or the lower row of contacts. All within-channel field coupling occurs on one side of the board only with virtually no coupling occurring from top to bottom. Figure 2 demonstrates connector placement between two PCB cards.

Figure 2: CoEdgeTM connector placed between two PCB cards

The serial placement of PCB card edge-to-connector-to-PCB card edge was ideal for this development study given the presence of two consecutive card edge interfaces. The design premise was that if electrical granularity could be reduced to a minimal level for a target data rate then a card edge interconnect system could be used to support very high data rates such as 25-Gbps. Having two card edge interfaces in the same channel would certainly be a good test platform for electrical granularity where card edge interfaces are a historical source for rough signal transfer characteristics. Electrical Granularity Direct coplanar interfaces employing PCB contact pads and traditional card edge technology have exhibited typically rough insertion loss decay and relatively poor return loss at higher frequencies. While these parameters have been helped by moving to differential signaling, performance above 5 GHz has not been competitive with 2-piece backplane connectors. In general 1-piece card edge connectors have frequently been moved out of consideration for advanced high speed serial transmission schemes. With high-speed architectures being stressed for performance, cost and diversity, additional interconnect options could provide desired relief. In order to make these alternate structures viable for consideration, of course they must demonstrate operational fitness. Operational fitness must be achieved through designs that define buildable structures and use available materials. Card edge connectors were considered to be very desirable candidates for review given their prolific nature and widely available materials.

Consequently, a core objective was to define repeatable structures that would be capable of operation up to 25-Gbps using differential signaling. Considering the historically rough performance of cards edge connectors, an almost literal focus on “smoothing out” the associated geometric structures was undertaken. The physical features of contact structures comprising the signal path were considered for their electrical smoothness from the signal injection at the contact pad on a first PCB to the line termination at the contact pad on a second PCB. See figure 3.

Figure 3: Ideal non-deviating longitudinal current flow

An ideal transmission structure from PCB 1 to PCB 2 would be electrically consistent and exhibit a low level of electrical granularity. Low electrical granularity was the primary objective. Although relative transmission loss was considered important, it was felt that if granularity could be controlled then good loss performance would follow. In order to maintain low electrical granularity, the transmission structures should support longitudinal current flow with minimal alternate or tangential current paths. In this case tangential current paths are defined as any conductive features extending beyond the root current path that are not needed to establish consistent transmission path impedance. Figure 4 depicts this condition.

Figure 4: Presence of tangential current flow creates temporal deviations when reflected

back into data stream.

Conductive extensions are frequently used to provide effective mechanical lead-in and terminal retention. These functions were reviewed and preserved. Only terminal

PCB 1 PCB 2

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candidates that could preserve these functions were prototyped. In some cases models were run for corner cases but these were not built.

G S+ S- G

0.8 mm pitch

G S+ S- G G S+ S- G

0.8 mm pitch 0.8 mm pitch

Figure 5: Consistent Dielectric Characteristics Maintained Across Each Channel Section

Figure 5 illustrates the core elements making up the differential signal pair. The signal pair includes two terminals that are broadside coupled and each terminal includes an adjacent ground return terminal. This minimum terminal functional set was always maintained for all testing. The terminal functional set was repeated across the connector body. In order to minimize any lateral differences within a given transmission channel, all terminal thicknesses were held constant. In addition, terminal pitch was maintained at 0.8 mm and all dielectric region characteristics were maintained between both signal-to-signal pairs and signal-to-ground pairs. In effect a bounding box was established with defined ground boundaries and the presentation of consistent dielectric features. This was purposely done to control coupling within the transmission channel. In this manner, the regional coupling within channel transmission elements was maintained with a minimum of dielectric granularity. Given consistent terminal spacing, terminal thickness and permittivity across subsequent dielectric region sections; propagation modes and temporal performance could be better controlled [1].

The electrical granularity along the length of the transmission channel was then reviewed.

Figure 6: Constant impedance root current path

Figure 6 shows a schematic view highlighting the root current path. A principal function of the design exercise was to identify a root current path that, without other conductive deviation, would define a constant impedance transmission line between signal injection at PCB Pad A and signal extraction at PCB Pad B. Figure 6 also identifies a small

tangential deviation of 0.1 mm at the terminal center. All other conductive features that were not part of the longitudinal current path along the center section were removed. Center section height was a factor that was varied through modeling to control the impedance along this section. Otherwise the region was kept smooth.

Figure 7: Lead-in geometry results in dominant tangential current path deviation

Figure 7 shows the dominant tangential deviation to the root current path at the distal ends of the terminal. These stub extensions are present as mechanical lead-in features to provide lead-in guidance and mechanical wipe to establish a good contact interface. The stub extensions were identified as a second factor responsible for generating potentially significant tangential delay currents that could distort the signal envelope and degrade return loss. The stub extension path was varied through modeling. The size of these lead-in features was typically held between 1 – 2 mm. The spring and contact region were generally kept smooth.

A primary performance goal was to control return loss and maintain smooth and monotonic insertion loss decay by minimizing electrical granularity. A design budget was established with two areas of focus; first to define a sensitivity level in mechanical length along the longitudinal current path that would establish a control region and second to define a maximum mechanical target extension as a source for tangential current within that region. Figure 7 depicts the terminal broken up into 4 regions along the longitudinal current path. The mechanical length of each region was defined by a wavelength fraction associated with an upper limit for a given data rate. The fundamental or Nyquist frequency was identified for a data rate target and an initial wavelength fraction of (wavelength/6) was chosen to represent a sensitivity level for discrete tangential current events to be recognized. It should be noted that other more rigorous wavelength fractions such as (wavelength/8) or (wavelength/10) could be used to develop sensitivity levels and associated regions, although good initial results were obtained with a (wavelength/6) design rule that typically could achieve a (-10dB) or better return loss performance for the target data rate.

The design exercise identified three initial data rates; a 10-Gbps baseline, 20-Gbps and 25-Gbps. The 10-Gbps baseline was included primarily for comparison purposes. 20-Gbps and 25-Gbps were actual design targets. The fundamental frequency associated with the data rate was determined and the effective regional dielectric constant was projected. The blanked terminals sit in an LCP housing with a considerable amount of air in the channel region yielding an effective dielectric constant that was typically 2.0.

The wavelength fraction was set at (wavelength/6) and the electrical delay associated with the wavelength fraction was then determined. The mechanical root current path length was determined as 14.3 mm. The wavelength to current path ratio was determined by dividing the root current path length by the transit distance associated with the wavelength fraction. This information is assembled in Table 1 for comparison.

Data Rate

(NRZ)

Nyquist Frequency

Regional

Dielectric Constant

(Effective)

Wavelength

Fraction

Root Current

Path Length

Wavelength to Current Path Ratio

(Regions)

Maximum Tangential Current

Path Deviation

10 Gbps

5.0 GHz 2.0 14.3

mm 2.02 3.54 mm

20 Gbps 10.0 GHz 2.0

14.3 mm 4.04 1.77 mm

25 Gbps 12.5 GHz 2.0

14.3 mm 5.06 1.41 mm

Table 1: Maximum Tangential Current Path Deviation (Mechanical)

Each of these regions was considered to represent a sensitivity level for the associated data rate. Each region was considered in a discrete design exercise as each region was considered capable of generating discrete tangential current events and degrading return loss at the data rate fundamental. The number of regions grows with increasing data rate thereby increasing the sensitivity of the design to any current path deviations. This design study considered the electrical granularity associated with 4-5 discrete regions for data rates up to 25-Gbps.

A design guideline, again using a (wavelength/6) rule, was used to limit any mechanical feature within each region not to increase beyond ½ of the electrical distance associated with a (wavelength/6) excursion. This was done to account for the delay to the boundary and back again. The maximum current path deviation targets within each region are shown in Table 1.

Performance Targets Three basic performance targets were established:

1. Insertion loss decay had to be smooth. Actual insertion loss was not considered as critical as achieving a smooth and monotonic decay.

2. Return loss was to be no greater than (-10dB) across the channel of interest at the fundamental frequency for the chosen data rate.

3. Crosstalk noise components (NEXT and FEXT) were to be limited to less than 1% operating in the channel of interest through the fundamental frequency for the chosen data rate.

Although insertion loss for the channel was not considered as a primary design driver, the channel performance was reviewed at (-18dB) and (-24dB) as indicators for possible SERDES signal recovery. Model Development Initially modeling was started with a mechanical form factor. The form factor provided a mechanical template for a buildable connector solution. The distinction was that the first focus was on creating a smooth transmission path with consistent impedance. Mechanical features that would potentially add any tangential current deviation were scrutinized for necessity or improved characteristics. The established design rules provided guidance throughout modeling.

Models were conducted using Ansoft HFSS with initial sweeps to 26-Ghz and eventually moving to 36-GHz to assess more advanced connector designs.

The first model set was conducted using a surface layer microstrip interface with split pad card edge contacts. This interface configuration, while effective for defining performance within the connector, was deemed vulnerable to crosstalk. The dominant coupling source was considered to be in the PCB structure. Consequently an embedded stripline structure was contemplated for the fabrication of a PCB set for characterization.

Two factors were reviewed for design impact; first center section terminal height (blanked terminal width) and secondly terminal lead-in that would result in a stub extension therefore acting as a source for tangential current generation. Representative modeling results are presented in the next four graphs (1-4). Parametric sensitivity was determined for the range of mechanical change as shown. In all four cases a performance inflection point occurred with a baseline stub extension of 1.76 mm. This baseline stub extension was adopted for a first contact prototype. The performance change noted occurred at approximately 10-GHz which was consistent with empirically demonstrated return loss and insertion loss deviation. Through 10-GHz even the baseline performance was smooth and monotonic.

Graph 1: Differential insertion loss with variation of center section height

Range of Variation to Center Section Height

• Maximum height = 0.5 mm

• Minimum height = 0.39 mm

Graph 2: Differential return loss with variation of center section height

Range of Variation to Center Section Height

• Maximum height = 0.5 mm

• Minimum height = 0.39 mm

Graph 3: Differential insertion loss with variation of stub length

• Range of Variation to Stub Length

• Maximum length = 1.76 mm

• Minimum length = 0.55 mm

Graph 4: Differential return loss with variation of stub length

• Range of Variation to Stub Length

• Maximum length = 1.76 mm

• Minimum length = 0.55 mm

PCB Development Initial modeling employed surface microstrip structures to interface with the card edge pads. While this structure was convenient to use and provided an interface termination, the coupling to adjacent channels was deemed unacceptably high. Near and far end crosstalk levels were demonstrating peaks to between (-30dB) to as high as (-26dB). These levels were higher than the (-40dB) target and it was felt that presence of these unacceptable levels was mainly associated with the rather open microstrip PCB constructions. As previously indicated, the connector was performing well with predictable modeling results for insertion loss and return loss. Another, more robust, PCB structure was contemplated to ensure that the connector-to-board interface was also performing as well as possible for crosstalk. An asymmetrical stripline PCB channel construction using via-in-pad technology was chosen. The microstrip models had employed a reduced-capacitance split active signal pad consistent with the AMC.0 footprint as shown in figure 8. This split pad design utilizes a non-active lead-in pad section to maintain contact cleanliness and mechanical control followed by a 1.2 mm active signal pad section. This same split pad design was used with the asymmetrical stripline construction chosen for the empirical evaluation. Ground return contact pads extended unbroken for the full pad height of 3.1 mm. Communicating signal vias from layer 1 to layer 2 were constructed directly within the pads with controlled depth drilling.

Figure 8: Split pad card edge configuration

Figure 9: PCB construction used to reduce coupling while maintaining channel-to-

channel isolation Figures 9 and 10 demonstrate the comparatively thin 2113 single ply construction that establishes tight coupling between signals on L2 and ground return on L1. Single ply 2113 glass was chosen both for thickness and a denser glass weave that would exhibit more consistent dielectric behavior [2] than other resin rich glass constructions such as 1080.

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Figure 10: PCB construction using single ply 2113 glass with full penetration ground drilling to eliminate need for sequential book manufacture

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Split Active Pad evaluated In a variety of lengths

To evaluate Return Loss Performance

Controlled depth communicating Via maintains 0.75 to 1Aspect Ratio

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Card Edge contact construction with asymmetrical stripline

configuration moves remote ground layers on L3 and L4

back from associated signal pad reducing coupling.

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Center Core Thickness VariableCenter Core Thickness VariableCenter Core Thickness Variable







Figure 10 also depicts through drilling of the ground features that ultimately eliminated any need for sequential PCB construction. The first PCB set (Rev A) constructed to characterize the channel performance employed a staggered ground topology from the primary to secondary side of the PCB. Initially this was done to reduce potential primary to secondary side coupling. This concern turned out to be unfounded with a high level of top-to-bottom isolation actually being realized. The second board set (Rev B) moved to ground-over-ground. This allowed for through drilling to pin ground planes and to communicate ground pads through the board using standard PCB construction. Eliminating the need for sequential PCB construction resulted in a construction that was much easier to build and more cost effective.

Figure 11: Rev B PCB construction with dual trace communication to L1 ground pads The Rev B PCB construction also went to a dual trace configuration to tie ground pads to ground layer 1. The 1.2 mm split pad construction was also varied to review associated return loss performance. Figure 11 shows the alternate 1.6 mm active pad section while figure 12 shows the minimized 0.9 mm pad construction.

Figure 12: Rev B PCB construction with alternate 0.9 mm active pad

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Both Rev A and Rev B board sets employed a standard 2.0 inch pad-to-SMA channel length constructed with a 50-Ohm single-ended build. The Rev B board set also added a special elongated 4.0 inch channel length (identified as the optical channel) with both 0.9 and 1.2 mm active pads. The 0.9 mm active pad option was added to evaluate a limit condition. A mechanical tolerance study was conducted to evaluate the design of a potentially minimized pad height. The 0.9 mm active pad was chosen to evaluate the performance limit of the system.

Figure 13: Rev A PCB construction with single ground trace to L1

Figure 14: Rev B PCB construction with dual ground trace to L1 Figures 13 and 14 compare the single to dual ground construction used to communicate ground pad to the layer 1 ground plane. Other than a range of added active pad sizes, ground-over-ground topology the dual ground trace to layer 1, the construction of the Rev B board set was quite similar to the Rev A set. Both sets used the same PCB stack with NelcoTM N4000-29 RoHS compliant laminate and both employed Molex Microwave compression fit SMA’s [3] to port the 50-Ohm split differential signals to outboard systems.

Empirical Results

revA board newconA diff p4_2728 P3_2728.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (A) with 1200 um split pad design and 100-Ohm channel. Insertion Loss:

• -10 dB intercept at 10.8 GHz • -18 dB intercept at 18.1 GHz • -24 dB intercept at > 20 GHz

Return Loss:

• -7 dB intercept at 11.0 GHz • -10 dB intercept at 9.8 GHz • -15 dB intercept at 6.3 GHz; -15 dB below held through DC

Comment: This test condition demonstrated very consistent performance with other similar channels and across the same type of terminals.

revB board newconA diff p4_2425 P3_2425 1200um.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 1200 um split pad design and 100-Ohm channel. Insertion Loss:


Return Loss:


Comment: This test condition demonstrated very consistent performance with other similar channels and across the same type of terminals. No significant performance change was noted between Rev A and Rev B board sets.

RevB newconnA P4_2221 P3_1918 NEXT.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 1200 um split pad design and 100-Ohm channel. NEXT:

• - 45 dB intercept at 3.5 GHz • - 40 dB through 12.3 GHz

RevB newconnA P4_2221 P3_1918 FEXT.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 1200 um split pad design and 100-Ohm channel. FEXT:

• - 49 dB intercept at 6.3 GHz • - 40 dB through 12.3 GHz

revB board newconA diff p4_2728 P3_2728 1600um.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with the longer 1600 um split pad design and 100-Ohm channel. Insertion Loss:


Return Loss:



revB optic newconB diff p2_2728 P1_2728 1200um.png Channel Identification: Newcon B refers to 2nd run of contact types on differential card (B) with 1200 um split pad design and 100-Ohm channel. The optical channel employs 4.0 inch transmission lengths on each line card. This is increased from the previous 2.0 inch length on the non-optical channels. Insertion Loss:

• -10 dB intercept at 7.2 GHz • -18 dB intercept at 11.8 GHz • -24 dB intercept at > 17.3 GHz

Return Loss:

• -7 dB intercept at > 20.0 GHz • -10 dB intercept at 13.4 GHz • -15 dB intercept at 7.5 GHz; -15 dB below held through DC


revB optic newconA diff p2_3031 P1_3031 900um.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 900 um split pad design and 100-Ohm channel. Insertion Loss:

• -10 dB intercept at 7.2 GHz • -18 dB intercept at 11.8 GHz • -24 dB intercept at > 17.3 GHz

Return Loss:

• -7 dB intercept at > 20.0 GHz • -10 dB intercept at 13.4 GHz • -15 dB intercept at 9.1 GHz; -15 dB below held through DC


RevB optic newconnA P2_3130 P2_2827 NEXT.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 1200 um split pad design coupling to 900um split pad and 100-Ohm channel. NEXT:

• - 46 dB intercept at 3.0 GHz • < - 46 dB through 20.0 GHz

RevB optic newconnA P2_3130 P1_2827 FEXT.png Channel Identification: Newcon A refers to 2nd run of contact types on differential card (B) with 1200 um split pad design coupling to 900um split pad and 100-Ohm channel. FEXT:

• - 52 dB intercept at 6.4 GHz • < - 52 dB through 20 GHz

revB optic P2_2827 P1_2827 shortail 1200um.png Channel Identification: Rev B optic refers to 4.0 inch (per card) channel with 1200um active pad and 1.37 mm lead-in in a 100-Ohm channel. Insertion Loss:

• -10 dB intercept at 7.0 GHz • -18 dB intercept at 12.0 GHz • -24 dB intercept at 17.7 GHz

Return Loss:

• -7 dB intercept at > 20 GHz • -10 dB intercept at 14.7 GHz • -15 dB intercept at 8.5GHz; -15 dB below held through DC

revB optic P2_3130 P1_3130 shortail 900um.png Channel Identification: Rev B optic refers to 4.0 inch (per card) channel with 900um active pad and 1.37 mm lead-in in a 100-Ohm channel. Insertion Loss:

• -10 dB intercept at 7.1 GHz • -18 dB intercept at 12.4 GHz • -24 dB intercept at 17.8 GHz

Return Loss:

• -7 dB intercept at > 20 GHz • -10 dB intercept at 18.4 GHz • -15 dB intercept at 9.1GHz; -15 dB below held through DC

revB optic P2_3130 P2_2827 shortail 900-1200umNEXT.png Channel Identification: Rev B optic refers to 4.0 inch (per card) channel with 900um active pad and 1.37 mm lead-in in a 100-Ohm channel. NEXT:

• - 46.8 dB intercept at 6.3 GHz • < - 46.8 dB through 20.0 GHz

revB optic P2_3130 P1_2827 shortail 900-1200umFEXT.png Channel Identification: Rev B optic refers to 4.0 inch (per card) channel with 900um active pad and 1.37 mm lead-in in a 100-Ohm channel. FEXT:

• - 46.9 dB intercept at 6.3 GHz • < - 46.9 dB through 20 GHz

Decision Matrix Lead-

In Performance Characteristic

Active Pad Height

1.6 mm 1.2 mm 1.2 mm Optical

0.9mm Optical

RL < -15 dB

5.1 GHz

6.3 GHz 7.5 GHz 9.1 GHz

RL < -10 dB

9.8 GHz 9.7 GHz 13.4 GHz 13.4 GHz

1.8 mm

NEXT/FEXT -40 dB thru 12.3 GHz

-46 dB thru 20 GHz

-46 dB thru 20 GHz

RL < -15 dB

8.5 GHz 9.1 GHz

RL < -10 dB

14.7 GHz 18.4 GHz

1.37 mm

NEXT/FEXT -46 dB thru 20 GHz

-46 dB thru 20 GHz

Table 2: Decision Matrix

The decision matrix in table 2 provides a summary of the channel performance when mechanical lead-in length is varied against the mechanical contact height associated with the active signal pad portion of the card edge contact fingers.

Performance to IEEE KR

Graph 5: Differential return limit to IEEE KR

Graph 6: Differential insertion loss deviation to IEEE KR

Return Loss Limit (KR)

CoEdge optical channel shaort tail & pad

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3

4

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Freq. (GHz)

ILD

(dB

) ILDmaxILDILDmin

Graph 7: Differential insertion loss limit to IEEE KR

Insertion Loss Limit (KR)CoEdge optical channel short tail & pad

-160

-140

-120

-100

-80

-60

-40

-20

00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Freq. (GHz)

Loss

(dB

)

ILILmax

Conclusions

1. A card edge interface can be effectively designed to achieve high levels of signal performance in 10 – 25 Gbps channels. 2. Using a low electrical granularity model for high-speed transmission structures can provide effective design guidance. 3. Using a wavelength/6 design rule can be useful in establishing an effective current

path sensitivity level. 4. Crosstalk noise components (NEXT and FEXT) can be limited to less than 1% operating in the channel (at Nyquist) using card edge technology. 5. Differential card edge interfaces using via- in-pad techniques combined with reduced height split contact pads can achieve very high data rates. 6. The core objective to define repeatable (coplanar) structures capable of operation up to 25-Gbps was met.

References [1] G. Blando, et.al, “Losses Induced by Asymmetry in Differential Transmission Lines,” DesignCon 2007 [2] J. Loyer, et.al, “Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies,” DesignCon 2007 [3] S. McMorrow, A. Neves, “A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions,” DesignCon 2004

DesignCon 2009 Coplanar Study Final - Molex

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