DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER...
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1 DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER USING BANDWIDTH- EFFICIENT HALF-SYMBOL-RATE-CARRIER OFFSET QUADRATURE PHASE SHIFT KEYING MODULATION By HYEOPGOO YEO A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2007
Transcript of DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER...
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DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER USING BANDWIDTH-EFFICIENT HALF-SYMBOL-RATE-CARRIER OFFSET QUADRATURE PHASE SHIFT
KEYING MODULATION
By
HYEOPGOO YEO
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2007
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© 2007 Hyeopgoo Yeo
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To my parents and family
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ACKNOWLEDGMENTS
I express my sincere gratitude to my supervisory committee chair, Dr. Jenshan Lin, for his
support throughout the course of this work. I also thank Professors William R. Eisenstadt,
Rizwan Bashirullah, and Li-Chien Shen for their advice on this work and their willing service
and guidance on my research. Without their invaluable support and encouragement, my
exploration in the research could not have come to fruition. I appreciate their interest in my work
and valuable suggestions and comments from the research proposal to its realization.
I thank my fellow colleagues (Tien-Yu Chang, Mingqi Chen, Lance Covert, Sangwon Ko,
Changzhi Li, Zehn Ning Low, Yachi Liu, Zivin Park) in the Radio Frequency Silicon on Chip
(RFSOC) Group for all the help they offered. My thanks also go to my other colleagues in
Electrical and Computer Engineering for their helpful discussion, advice, and friendship (Jongsik
Ahn, Kooho Jung, Sudeep, Jeashin Kim, Jeaseok Kim, Kwangchun Jung, Eunyoung Seok,
Dongha Sim, Kyujin Oh, Minsun Hwang, Seon-Ho Hwang). Their support and advice have
contributed immensely to my work. Also, I thank all of the friends who made my years at the
University of Florida such an enjoyable chapter of my life (Jangsup Yoon, SeungHwan Kim,
Sanghoon Choi, Jiwoon Yang, Choongeol Cho, Okjune Jeon). I acknowledge TSMC and UMC
for the technical and state-of-art fabrication support. I thank Inphi Corp. and Agilent
Technologies for their help on test equipments.
I dedicate this work and my deepest love to my parents who have given me utmost trust
and support throughout the years. I express my profound thanks to my wife, Seungyun Lee, for
her endless and unconditional love and support, and my dearest children, One and Myoung.
Without them, it would not have been possible to pursue my graduate studies.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS ...............................................................................................................4
LIST OF TABLES...........................................................................................................................7
LIST OF FIGURES .........................................................................................................................8
ABSTRACT...................................................................................................................................13
CHAPTER
1 INTRODUCTION ..................................................................................................................15
1.1 Motivations .......................................................................................................................15 1.2 Compensation Techniques of High Frequency Signal .....................................................19
1.2.1 Pre-Emphasis Signal...............................................................................................19 1.2.2 Broadband Circuit Technique.................................................................................20
1.3 Modulation Techniques ....................................................................................................22 1.3.1 Conventional Modulation Techniques ...................................................................22 1.3.2 Modulation Technique Using Half-Symbol-Rate-Carrier (HSRC)........................24 1.3.2.1 Why Not Carrier Modulation?.............................................................................25
2 HSRC PHASE SHIFT KEYING (PSK) MODULATIONS ..................................................27
2.1 Binary Modulation............................................................................................................27 2.2 Quadrature Modulations ...................................................................................................28
2.2.1 HSRC Quadrature PSK (QPSK) Modulation.........................................................28 2.2.2 HSRC Offset QPSK (OQPSK) Modulation ...........................................................28 2.2.3 HSRC Minimum Shift Keying (MSK) Modulation ...............................................30
2.3 Signal Spectrum................................................................................................................31 2.4 Bit Error Rate (BER) Performance...................................................................................33 2.5 DC-Free Signaling Based on HSRC-OQPSK Modulation...............................................41 2.5 Measurement of the HSRC-OQPSK Signal .....................................................................45 2.6 Summary...........................................................................................................................51
3 HSRC-OQPSK TRANSMITTER ..........................................................................................53
3.1 Transceiver Architecture ..................................................................................................53 3.1.1 A Conventional Serial Link Transceiver Architecture...........................................53 3.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture .......................................53
3.2 HSRC-OQPSK Transmitter Architecture.........................................................................55 3.2 Circuit Implementation.....................................................................................................57
3.2.1 Current-mode-logic (CML) Circuit ........................................................................57 3.2.2 CML Double-Edge Triggered D flip-flop ..............................................................61 3.2.3 Resistive Load Gilbert Mixer .................................................................................62
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3.2.4 Quadrature Phase Clock Generator ........................................................................63 3.2.5 I/Q Channel Signal Combining ..............................................................................66 3.2.6 Output Buffer..........................................................................................................66
3.3 Chip Design ......................................................................................................................69 3.3.1 Rev. 1 Transmitter ..................................................................................................69 3.3.2 Rev. 2 Transmitter ..................................................................................................71
3.4 Measurement.....................................................................................................................76 3.4.1 Rev.1 transmitter ....................................................................................................76 3.4.2 Rev. 2 transmitter ...................................................................................................81
4 HSRC-OQPSK RECEIVER DESIGN ...................................................................................91
4.1 Receiver Architecture .......................................................................................................91 4.2 HSRC-OQPSK Receiver (Rev. 1) ....................................................................................91 4.3 HSRC-OQPSK Receiver (Rev. 2) ....................................................................................93
4.3.1 Polarity-Type Costas Loop for Carrier Synchronization........................................94 4.3.2 A New Clock and Data Recovery (CDR) based on the Modified Costas Loop.....96
4.3.2.1 Phase detector characteristics.......................................................................97 4.3.2.2 Loop analysis..............................................................................................102 4.3.2.3 Noise characteristics...................................................................................104
4.3.3 Behavioral Model Simulations .............................................................................106 4.3.3.1 Phase error..................................................................................................106 4.3.3.2 Time domain simulation.............................................................................107
4.4 Chip Design (Rev. 2) ......................................................................................................110 4.4.1 Circuit Implementation.........................................................................................111
4.4.1.1 Sample/hold circuit ....................................................................................111 4.4.1.2 Quadrature VCO (QVCO) .........................................................................112 4.4.1.3 Voltage-to-current (V/I) converter .............................................................114
4.4.2 Circuit Simulations...............................................................................................115 4.4.3 Layout...................................................................................................................119
4.5 Measurement (Rev.2) .....................................................................................................120 4.6 Summary.........................................................................................................................125
5 SUMMARY AND SUGGESTIONS FOR FUTURE WORK .............................................127
5.1 Summary.........................................................................................................................127 5.2 Four-fold Ambiguity Issue .............................................................................................130
LIST OF REFERENCES.............................................................................................................133
BIOGRAPHICAL SKETCH .......................................................................................................137
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LIST OF TABLES
Table page 2-1 Summary of components used in the measurement...........................................................48
4-1 Transceiver (Rev.2) performance summary ....................................................................124
5-1 Performance comparison of the different modulations....................................................129
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LIST OF FIGURES
Figure page 1-1 Characteristics of a PCB trace channel with various lengths. ...........................................16
1-2 Basic information of eye diagram......................................................................................16
1-3 Eye diagram of the 10Gbps signal at the far-end after tracing (a) 0.1” (b) 10” (c) 20” PCB channel.......................................................................................................................17
1-4 High data-rate transmission with (a) a conventional parallel bus (b) a serial link. ...........18
1-5 Pre-emphasis of NRZ signal and received signal with/without pre-emphasis. .................19
1-6 Frequency domain representation of the pre-emphasis technique of the transmitted signal. 20
1-7 Active inductor (a) realized with NMOS source follower (b) small signal equivalent circuit (c) simplified model................................................................................................21
1-8 Comparison of PAM-2 and PAM-4 signal spectrum.........................................................23
1-9 Basic digital modulation schemes (a) baseband data (b) ASK (c) FSK (d) PSK. .............24
1-10 Simplified spectrums of carrier modulation signals (a) using carrier signal higher than data-rate (b) using half-symbol-rate-carrier signal. ...................................................26
2-1 HSRC-BPSK modulation: baseband data sequences and modulated signal. ....................27
2-2 HSRC-QPSK and OQPSK (a) modulation scheme, (b) QPSK time domain waveforms, (c) OQPSK time domain waveforms. ............................................................29
2-3 HSRC-MSK (a) modulation scheme (b) time domain waveforms. ...................................30
2-4 Normalized power spectral density for HSRC modulations..............................................32
2-5 Modulated time domain signals of HSRC-OQPSK and its symbol energies. ...................33
2-6 Gaussian distribution of different energy symbols for HSRC-OQPSK modulation. ........36
2-7 Comparison of theoretical and simulated BER performance of HSRC modulations........37
2-8 The demodulated signal (a) demodulation process of I (or Q) channel (b) demodulated peak signal (Es,p) of the HSRC-OQPSK. .....................................................38
2-9 Comparison of the BER performance between the symbol time (matched filter) and the bit time integration of HSRC-OQPK signal. ...............................................................39
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2-10 Frequency response of the band-limited channel modeled with a one pole low-pass filter. ...................................................................................................................................40
2-11 Comparison of simulated BER performance of the PAM-2 (NRZ) and HSRC-OQPSK modulation with band-limited channel. ...............................................................41
2-12 DC-free modulation based on HSRC-OQPSK (a) modulation scheme (b) time-domain waveforms.............................................................................................................43
2-13 Comparison of the spectra between NRZ and the dc-free signals. ....................................44
2-14 A prototype HSRC-OQPSK transmitter and measurement setup......................................45
2-15 A 500MHz branch-line hybrid quadrature power splitter structure for HFSS simulation...........................................................................................................................46
2-16 Simulated and measured characteristics of the 500MHz branch-line hybrid quadrature power splitter (a) S-parameters (b) phases. .....................................................46
2-17 Measured characteristics of the HSRC-OQPSK modulation (equivalent 2Gbps random data input) (a) time domain waveform (b) spectrum. ...........................................49
2-18 Comparison of the theoretical and measured waveforms of HSRC-OQPSK modulation. ........................................................................................................................50
2-19 Comparison of the measured and theoretical spectrum of the HSRC-OQPSK signal. .....50
3-1 A simplified conventional transceiver for a serial data link. .............................................54
3-2 A conceptual HSRC-OQPSK transceiver architecture. .....................................................54
3-3 A HSRC-OQPSK transmitter architecture.........................................................................55
3-4 A structure of the DET F/F and data and clock synchronization by inserting (a) delay unit (b) a MUX as a delay unit...........................................................................................56
3-5 A fully differential (a) CML buffer and (b) differential input voltage versus output voltages. .............................................................................................................................58
3-6 Characteristics of a differential pairs versus differential input voltage (a) drain currents (b) transconductance. ...........................................................................................60
3-7 CML Circuits (a) D-latch (b) analog multiplexer (c) double-edge triggered flip-flop. .....61
3-8 A resistive load Gilbert mixer............................................................................................63
3-9 Two different delay control circuit (a) a current-starved inverter (b) a shunt capacitive inverter. .............................................................................................................64
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3-10 A fully differential (a) shunt capacitor inverter with cross-coupled PMOS active load and (b) two-stage ring oscillator. .......................................................................................65
3-11 Injection-locked LC QVCO...............................................................................................66
3-12 Combining I and Q channel signal by direct connecting outputs. .....................................67
3-13 Three stage output buffer with open drain output stage. ...................................................67
3-14 Output buffer (a) differential three-stage output buffer (b) doubly terminated structure..............................................................................................................................68
3-15 HSRC-OQPSK transceiver chip using TSMC 0.18μm CMOS technology. .....................69
3-16 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum........70
3-17 Transmitter die photo implemented by UMC 0.18μm CMOS technology. ......................71
3-18 Linearity simulation of resistive Gilbert mixer using UMC 0.18μm CMOS technology (a) conversion gain vs. LO power, (b) conversion gain vs. RF input frequency, (c) input referred 1dB compression. ................................................................73
3-19 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum........74
3-20 Simulated dc-free signaling (a) time domain waveforms (b) signal spectrum ..................75
3-20 Test board for the Rev. 1 HSRC-OQPSK transmitter (transceiver) implemented by TSMC 0.18μm CMOS Technology. ..................................................................................76
3-21 Measured spectrums and phase noise of the transmitter’s QVCO implemented by TSMC 0.18μm CMOS technology (center frequency of 2.5GHz with 5MHz span and 47 KHz RBW) (a) free-running mode (b) injection-locked mode (c) comparison of the phase noises between free-running and injection-locked modes. ................................77
3-22 Simplified test setups for (a) 2.5Gbps (5Gbps equivalent) (b) 10Gbps random input for the transmitter...............................................................................................................79
3-23 Eye-diagram of the HSRC-OQPSK transmitted signal implemented by TSMC 0.18μm CMOS technology. ...............................................................................................81
3-24 Test board for the Rev. 2 transmitter implemented by UMC 0.18μm CMOS technology..........................................................................................................................82
3-25 Measured spectrums and phase noise of the transmitter’s QVCO implemented by UMC 0.18μm CMOS technology (center frequency of 2.25GHz with 100MHz span and 910 KHz RBW) (a) free-running mode (b) injection-locked mode (c) comparison of the phase noises between the free-running and the injection-locked modes. ................83
3-26 Characteristics of channels used in the measurement........................................................85
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3-27 Eye-diagram of HSRC-OQPSK transmitted signal implemented by UMC 0.18μm CMOS technology after (a) 2” PCB trace, (b) 5” PCB trace, (c) 10” PCB trace, (d) 20” PCB trace, (e) 19” SATA cable, in response to 4.86Gbps (both I and Q channel input with 2.43Gbps pseudo random bit stream (PRBS) sequence of 231-1).....................86
3-28 Spectrum of 4.86Gbps dc-free signal.................................................................................88
3-29 Eye-diagram of the HSRC-OQPSK transmitted signal with 9.72Gbps PRBS sequence of (a) 27-1 (ideal eye-opening is depicted with blue line), (b) 231-1. .................89
3-30 Signal spectrum in response to9.72Gbps PRBS sequence of 27-1.....................................53
4-1 HSRC-QOPSK receiver (Rev. 1) architecture incorporated with quarter-rate PD............92
4-2 Quarter-rate phase detector (a) architecture (b) waveforms (for 40Gbps NRZ). ..............92
4-3 HSRC-OQPSK receiver architecture incorporated with a CDR........................................94
4-4 Polarity-type Costas loop for QPSK signal carrier recovery. ............................................95
4-5 A modified Costas loop for the HSRC-OQPSK signal clock and data recovery. .............97
4-6 Early and late sampling time of I/Q data. ........................................................................100
4-7 Averaged phase detector characteristic of the proposed CDR loop. ...............................101
4-8 Equivalent linear model of proposed CDR for HSRC-OQPSK. .....................................103
4-9 Open loop gain characteristics of the proposed CDR loop..............................................104
4-10 Phase error characteristic with SNR (S-curve) of the proposed CDR loop. ....................105
4-11 Phase error simulations of the CDR for the HSRC-OQPSK signal with MatLab Simulink behavioral models. ...........................................................................................106
4-12 Behavioral model simulation result of the phase error for the proposed CDR using MATLAB.........................................................................................................................107
4-13 HSRC-OQPSK Transceiver Model with QVCO for Time-Domain Simulation. ............108
4-14 Time-domain response of phase error signal for the VCO frequency control.................108
4-15 Time-domain response of phase error signal for the VCO frequency control with 10° I/Q mismatch....................................................................................................................109
4-16 Normalized settling time and peak-peak ripple voltage in locking state vs. I/Q mismatch. .........................................................................................................................110
4-17 A high-speed differential sample/hold (S/H) circuit........................................................111
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4-18 A ping-pong structure differential sample/hold circuit....................................................112
4-19 LC quadrature VCO (LC-QVCO). ..................................................................................113
4-20 Simulated QVCO’s tuning range and its gain..................................................................114
4-21 A differential to single-ended V/I converter. ...................................................................115
4-22 A detailed receiver architecture. ......................................................................................115
4-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm transmission line with characteristic impedance of 50Ω. ................................................116
4-24 Simulation of the locking behavior of the proposed CDR loop.......................................117
4-25 I/Q data of the transmitter and the receiver in the proper phase locked state. .................118
4-26 HSRC-OQPSK receiver chip fabricated with UMC 0.18μm CMOS technology. ..........119
4-27 Receiver test board...........................................................................................................120
4-28 Simplified receiver (transceiver) measurement setups (a) for 2.5Gbps input (equivalent data-rate of 5Gbps), (b) for 10Gbps data-rate...............................................121
4-29 Phase noise performance of the receiver’s VCO in free-running and locking states. .....122
4-30 Measured jitter of recovered clock in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1)................................................................123
4-30 Recovered I (or Q) channel eye-diagrams in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1). .................................................123
5-1 A differentially coded HSRC-OQPSK transceiver architecture to resolve the fourfold ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel data (b) alternative architecture without using a multiplexer. .........................................130
5-2 An example of a conceptual architecture for resolving four-fold ambiguity issue using eight bits SYNC field. ............................................................................................132
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
DESIGN OF MULTI-GIGABIT SERIAL LINK TRANSCEIVER USING BANDWIDTH-EFFICIENT HALF-SYMBOL-RATE-CARRIER OFFSET QUADRATURE PHASE SHIFT
KEYING MODULATION
By
Hyeopgoo Yeo
August 2007
Chair: Jenshan Lin Major: Electrical and Computer Engineering
My research introduces new quadrature phase-shift-keying (QPSK) modulation techniques
for high-speed data communication systems that use two orthogonal half-symbol-rate-carrier
(HSRC) signals by which channel bandwidth requirements are reduced compared to that of the
conventional non-return-to-zero (NRZ) modulation. The proposed HSRC offset-QPSK (HSRC-
OQPSK) improves spectral efficiency by reducing the side lobes of the signal spectrum. In
addition, HSRC minimum-shift keying (HSRC-MSK) modulation is also introduced. The
performances and the simulation results of the proposed modulation techniques are studied and
compared with those of the conventional ones.
Using the proposed HSRC-OQPSK modulation, a prototype transmitter generating the
HSRC-OQPSK signal was designed and built. Measurement results confirm the theory that the
proposed HSRC-OQPSK modulation improves spectral efficiency by reducing the second lobe
of the signal spectrum by 10dB. Furthermore, the HSRC-OQPSK modulation reduces the first
null bandwidth by 25% compared to the standard Non-Return-to-Zero (NRZ) modulation. Like
NRZ, HSRC-OQPSK uses a 2-level data decision which enables a simpler transceiver
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architecture than multi-level pulse amplitude modulations (PAM), such as 4-PAM and
duobinary.
My research also examines a modified Costas loop for the clock and data recovery (CDR)
involving HSRC-OQPSK modulation. Behavioral model simulation has verified analysis of the
proposed CDR. The carrier frequency of the HSRC-OQPSK signal is quarter data rate. Hence the
proposed CDR is comparable to quarter-rate CDR using quadrature-phase VCO (QVCO), which
relaxes the timing constraints and allows a simple structure as well.
The HSRC-OQPSK transceivers are implemented and simulated with TSMC and UMC
0.18μm CMOS technology to prove the theoretical performance. The theory and the
measurement results show that it is feasible to increase the data-rate in wire-line communications
using low-cost channels.
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CHAPTER 1 INTRODUCTION
1.1 Motivations
These days, a demand for high data rate transmission through low cost band-limited
channels (e.g., copper trace on FR4 PWBs and CAT-5 cables) is increasing. Data transmission
with binary format, (represented by non-return-to-zero (NRZ) format) to receive data looks very
simple and clear. However, it is a real challenge to high data rate communications over the band-
limited channel because of impaired signal loss, reflections, and crosstalk. Although parallel I/O
data transmission is efficient for short length data communications, it suffers from a large data
skew and jitter for the aforementioned reasons. Obviously, those problems will be more severe as
data rates and channel lengths increase. The high speed point-to-point link, a serial link, can
overcome these kinds of bottlenecks. It offers high data transmission, up to multi-gigabit data
transmission, over a long PCB trace, and a cable line. The transmitted signal bandwidth for the
point-to-point links increases directly proportional to the data rate. Since a low cost channel,
such as a PCB trace (e.g., copper cable), has low-pass characteristics, the high frequency loss of
the transmitted data is unavoidable, as shown in Figure 1-1. This frequency dependent low-pass
characteristic largely comes from the skin effect of the material as well as dielectric loss of the
material. Figure 1-1 also shows the frequency characteristics of the FR4 PCB with various
lengths. 10 GHz signal attenuated about 20dB in 50Ω characteristic impedance of 20” length
with a tangential loss of 0.023. Besides board trace, a board attachment, a connector, and IC
package make parasitics. Unfortunately, these cause nonlinear effects such as reflection,
resonance, and ripple.
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2 4 6 8 10 12 140 16
-25
-20
-15
-10
-5
-30
0
freq, GHz
dB(S
(2,1
))5"
10"
20"
15"
Figure 1-1 Characteristics of a PCB trace channel with various lengths.
The non-return-to-zero (NRZ) signal, which is the same as PAM-2, is commonly used for
digital systems including high speed serial links. The NRZ signal, defined as binary data, can be
very simple because the signal has 2-levels and is easily implemented by digital circuits. An eye
diagram is usually used to estimate signal quality. The signal is chopped into equal periods and
accumulated onto one plot. The eye diagram gives visual information regarding signal usefulness
in data communication systems [1].
Zero-crossing jitter
Unit Interval
SNR at the sampling point
ISI
Ideal sampling point
Figure 1-2 Basic information of eye diagram.
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Figure 1-3 shows an example of the eye diagrams for various trace lengths. The 10Gbps
random binary data is applied to the input port and the output signal is monitored. The eye
diagram has no jitter components and its opening is very clear with 0.1” channel trace. However,
as the PCB trace increases, distortion and jitter components are introduced to the signal and the
eye opening is almost closed after 20” trace, as shown in Fig. 1-3(a).
0.1"
0 20 40 60 80 100 120 140 160 180 200-20 220
0.0
0.2
0.4
0.6
0.8
1.0
-0.2
1.2
time, psec
0 20 40 60 80 100 120 140 160 180 200-20 220
0.0
0.2
0.4
0.6
0.8
1.0
-0.2
1.2
time, psec
10"
0 20 40 60 80 100 120 140 160 180 200-20 220
0.0
0.2
0.4
0.6
0.8
1.0
-0.2
1.2
time, psec
20"
(a) (b) (c)
Figure 1-3 Eye diagram of the 10Gbps signal at the far-end after tracing (a) 0.1” (b) 10” (c) 20” PCB channel.
Conventional parallel buses are used for short range data links such as system buses
between CPU and the main memory to increase the data-rate. However, there are several crucial
limitations to increase data-rate to infinity. First, in high-speed parallel buses, signal jitter and
data skew occur due to the crosstalk between signals, which causes a synchronization problem
between the signal lines at the receiver-end. The synchronization mismatch prevents the
appropriate data transmission between the transmitter and the receiver even though a precise
clock signal is used for the data fetch. Figure 1-4 shows the example of data skew between the
signal lines and the misaligned data arrival at the receiver-end, which causes the wrong data
transfer. Moreover, the skew problem is getting more severe as the clock frequency goes high [2].
Instead of using parallel buses, point-to-point communication called a serial link is used to
resolve the skew problem. This communication uses a low-swing signal instead of a
conventional large swing signal with the terminations which prevent the signal reflection. The
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low-swing signaling can also reduce the power dissipation. However, to convert the parallel-bit
data into a serial data, the clock frequency should be increased by the parallel bit times for
maintaining the data-rate. However, this method can resolve the data skew between the data in
parallel bits, hence, the synchronization problem can be fixed even if the jitter is introduced to
the signal. Of course, the duration of the data fetch timing is reduced due to the jitter in the signal.
Figure 1-4(b) shows the example of the serial link.
Tx RxParallel Bus
Serial Link
Crosstalk, Jitter, Skew
(Backplane PCB, USB, Ethernet, Optical link)ex) USB2 : 480Mb/s
(a)
(b)
Tx RxParallel Bus
Serial Link
Crosstalk, Jitter, Skew
(Backplane PCB, USB, Ethernet, Optical link)ex) USB2 : 480Mb/s
(a)
(b)
Figure 1-4 High data-rate transmission with (a) a conventional parallel bus (b) a serial link.
Since a serial link uses a very high frequency clock compared to a parallel bus system, the
signal quality gets more influenced from the limitation of the data bandwidth due to the loss of
high frequency energy in the band-limited channel which has normally a low-pass characteristic
as investigated before. Therefore, it remains a challenging problem in the high-speed serial link
communications as to how to compensate the high-frequency energy of the signal and recover
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the transmitted data at the receiver, including clock and data recovery (CDR) using the
transmitted signal.
1.2 Compensation Techniques of High Frequency Signal
1.2.1 Pre-Emphasis Signal
There are two primary approaches to improving high speed data link limitation over the
low-cost channel. First is a direct compensation of the signal’s high frequency component during
transmission and reception. Pre-emphasis of the PAM-4 transmitted signal with an equalizer
implemented by a multi-tap finite impulse response (FIR) filter has been demonstrated in [3-4].
The equalization distorts the transmitted signal by giving the signal high frequency energy,
hence, the signal arriving at the receiver-end has more power compared to the non pre-emphasis
signal, which are shown in Figure 1-5. However, it is still challenging to implement the equalizer
in the GHz range with CMOS technology [5].
Pre-emphasis Signal
Received Signal
Received Signal without pre-emphasis
Figure 1-5 Pre-emphasis of NRZ signal and received signal with/without pre-emphasis.
Figure 1-6 depicts the pre-emphasis in the frequency domain. The band-limited channel is
characterized as a low-pass characteristic as discussed in the previous section. The FIR filter for
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the pre-emphasis of the signal should have a high-pass characteristic to compensate the energy of
high-frequency signal which will be attenuated more than the lower frequency signal energy.
However, this technique is very challenging in GHz range with CMOS technology as well as
requires high speed sampling DAC, ADC for the PAM-4 signal, which increase the system
complexities [3-4].
+Channel
Equalizing
Received Signal
Transmitted Signal
+Channel
Equalizing
Received Signal
Transmitted Signal
Figure 1-6 Frequency domain representation of the pre-emphasis technique of the transmitted signal.
1.2.2 Broadband Circuit Technique
Besides the direct compensation of high frequency components, broadband circuit
techniques to broaden the limitation of the operation frequency of the circuit, such as an inductor
peaking, capacitive degeneration, a Cherry-Hooper limiting amplifier, and a fT doubling, can be
classified as compensation techniques of the high frequency signal [6].
Inductive peaking is one of the broadband techniques widely used to increase the
bandwidth of the amplifier. However, a passive inductor integrated in chip occupies a large chip
area. An active inductor implemented by an active device such as a MOS can be used to save the
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chip area. Detailed active inductor analysis is presented in [6]. Figure 1-7 shows the active
inductor implemented with a PMOS device and its equivalent models.
M1
VDD
RS
Zout
R1R2 Zout
LRS
CGS
IXVX
+-
+- V1
Figure 1-7 Active inductor (a) realized with NMOS source follower (b) small signal equivalent circuit (c) simplified model [6].
The small-signal equivalent circuit is obtained as (1-1), (1-2), and the impedance of the output
node is derived as (1-3).
jωCGSV1 + gmV1 = -IX (1-1)
jωCGSV1RS + V1 = -VX (1-2)
GSm
SGSout Cjg
RCjZ
ωω+
+=
1 (1-3)
Note that if RS >> 1/gm, absolute value of the Zout is increasing with frequency, which behaves
like an inductor and is modeled as depicted in Figure 5-1(c) where R1= RS – 1/gm, R2 = 1/gm.
Then the value of the inductor, L is obtained as (1-4).
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
mS
m
GS
gR
gC
L 1 (1-4)
To get a high quality (Q) factor of the active inductor, we must maximize R1 and minimize
R2. Since the Q of the parallel combination of R1 and L is represented by R1/ωL and R1/L =
gm/CGS, Rs does not affect the Q factor significantly. However, the active inductor mainly
suffers from its voltage headroom for the operation. To relieve voltage headroom, a modified
22
active inductor with NMOS has been developed; however, the achievable bandwidth of the
circuit is limited compared to those using a passive inductor.
Other broadband techniques such as a capacitive degeneration, a Cherry-Hooper limiting
amplifier, are studied well in [6].
1.3 Modulation Techniques
1.3.1 Conventional Modulation Techniques
Pulse amplitude modulation (PAM) -strictly baseband PAM- signal is most often used in
high-speed data communications, such as a serial link communication because it is easy to define
its level of “1” or “0” and implement with a simple digital circuit. However, it needs a relatively
large bandwidth requirement for the data transmission. For high-speed serial link over the band-
limited channel, it is important to reduce the bandwidth requirement of the transmitted signal
because the channel has low-pass characteristics, as discussed in the previous section. Multi-
PAM (e.g. 4-PAM) which reduces signal bandwidth requirement has been introduced and
demonstrated to increase the data-rate [3]. Duobinary, which is characterized as a 3-level PAM,
has also been introduced [7]. However, in these multi-PAMs, it is difficult to maintain the linear
spacing between levels in low-voltage and low-power application and as a result the system’s
performances are degraded. The level spacing also causes complexity in the transceiver design
not only because the received signal needs to be linearly amplified but also because the multi-
PAM signal requires accurate reference voltages.
Second is a modulation technique that reduces the transmitted bandwidth signal, such as
multi-level pulse-amplitude modulation (PAM). Four-level PAM (known as PAM-4) signaling
for serial links using CMOS technology has been proposed and demonstrated over the band-
limited channels [3], [8]. Obviously, the PAM-4 data rate is double that of a non-return-to-zero
(NRZ) with the same bandwidth signal because the former uses four-levels instead of two-levels.
23
Figure 1-8 shows the signal spectrums of baseband PAM-2 and PAM-4. The PAM-4 signal
occupies exactly half of the bandwidth of PAM-2 signal. However, the multi-level signal reduces
the signal energy hence degrading the BER performance. Moreover, electrical limitations of the
system such as low supply voltage resulting from device scaling make the system design more
difficult. For example, the level spacing of the PAM-M signal is inversely proportional to (M-1).
Therefore the level is much smaller in low voltage systems, which are vulnerable to noise and
also require a more precise ADC for the reliable communications. Recently, duobinary signaling,
a 3-level PAM, for the backplane serial link has been introduced and demonstrated for serial
links applications [9]. The duobinary signal has only three signal levels which offer higher signal
energy than the PAM-4 signal within the same voltage system.
0 0.5 1 1.5 2 2.5 3-60
-50
-40
-30
-20
-10
0
10
f/BR (Hz/bit/s)
Nor
mal
ized
Pow
er S
pect
ral D
ensi
ty (d
B)
PAM-2PAM-4
Figure 1-8 Comparison of PAM-2 and PAM-4 signal spectrum.
24
1.3.2 Modulation Technique Using Half-Symbol-Rate-Carrier (HSRC)
On the other hand, a carrier modulation such as a phase-shit-keying (PSK) modulation is
difficult to be used in the serial link data communications because the carrier signal makes
baseband data to the passband signal. Figure 1-9 shows basic digital modulation schemes using
carrier signals. Digital modulation is using an analog carrier signal to modulate the binary digital
sequences. The basic digital modulation schemes are depicted in Figure 1-5. Amplitude-shift-
keying (ASK) is the modulation technique that mixes the baseband binary data with a carrier
signal. The carrier signal is generated when the data is high, otherwise the amplitude of the
carrier goes zero. Frequency-shift-keying (FSK) modulation has two different frequency carrier
signals representing one or zero data. Baseband data is used for the information of the frequency
to be generated from the carrier signal generator which will be usually implemented by a voltage
controlled oscillator (VCO). Phase-shift-keying modulation uses one carrier frequency signal
different from the FSK. The phase of the carrier signal is changed as the baseband data changes.
1 0 0 1
(a)
(b)
(c)
(d)
1 0 0 1
(a)
(b)
(c)
(d)
Figure 1-9 Basic digital modulation schemes (a) baseband data (b) ASK (c) FSK (d) PSK.
25
1.3.2.1 Why Not Carrier Modulation?
These carrier modulation techniques shift the spectrum of the baseband data to the carrier
frequency, as shown in Figure 1-10(a). Usually the carrier frequency is much higher than the
baseband data-rate. Applied to the baseband data communications, the carrier modulation shifts
the baseband data information to the carrier frequency so that the required bandwidth to transfer
the baseband information would be increased as shown in Figure 1-10(a). Consequently, it is
inevitable to waste the required bandwidth of the channel with this carrier modulation.
What happens in the PSK signal if the carrier signal is sub-symbol-rate? Figure 1-10(b)
shows the spectrum where a half-symbol-rate carrier is used as a carrier modulation signal. Both
main lobes of spectrums at positive and negative frequency are overlapped. The modulated
signal is characterized as a passband signal due to the carrier modulation; however, the spectrum
of the signal looks like that of a baseband signal, as depicted in Figure 1-10(b). This signal
would be called the pseudo-baseband signal. Quadrature modulation using two orthogonal carrier
signals can be defined. With this quadrature modulation – quadrature PSK (QPSK) - technique,
the bandwidth requirement of the baseband data can be reduced by half compared to the PSK
modulation using a single carrier signal [10]. What if the quadrature modulation uses the HSRC
signal? As mentioned earlier, the spectrums are overlapped as shown in Figure 1-10(b) so that
the modulation reduces the first-null bandwidth of the spectrum by 25% than that of non-return-
zero (NRZ) modulation.
My research mainly focuses on a signal modulation technique to reduce the bandwidth of
the transmitted signal. Modulations based on PSK are proposed and analyzed. The conventional
PSK type modulations are well-studied in [10-11]. The proposed high speed data links signal
modulation techniques modulating digital data with a half-symbol-rate carrier using phase-shift
keying (named as HSRC-PSK).
26
fc-fc
Signal Bandwidth
Required Bandwidth
fc=1/4Tb
Signal Bandwidth
Required Bandwidth
-fc=-1/4Tb
(a) (b)
Figure 1-10 Simplified spectrums of carrier modulation signals (a) using carrier signal higher than data-rate (b) using half-symbol-rate-carrier signal.
Like binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) used in
wireless systems using radio frequency (RF) carriers, this HSRC-PSK modulation technique can
be extended to quadrature type modulations using two orthogonal carrier signals, such as QPSK,
offset-QPSK (OQPSK), minimum shift keying (MSK) modulations popularly used in wireless
communications. These quadrature type PSK modulations can increase the data rate with nearly
equal signal energy [9]. The proposed half-symbol-rate carrier modulation technique is similar to
conventional modulation techniques. However, their properties are not identical and the analysis
is given in this report. Effectively, the half-symbol-rate-carrier modulation performs waveform
shaping on the data bits when transmitted through band-limited channels. The signal spectrums
of proposed modulations are derived in analytical form and their bit error rate performances are
simulated. The results are compared to conventional modulations.
The HSRC-OQPSK signaling is especially chosen as a possible modulation candidate for
high speed serial links, implemented and simulated by TSMC and UMC 0.18um CMOS
technology.
27
CHAPTER 2 HSRC PHASE SHIFT KEYING (PSK) MODULATIONS
2.1 Binary Modulation
A binary PSK (BPSK) signal whose sinusoidal carrier amplitude is Ac can be represented
by (2-1) where m(t) is the binary data signal, Tb is the bit period, fc, is the frequency of carrier,
and θc is the phase of the carrier [12].
( ) bccc TttfAtmts ≤≤+⋅= 02cos)()( θπ (2-1)
Let us now consider a special case where fc=1/2Tb (Nyquist bandwidth) and θc=-π/2. With
this condition, the BPSK signal can be represented by (2-2).
bb
c TttT
Atmts ≤≤⎟⎟⎠
⎞⎜⎜⎝
⎛⋅= 0sin)()( π
(2-2)
Since the carrier signal frequency is within the baseband, this modulation is similar to
signal waveform shaping rather than modulation. The baseband data are mixed with a carrier
whose frequency is the same as one half of the symbol rate, fc=1/2Ts, where Ts is the symbol
period, and Ts=Tb in BPSK. Figure 2-1 shows the concept of half-symbol-rate-carrier BPSK
(HSRC-BPSK) modulation.
-1
1m(t)
1 1s(t)
11 -1 1
sin(π/Tb)t
-1
1m(t)
1 1-1
1m(t)
1 1s(t)
11 -1 1
s(t)1
1 -1 1
sin(π/Tb)t
Figure 2-1 HSRC-BPSK modulation: baseband data sequences and modulated signal.
28
2.2 Quadrature Modulations
2.2.1 HSRC Quadrature PSK (QPSK) Modulation
HSRC-QPSK modulation is similar to a conventional QPSK modulation. The conventional
QPSK signal can be represented in (2-3), where mI and mQ are the data sequences in their in-
phase (I) and the quadrature-phase (Q) components, respectively, and fc is the carrier frequency
which is generally larger than the symbol rate.
tftmtftmts cQcI ππ 2sin)(2
12cos)(2
1)( ⋅+⋅= (2-3)
However, for multi-Gb/s data communications (i.e. backplane serial link), it is often
unpractical to generate a carrier frequency higher than the symbol rate. To address this issue, the
HSRC-QPSK modulation is proposed, as shown in Figure 2-2(a). The HSRC-QPSK signal is
obtained by substituting QPSK’s carrier frequency, as fc=1/(4Tb), where Tb is the bit-period,
which is the half-symbol-rate-carrier frequency, as shown in (2-4).
tT
tmtT
tmtsb
Qb
I ⎟⎟⎠
⎞⎜⎜⎝
⎛⋅+⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅=
2sin)(
21
2cos)(
21)( ππ (2-4)
Since the carrier frequency is lower than the data-rate, the phase of the carrier signal can
affect the modulated signal’s properties. Therefore, the phase of the carrier signal is fixed to
define this modulation. The theoretical time domain HSRC-QPSK waveforms are shown in
Figure 2-2(b).
2.2.2 HSRC Offset QPSK (OQPSK) Modulation
The HSRC-OQPSK shares the same architecture as HSRC-QPSK shown in Fig. 2-2(a). Its
signal is obtained by staggering (offsetting) I and Q by Tb, as shown in Figure 2-2(c). The
HSRC-OQPSK signal can also be defined by (2-3) but using offset sequences of mI and mQ [13].
29
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
(a)
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
m (t)m1
m2
m3 m4
m5 m8
m6 m7
0 2Tb 4Tb 6Tb 8Tb
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
( )tTb2cos2
1 π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin2
1 π
(a)
s I( t)
0 2 T b 4 T b 6 T b 8 T b
s I( t)
0 2 T b 4 T b 6 T b 8 T b
s Q ( t)
0 2 T b 4 T b 6 T b 8 T b
s Q ( t)
0 2 T b 4 T b 6 T b 8 T b
s ( t)
0 2 T b 4 T b 6 T b 8 T b
s ( t)
0 2 T b 4 T b 6 T b 8 T b
(b) (c)
m5
m7mI(t) m3
0 2Tb 4Tb 6Tb 8Tb
m1
Tb 9Tb3Tb 5Tb 7Tb
mQ(t)
m2
m4 m6
m8
ssI(t)
0 2Tb 4Tb 6Tb 8Tb
sQ(t)
Tb 9Tb3Tb 5Tb 7Tb
m5
m
0 2Tb 4Tb 6Tb 8Tb
mI(t) m1 m3 m7
mQ(t)
m2
m4 m6
m8
0 2Tb 4Tb 6Tb 8Tb
s ( t)s ( t)
Tb 9Tb3Tb 5Tb 7Tb
s I( t)
0 2 T b 4 T b 6 T b 8 T b
s I( t)
0 2 T b 4 T b 6 T b 8 T b
s Q ( t)
0 2 T b 4 T b 6 T b 8 T b
s Q ( t)
0 2 T b 4 T b 6 T b 8 T b
s ( t)
0 2 T b 4 T b 6 T b 8 T b
s ( t)
0 2 T b 4 T b 6 T b 8 T b
(b) (c)
m5
m7mI(t) m3
0 2Tb 4Tb 6Tb 8Tb
m1
m5
m7mI(t) m3
0 2Tb 4Tb 6Tb 8Tb
m1
Tb 9Tb3Tb 5Tb 7Tb
mQ(t)
m2
m4 m6
m8
Tb 9Tb3Tb 5Tb 7Tb
mQ(t)
m2
m4 m6
m8
ssI(t)
0 2Tb 4Tb 6Tb 8Tb
ssI(t)
0 2Tb 4Tb 6Tb 8Tb
sQ(t)
Tb 9Tb3Tb 5Tb 7Tb
sQ(t)
Tb 9Tb3Tb 5Tb 7Tb
m5
m
0 2Tb 4Tb 6Tb 8Tb
mI(t) m1 m3 m7
m5
m
0 2Tb 4Tb 6Tb 8Tb
mI(t) m1 m3 m7
mQ(t)
m2
m4 m6
m8
0 2Tb 4Tb 6Tb 8Tb
mQ(t)
m2
m4 m6
m8
0 2Tb 4Tb 6Tb 8Tb
s ( t)s ( t)
Tb 9Tb3Tb 5Tb 7Tb
s ( t)s ( t)
Tb 9Tb3Tb 5Tb 7Tb
Figure 2-2 HSRC-QPSK and OQPSK (a) modulation scheme, (b) QPSK time domain waveforms, (c) OQPSK time domain waveforms.
This is the same as the direct combination of conventional MSK’s I/Q channels without the
mixing of the carrier frequency. As shown in Figure 2-2(c), the combined signal is free from any
discrete transitions. If the in-phase signal is at its peak of either positive or negative value, the
quadrature-phase signal is zero at every 2Tb. On the other hand, if the quadrature-phase signal is
at its peak of either positive or negative value, the in-phase signal is zero at every 2Tb. Therefore,
the combined signal has no discrete transitions.
30
2.2.3 HSRC Minimum Shift Keying (MSK) Modulation
The HSRC-MSK modulation can be obtained by applying the HSRC signal to the
conventional MSK modulation format as described in (2-5) and shown in Fig. 2-3(a). As shown
in Fig. 2-3(b), the data sequences of I/Q channels are the same as those of the OQPSK as well as
the proposed HSRC-OQPSK. The resulting HSRC-MSK time domain data sequences are the
same as the original data sequences.
tT
tmtT
tmtsb
Qb
I ⎟⎟⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛=
2sin)(
2cos)()( 22 ππ (2-5)
sI(t)
0 2Tb 4Tb 6Tb 8Tb
sQ(t)
Tb 3Tb 5Tb 7Tb 9Tb
s(t)
Tb 3Tb 5Tb 7Tb 9Tb
m4
m6mI(t) m0 m2
0 2Tb 4Tb 6Tb 8Tb
mQ(t)
m1
m3 m5
m7
Tb 3Tb 5Tb 7Tb 9Tb
( )tTb2cos π
( )tTb2sin π
( )tTb2cos π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin π
m (t)m0
m1
m2 m3
m4 m7
m5 m6
0 2Tb 4Tb 6Tb 8Tb
(a)
(b)
sI(t)
0 2Tb 4Tb 6Tb 8Tb
sI(t)
0 2Tb 4Tb 6Tb 8Tb
sQ(t)
Tb 3Tb 5Tb 7Tb 9Tb
sQ(t)
Tb 3Tb 5Tb 7Tb 9Tb
s(t)
Tb 3Tb 5Tb 7Tb 9Tb
s(t)
Tb 3Tb 5Tb 7Tb 9Tb
m4
m6mI(t) m0 m2
0 2Tb 4Tb 6Tb 8Tb
m4
m6mI(t) m0 m2
0 2Tb 4Tb 6Tb 8Tb
mQ(t)
m1
m3 m5
m7
Tb 3Tb 5Tb 7Tb 9Tb
mQ(t)
m1
m3 m5
m7
Tb 3Tb 5Tb 7Tb 9Tb
( )tTb2cos π
( )tTb2sin π
( )tTb2cos π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin π
( )tTb2cos π
( )tTb2sin π
( )tTb2cos π
mI(t)
mQ(t)
Serial to
Parallel
s(t)
sI(t)
sQ(t)
m(t)
( )tTb2sin π
m (t)m0
m1
m2 m3
m4 m7
m5 m6
0 2Tb 4Tb 6Tb 8Tb
m (t)m0
m1
m2 m3
m4 m7
m5 m6
0 2Tb 4Tb 6Tb 8Tb
(a)
(b)
Figure 2-3 HSRC-MSK (a) modulation scheme (b) time domain waveforms.
31
The modulated signal described in (2-5) has the same data sequences to those of the
original binary data which is shown in Figure 2-3(a). This is similar to raised-cosine
approximation (RCA) signaling [14].
2.3 Signal Spectrum
Since the frequency of the carrier signal is lower than the data-rate, the carrier signal can
be effectively considered as a spectral pulse-shaping. The spectral pulse-shaping function of the
proposed modulations is derived as shown in (2-6) by applying the similar approach described in
[10]. Note that the pulse-shaping function of HSRC-QPSK and HSRC-OQPSK are different,
although the pulse-shaping functions of the conventional QPSK and OQPSK are the same.
( )
⎪⎪⎪⎪
⎭
⎪⎪⎪⎪
⎬
⎫
⎪⎪⎪⎪
⎩
⎪⎪⎪⎪
⎨
⎧
<<⎟⎟⎠
⎞⎜⎜⎝
⎛
<<⎟⎟⎠
⎞⎜⎜⎝
⎛
<<⎟⎟⎠
⎞⎜⎜⎝
⎛+
=
elsewhere
TtTt
TtTt
TtTt
tg
bb
bb
bb
;0
MSK-HSRCfor 20;2
sin
OQPSK-HSRCfor 20;2
sin
QPSK-HSRCfor 20;42
sin
2 π
π
ππ
(2-6)
The normalized power spectral densities, S(f), are derived by the Fourier transforms of (2-
6), S(f)=|G(f)|2/T, where G(f) is the Fourier transform of any given g(t) [10]. Using this equation
and combining with trigonometric identities of sin(x)=(ejx-e-jx)/2j, cos(x)=(ejx+e-jx)/2, the final
forms of S(f) can be equated as (2-7). Their plots are shown in Figure 2-4.
( )
( )
( ) ⎪⎪⎪⎪
⎭
⎪⎪⎪⎪
⎬
⎫
⎪⎪⎪⎪
⎩
⎪⎪⎪⎪
⎨
⎧
⎟⎟⎠
⎞⎜⎜⎝
⎛
−
⎟⎟⎠
⎞⎜⎜⎝
⎛
−
⎟⎟⎠
⎞⎜⎜⎝
⎛
−+
=
MSK-HSRC;412
2sin
OQPSK-HSRC;161
2cos16
QPSK-HSRC;161
2cos1618
2
22
2
222
222
22
bb
bb
b
bb
b
bbb
TffTfTT
TffTT
TffTTfT
fS
ππ
ππ
ππ
(2-7)
32
0 0.5 1 1.5 2 2.5 3-60
-50
-40
-30
-20
-10
0
10
f/BR (Hz/bit/s)
Nor
mal
ized
Pow
er S
pect
ral D
ensi
ty (d
B)
NRZ (PAM-2)HSRC-MSKHSRC-QPSKHSRC-OQPSK(MSK)
Figure 2-4 Normalized power spectral density for HSRC modulations.
The first null point of the HSRC-QPSK and HSRC-OQPSK spectrum are located at
0.75Tb. Therefore, their first-null bandwidths are reduced by 25% compared to the first-null
bandwidth of the conventional NRZ, alternatively known as baseband binary pulse-amplitude-
modulation (PAM-2). However, the first-null bandwidth of the HSRC-MSK is the same as that of
the conventional NRZ.
For the side lobes, HSRC-OQPSK shares the same pulse-shaping with the conventional
MSK. Therefore, the HSRC-OQPSK power spectral density should also be identical to that of
MSK, which is presented in [11]. Also, they fall off more rapidly (1/f4) than those of the
conventional NRZ (1/f-2) [11]. The side lobes of the HSRC-MSK fall off even more rapidly (1/f6)
and therefore the high frequency components can be further suppressed [14].
33
Recent semiconductor technologies scaled down the transistor size, which results in the
reduction of supply voltage. In low voltage circuits, PAM-4 modulation, that requires linear
amplification, is more difficult to maintain the same spacing between levels. The HSRC-OQPSK
is expected to have advantages over this because it does not need to space levels. Especially, for
the amplifiers to be operating at power saturation, MSK has superior performance to QPSK [13].
For bandwidth efficiency, the spectrum of HSRC-OQPSK, which is the same as MSK, contains
99% of the total signal power within the bandwidth, B≈(1.2/Tb), while for QPSK and PAM-4, the
99% bandwidth increase to B≈(8/Tb) [13], [15]. Therefore, it is expected that the HSRC-OQPSK
should have the effective signal spectrum in band-limited channel, such as backplane serial link.
2.4 Bit Error Rate (BER) Performance
The BER performances are characterized using a coherent demodulation with a matched
filter in Additive-White-Gaussian-Noise (AWGN) channel for the proposed HSRC modulations
are simulated via MATLAB. The HSRC-QPSK signal has only one symbol energy, Es.
Therefore, it is expected to follow the same BER performance of the conventional QPSK, as
shown in Figure 2-7.
s(t)Es,t Es,t
Es,t Es,tEs,f Es,p
Es,p Es,f
s(t)Es,t Es,t
Es,t Es,tEs,f Es,p
Es,p Es,f
Figure 2-5 Modulated time domain signals of HSRC-OQPSK and its symbol energies.
For the HSRC-OQPSK, the BER performance result is different from that of the
conventional OQPSK, due to the existence of three different symbol energies – namely, Es,t, Es,f,
34
Es,p. For the case where the quadrature symbols are evenly transmitted, an example of s(t)
illustrating the three different energies is described in Figure 2-5.
The upper sequences are for the I channel while the lower sequences are for the Q channel.
The different three symbol energies can be calculated by integrating the square of the modulated
signal (∫|s(t)|2dt) over a 2 bit-time (2Tb), as shown in (2-8)~(2-10). Es,t is the symbol energy for
the case where only one of the 2 bits transits between its high and low points. This symbol
energy is the same as that of the conventional QPSK, Es. Es,f is for the case where both 2 bits
remain in its high or low points (remains flat). Finally, Es,p is when the signal peaks by
consecutive transitions. Note that the final terms in (2-9), (2-10), Es,f, Es,p are expressed in scalar-
multiples of Es,t by kf, kp, respectively.
dtTtAE bT
bcts
22
0
2, 42
sin ∫ ⎟⎟⎠
⎞⎜⎜⎝
⎛+=ππ (2-8)
⎟⎠⎞
⎜⎝⎛ +
≡=⎟⎟⎠
⎞⎜⎜⎝
⎛+⋅= ∫ π
πππ 2 ; 42
sin2 ,
2
0
2, ftsf
T
bcfs kEkdt
TtAE b (2-9)
⎟⎠⎞
⎜⎝⎛ −
≡⋅=⎟⎟⎠
⎞⎜⎜⎝
⎛+⋅= ∫ π
πππ 2 ; 42
sin2 ,
222
, ptsp
T
Tb
cps kEkdtTtAE b
b
(2-10)
The average probability of errors of s(t) can be calculated using (2-10), where M is the
number of different types of symbols [10], [12]. As was the case in Figure 2-5, this equation
assumes that M symbols are evenly transmitted, where si represents one of M possible symbols
of the modulation signal.
( ) ( ) ( ) ( )∑=
==M
iieiiee sP
MsPsPP
1
|1| εεε (2-11)
35
If we define noise energy to be N, the BER can be expressed in terms of energy-per-
symbol (or bit) to the noise-density ratio of the three energies, as shown in (2-12)~(2-14). Note
that in the final terms of (2-13) and (2-14), the noises are scaled to an effective values, so that the
signal energies can be considered as a function of Es,t.
NE
NE sts =, (2-12)
f
tstsffs
kNE
NEk
NE
/,,, =
⋅= (2-13)
p
tstspps
kNE
NEk
NE
/,,, =
⋅= (2-14)
In the AWGN channel, the noise N, has a Gaussian distribution with the mean being 0 and
the variance being ½No. Hence, the scaled effective noises of N/kf and N/kp also have Gaussian
distributions where the means are 0 and variances are ½No/kf2 and ½No/kp
2, respectively. With
these parameters, the probability of errors for each symbol can be obtained by integrating the
Gaussian distribution functions over the error decision section as shown in Figure 2-6. Therefore,
the BER of HSRC-OQPSK in AWGN channel can be derived as (2-15), where Eb=Es/2 and
( ) ( )∫∞
−=x
dxxxQ 2/exp21 2
π.
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛ −
⋅+⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛ +
⋅+⎟⎟⎠
⎞⎜⎜⎝
⎛⋅=
000
224122
412
21
NE
QNE
QNE
QP bbbe π
ππ
π (2-15)
The 1/2 weight in the first term and the 1/4 in the second and last terms account for the fact
that Es,t occurs twice as often as Es,f or Es,p, in an evenly transmitted quadrature symbols. As
shown in Figure 2-7, (2-15) fits well with the results obtained from MATLAB.
36
Nominal EnergyLow EnergyHigh Energy
sEsE−
0
22
21
2N⎟
⎠⎞
⎜⎝⎛−
=ππσ
0
22
21
2N⎟
⎠⎞
⎜⎝⎛+
=ππσ
02
21 N=σ
( ) ( ) ⎟⎠⎞⎜
⎝⎛ −= 22
2exp2
1 σπσ sExxf
Es,t/N
Es,p/NEs,f/N
Figure 2-6 Gaussian distribution of different energy symbols for HSRC-OQPSK modulation.
The HSRC-MSK also has different BER from that of the conventional MSK, due to its
existence of two different symbol energies – namely, Es,t,m, Es,f,m. The analysis approach is the
same as that of the HSRC-OQPSK’s case and the results symbol energies and the BER of HSRC-
OQPSK are shown in (2-16), (2-17), and (2-18), respectively.
bc
T
bbcmts TAdt
Tt
TtAE b 2
22
0
222,, 2
cos2
sin =⎟⎟⎠
⎞⎜⎜⎝
⎛−⎟⎟
⎠
⎞⎜⎜⎝
⎛= ∫
ππ (2-16)
bc
T
bbcmfs TAdt
Tt
TtAE b 2
22
0
222,, 2
2cos
2sin =⎟⎟
⎠
⎞⎜⎜⎝
⎛+⎟⎟
⎠
⎞⎜⎜⎝
⎛= ∫
ππ . (2-17)
⎟⎟⎠
⎞⎜⎜⎝
⎛⋅+⎟
⎟⎠
⎞⎜⎜⎝
⎛⋅=
00
232
212
34
21
NE
QNE
QP bbe (2-18)
The analytical results are compared with those obtained from the MATLAB simulation as
shown in Figure 2-7. From the results, we observe that the HSRC-QPSK modulation has no
degradation of BER performance as compared to the conventional QPSK, which has almost the
37
same BER performance as that of the NRZ modulation. Therefore, HSRC-QPSK can be used as
a modulation technique for high-speed broadband communications with less bandwidth
requirement while keeping similar BER performance of NRZ. On the other hand, the HSRC-
OQPSK and HSRC-MSK modulations have less BER performances but having even more
efficient signal spectrum characteristics as described in the previous section.
0 5 10 15 2010-6
10-5
10-4
10-3
10-2
10-1
100
Eb/N0 (dB)
BE
R
Theoretical QPSKTheoretical HSRC-MSKTheoretical HSRC-OQPSKSimulated HSRC-QPSKSimulated HSRC-MSKSimulated HSRC-OQPSK
Figure 2-7 Comparison of theoretical and simulated BER performance of HSRC modulations.
The BER performances of the proposed HSRC PSKs’ are calculated by demodulation with
the matched filer. Generally, the demodulation with a matched filter enables the system to have
the best performance. However, a different result is obtained in the HSRC-OQPSK modulation.
Figure 2-8 shows demodulation process of I (or Q) channel at the HSRC-OQPSK receiver which
is presented in Chapter 4 in detail and the demodulated peak signal of the HSRC-OQPSK, which
has a low symbol energy, Es,p. The carrier signals are mixed with the incoming signals, as shown
in Figure 2-8. The demodulated signals at the first half bit time and the last half bit time periods
38
have negative values while the signal at the middle bit time period is positive. Therefore, the
integration of the demodulated HSRC-OQPSK signal over the period of 2Tb is less than that over
the period of Tb, as shown in Figure 2-8.
+
- -Bit Period (Tb)
Symbol Period (2Tb)
(a)
(b)
Carrier Signal
Input Signal
Figure 2-8 The demodulated signal (a) demodulation process of I (or Q) channel (b)
demodulated peak signal (Es,p) of the HSRC-OQPSK.
Since a matched filter is not used in the actual realization of the receiver (the level decision
is made by a clocked flip-flop (FF)) which is discussed in Chapter 4, the integrated value of the
demodulated signal over the period of Tb produce more realistic BER performance. The signal
energy is calculated as (2-19).
21 ;
2sin
42cos22 '
,'
2
2', ≡⋅=⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅⎟⎟
⎠
⎞⎜⎜⎝
⎛+⋅= ∫ ptsp
TT
bbcps kEkdt
Tt
TtAE b
b
πππ (2-19)
Since the BER performance of the HSRC-OQPSK modulation is mainly determined by
third term of (2-15), the BER performance with the symbol energies of (2-19) can be represented
as (2-20) approximately.
39
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎠⎞
⎜⎝⎛⋅≈
0
221
41
NE
QP be (2-20)
Figure 2-9 shows the theoretical BER performance using symbol energies of (2-19) and
simulated BER performance. From the simulation results, the difference of the BER
performances between the theoretical PAM-2 (NRZ) and the HSRC-OQPSK is approximately
4dB instead of 8dB (shown in Figure 2-7). The difference between the theoretical and simulated
BER performance is caused the noise amount integrated during the bit time period is, Tb, is
different from the total noise introduced in the AWGN channel. Although, the absolute values of
the BER performance using an AWGN channel would be different from that using a band-
limited channel, the difference of the BER performance is comparable to those in the band-
limited channel.
0 5 10 15 2010-6
10-5
10-4
10-3
10-2
10-1
100
Eb/N0 (dB)
BE
R
Theoretical PAM-2 (NRZ)Theoretical HSRC-OQPSK (Tb time integration)Theoretical HSRC-OQPSK (2Tb time integration)Simulated HSRC-OQPSK (Tb time integration)
Figure 2-9 Comparison of the BER performance between the symbol time (matched filter) and
the bit time integration of HSRC-OQPK signal.
40
To estimate the BER performance in the band-limited channel, a simple low-pass filter
having one pole, which is characterizing a band-limited channel, is added to the channel. The
transfer function is (2-21) and Figure 2-10 shows the frequency response of (2-21). The
characterized channel is comparable to the band-limited channel which has the loss of
0.75dB/GHz approximately.
10
10
103103)(⋅+
⋅=
ssH (2-21)
0 2 4 6 8 10 12 14 16-12
-10
-8
-6
-4
-2
0
Frequency (GHz)
H(s
) (dB
)
Figure 2-10 Frequency response of the band-limited channel modeled with a one pole low-pass
filter.
Figure 2-11 shows the simulated results of the 10Gbps system. Approximately, 5dB more
signal power is needed with the band-limited channel modeled as (2-21) to get the same BER
performance, which is caused energy loss of the transmitted signal in the band-limited channel
modeled as (2-21). From the frequency response depicted in Figure 2-10, 5GHz signals which is
comparable to 10Gbps data rate are losing their energy of 4dB by the band-limited channel.
41
However, the difference (4dB) of the signal to noise ratio per bit (Eb/N0) between the NRZ and
the HSRC-OQPSK is almost the same as the simulation result without the band-limited channel.
If the signal power is enough compared to noise introduced in the channel, the energy loss of the
signal in the band-limited channel mainly determines the BER performance of the system.
0 5 10 15 2010-5
10-4
10-3
10-2
10-1
100
Eb/N0 (dB)
BE
R
Simulated PAM-2 (NRZ)Simulated HSRC-OQPSK
Figure 2-11 Comparison of simulated BER performance of the PAM-2 (NRZ) and HSRC-
OQPSK modulation with band-limited channel.
2.5 DC-Free Signaling Based on HSRC-OQPSK Modulation
The ac coupled interconnect gives several advantages over the dc coupled interconnect.
First, the ac coupled channel would provide more flexible interconnection between the various
signal standards [16]. Second, the ac coupled interconnect allows high density and low-power
chip-to-chip communication. Recently, an ac coupled interconnect (ACCI) for the chip-to-chip
communication has been introduced and its performance demonstrated [17]. It enables low
power properties as well as high density I/Os. Moreover, an on-chip capacitor formed under pad
42
blocks the dc levels of the signal line which allows communication between the chips using a
different voltage level. However, capacitive coupling interconnect suffers from the “zero
wander” effect [16]. The capacitive coupling characterized as a high pass filter tends to cut off
the dc or low frequency information. However, it is very difficult to compensate the loss of the
signal where an ac coupled interconnect is used in a long line channel, such as a high-speed
serial links because both low and high frequency signal information should be compensated due
to the high frequency signal loss in the channel being characterized as a low pass filter.
Therefore, a modulation technique that removes the dc or low frequency component seems to be
more effective in this long line channel communication to relieve this “zero wander” problem
effectively.
This section investigates a modulation technique that removes the dc component in the
signal, which is relied on half-symbol-rate-carrier offset QPSK (HSRC-OQPSK) modulation.
The proposed dc-free signaling can not only remove the dc and low frequency components but
also maintain the (first-null) bandwidth of non-return-to-zero (NRZ) signal which is use in data
communication of the most conventional digital systems. In telecommunications, the transmitted
data are often encoded with 8B/10B [18] that converts 8-bit symbols to 10-bit symbols for proper
dc balance to guarantee clock and data recovery (CDR) operation at the receiver. This encoding
scheme will increase the transmitted data bandwidth by 20%. However, the 8B/10B encoding
might not be necessary for this modulation because the modulated signal includes the carrier
signal and no dc components. Consequently, this dc-free signaling will decrease the required
bandwidth by 20% effectively. As analyzed in section 2.4, approximately 4dB more signal to
noise ratio per bit is required to get the same BER performance of the NRZ modulation.
43
Decreasing data-rate by half, TB=2Tb, with maintaining data offset of Tb of (2-4), we can
get another modulation which can be characterized as a half bit time, TB/2, offset QPSK using a
quadrature symbol-rate-carrier (HRC) signal. The signal can be obtained as (2-22) simply by
substituting 2Tb=TB of (2-4). Figure 2-12 shows the modulation scheme and its time domain
waveforms.
tT
tmtT
tmtsB
QB
I ⎟⎟⎠
⎞⎜⎜⎝
⎛⋅+⎟⎟
⎠
⎞⎜⎜⎝
⎛⋅=
ππ sin)(2
1cos)(2
1)( (2-22)
(a)
(b)
0
mI(t)
2TB 4TB 6TB 8TB
m1 m3m5
m7
0.5TB(=Tb) 2.5TB 6.5TB4.5TB 8.5TB
mQ(t)
m2
m4 m6m8
sI(t)
0 2TB 4TB 6TB 8TB0
0.5TB 2.5TB 4.5TB 6.5TB
sQ(t)
8.5TB
s(t)
0.5TB 2.5TB 4.5Tb 6.5Tb 8.5Tb
00 2TB
m(t)m1
m2
m3 m4
m5
m6 m7
m8
Serial to
Parallel
1 ( )tTBcos2
π2
mI(t)
mQ(t) sQ(t)
sI(t)
s(t)
4TB 6TB 8TB
T( )tsin21 π2
B
(a)
(b)
0
mI(t)
2TB 4TB 6TB 8TB
m1 m3m5
m7
0
mI(t)
2TB 4TB 6TB 8TB
m1 m3m5
m7
0.5TB(=Tb) 2.5TB 6.5TB4.5TB 8.5TB
mQ(t)
m2
m4 m6m8
0.5TB(=Tb) 2.5TB 6.5TB4.5TB 8.5TB
mQ(t)
m2
m4 m6m8
sI(t)
0 2TB 4TB 6TB 8TB0
sI(t)
0 2TB 4TB 6TB 8TB0
0.5TB 2.5TB 4.5TB 6.5TB
sQ(t)
8.5TB0.5TB 2.5TB 4.5TB 6.5TB
sQ(t)
8.5TB
s(t)
0.5TB 2.5TB 4.5Tb 6.5Tb 8.5Tb
s(t)
0.5TB 2.5TB 4.5Tb 6.5Tb 8.5Tb
00 2TB
m(t)m1
m2
m3 m4
m5
m6 m7
m8
Serial to
Parallel
1 ( )tTBcos2
π2
mI(t)
mQ(t) sQ(t)
sI(t)
s(t)
4TB 6TB 8TB
T( )tsin21 π2
B
00 2TB
m(t)m1
m2
m3 m4
m5
m6 m7
m8
Serial to
Parallel
1 ( )tTBcos2
π21 ( )tTBcos2
π2
mI(t)
mQ(t) sQ(t)
sI(t)
s(t)
4TB 6TB 8TB
T( )tsin21 π2
BT( )tsin21 π2
B
Figure 2-12 DC-free modulation based on HSRC-OQPSK (a) modulation scheme (b) time-
domain waveforms.
Unlike conventional OQPSK modulation, data offset of the dc-free modulation using SRC
signal is half bit time not 1-bit time as shown in Figure 2-10. As shown in Fig 1(b), there are no
discrete transitions in the signal like HSRC-OQPSK, from which we can expect the side lobes of
44
the signal spectrum to be suppressed like those of MSK. The pulse shaping function of the signal
can be represented as (2-23).
( )⎪⎩
⎪⎨
⎧<<⎟⎟
⎠
⎞⎜⎜⎝
⎛=
elsewhere
TtT
ttg B
B
0
20sin π (2-23)
The normalized power spectral density, S(f), is derived by the Fourier transform of (2-23),
S(f)=|G(f)|2/T, where G(f) is the Fourier transform of g(t). The resulting power spectral density is
represented as (2-24).
( )2
222 412sin4
⎟⎟⎠
⎞⎜⎜⎝
⎛
−=
B
BB
TffTTfS π
π (2-24)
Figure 2-13 shows the theoretical spectrums of NRZ and dc-free signals. The first null
point of the spectrum of the dc-free signal is located at fB=1/TB, which is the same as that of the
conventional NRZ.
0 0.5 1 1.5 2 2.5 3-60
-50
-40
-30
-20
-10
0
10
f/BR (Hz/bit/s)
Nor
mal
ized
Pow
er S
pect
ral D
ensi
ty (d
B)
NRZdc-free
Figure 2-13 Comparison of the spectra between NRZ and the dc-free signals.
45
The carrier signal moves the dc information of the data to the other frequency range
without increasing bandwidth of the signal transmitted. Moreover, the side lobes of the dc-free
modulation fall off more rapidly (1/f4) than conventional NRZ (1/f-2).
2.5 Measurement of the HSRC-OQPSK Signal
A prototype HSRC-OQPSK transmitter was built and tested because the HSRC-OQPSK is
the most feasible modulation to be implemented for high-speed wire-line data communications,
such as a backplane serial link. The block diagram of the transmitter with test setup is shown in
Figure 2-14.
CK
I Data
I/Q Modulator
Spectrum Analyzer
Bit Pattern Generator
500MHz ClockSignal Generator
90o
90° Power Splitter
180° Power Splitter
180° Power Splitter
180o
180o
Oscilloscope
Branch Line
5MHz Pulse Function Generator
Power Combiner
Q Data
M1
M2
M3
External Clock In
1GHz Clock
1Gbps Data
Frequency Doubling
Figure 2-14 A prototype HSRC-OQPSK transmitter and measurement setup.
Two wide-band mixers, with a bandwidth of 50~4200MHz, are used as I/Q channel
mixers. A 500MHz quadrature branch-line hybrid power splitter which is constructed with PCB
is used to generate quadrature carrier signals. Figure 2-15 shows the structure of the branch-line
hybrid power splitter. The port2 and port3 received the signal power split equally from port1
with a phase offset of 90°. Of course, the symmetrical S-parameter characteristic can be observed
46
due to the symmetric structure. The characteristics of S-parameters are simulated with Ansoft
HFSS and compared to the measured data in terms of their magnitude and phase information, as
shown in Figure 2-16. The splitter can be integrated into a single chip using the passive elements
approach [19].
Figure 2-15 A 500MHz branch-line hybrid quadrature power splitter structure for HFSS simulation.
200 300 400 500 600 700 800-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Frequency (MHz)
Mag
nitu
de (d
B)
S12
S13
S23
Simulated S12 Simulated S13 Simulated S23 Measured S12 Measured S13 Measured S23
(a)
Figure 2-16 Simulated and measured characteristics of the 500MHz branch-line hybrid quadrature power splitter (a) S-parameters (b) phases.
47
200 300 400 500 600 700 8000
30
60
90
120
150
Frequency (MHz)
Pha
se D
iffer
ence
(deg
ree)
SimulatedMeasured
(b)
Figure 2-16 (continued).
The two quadrature output signals are split again by using 180° power splitters. The 0°
signals of the 180° power splitters are used for the quadrature carriers while the 180° signals are
fed into the mixer M3 to generate a 1GHz clock signal for the digital bit pattern generator’s
external clock. The bit pattern generator generates 1Gbps pseudo random data for the
transmitter’s I channel. The HSRC-OQPSK modulation requires a serial-to-parallel conversion
with 1-bit time offset. To simplify the test, a 5MHz pulse is injected into the Q channel input to
represent fixed-pattern data bits. Time delay from the bit pattern generator is adjusted to
synchronize the I channel data and the carrier signal. Consequently, the overall transmitter data
rate is equivalent to 2Gbps.
Agilent N4906A 3.6Gbps serial Bit Error Rate Tester (BERT) is used to generate 1Gbps
pseudo random data. Agilent 54832D 4Gsa/s oscilloscope and Agilent E4448A spectrum
analyzer are used to monitor the time domain waveforms and output signal spectrum,
respectively. Table I summarizes the components used in the measurement.
48
Table 2-1 Summary of components used in the measurement.
Device Function Model Frequency Range
Mixer (M1, M2) I/Q channel mixer Mini-Circuits ZX05-42MH-S 5 ~ 4200MHz
Mixer (M3) Frequency Doubler Mini-Circuits ZX05-30W 300 ~ 4000MHz
90° Power Splitter Dividing I/Q channel carrier Quadrature Hybrid (Branch Line) 500MHz
180° Power Splitter Frequency double Mini-Circuits ZFSCJ-2-4 50 ~ 1000MHz
Power Combiner/Divider I/Q channel signal combine Agilent 11636A DC ~ 18GHz
Signal Generator 500MHz carrier source Agilent E8254A 250KHz ~ 40GHz
Function Generator 5MHz pulse for Q channel Agilent 33120A 15MHz
BERT 1Gbps I channel data Agilent N4906A 3.6Gbps Serial BERT
Oscilloscope Monitoring time domain waveform Agilent 548320 1GHz / 4Gsa/s
Spectrum Analyzer Monitoring signal spectrum Agilent E4448A 3Hz ~ 50GHz
Figure 2-17 shows the measured HSRC-OQPSK time domain waveform and its spectrum.
Since the HSRC-OQPSK signal follows the MSK signal spectrum, the first null point of the
spectrum must be located at 1.5GHz because the equivalent data rate is 2Gbps. Time domain
waveform is also well-matched with the theoretical waveform shown in Figure 2-2(c).
Both time domain waveforms and frequency domain spectrum were measured and
compared to the theoretical predictions. Figure 2-18 shows the measured HSRC-OQPSK time
domain waveform and the theoretical prediction.
For comparison purposes, a fixed pattern of sequences ‘110’ was used for the data pattern
instead of random bit patterns. Therefore, the data sequence of the I channel is
‘110110110……’. Measured waveform matches well with the theoretical waveform as shown in
49
Figure 2-12. A phase mismatch between the data and the carrier signal caused the difference in
waveform.
100mV/div
2ns/div
100mV/div
2ns/div
(a)
(b)
Figure 2-17 Measured characteristics of the HSRC-OQPSK modulation (equivalent 2Gbps random data input) (a) time domain waveform (b) spectrum.
Random data sequences were fed into the I channel to measure the signal spectrum. As
shown in Figure 2-19, the measured broadband spectrum matches very well with the theoretical
spectrum of a 2Gbps random bit stream. The spectrum’s first null is located at 1.5GHz which is
50
the same as the theoretical value. Other null points match the theoretical predictions as well. The
difference between the measured spectrum’s main lobe and second lobe is approximately 23dB,
which agrees with the theoretical value.
10 15 20 25 30 35-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
Time (ns)
Am
plitu
de (V
)
Theoretical WaveformMeasured Waveform
Figure 2-18 Comparison of the theoretical and measured waveforms of HSRC-OQPSK
modulation.
0 1 2 3 4 5-90
-80
-70
-60
-50
-40
-30
-20
-10
Frequency (GHz)
Pow
er S
pect
ral D
ensi
ty (d
Bm
)
Theoretical Spectrum
23dB
Figure 2-19 Comparison of the measured and theoretical spectrum of the HSRC-OQPSK signal.
51
2.6 Summary
The HSRC-PSK modulations are proposed to optimize spectral efficiency for high data-
rate transmission over band-limited channels. The analysis and simulation results show that the
proposed modulations can be used in high-speed data communications, such as a backplane
serial link.
In the past, a multi-PAM signal (e.g., PAM-4) has been demonstrated to increase the data-
rate in band-limited channels [3]. However, in PAM-4 modulation, it is difficult to maintain the
linear spacing between levels in low-voltage and low-power application and as a result the
system’s performances are degraded. The level spacing also causes complexity in the transceiver
design not only because the received signal needs to be linearly amplified but also because PAM-
4 signaling requires accurate reference voltages.
The proposed HSRC modulations not only reduced the bandwidth requirement but also can
be easily implemented in deep submicron integrated circuit technologies with low supply
voltages. The proposed HSRC-QPSK signal has irregular timing transitions and therefore a new
phase detector design for clock and data recovery (CDR) and a matched filter for the
demodulation are required. On the other hand, since such irregular transition does not exist in
HSRC-OQPSK, the HSRC-OQPSK signaling can be used effectively in band-limited wire-line
applications with maximum spectral efficiency. This modulation might be able to optimize the
spectral efficiency for baseband high data rate transmission over band-limited channels.
Compared to the conventional NRZ modulation, the proposed modulation greatly reduces the
bandwidth requirements. For bandwidth efficiency, the HSRC-OQPSK spectrum, which is the
same as the MSK spectrum, contains 99% of the total signal power within the bandwidth of B ≈
(1.2/Tb). In comparison, PAM-4 has much larger 99% bandwidth of B ≈ (8/Tb) [13], [15].
Therefore, it is expected that the proposed HSRC-OQPSK modulation should have an efficient
52
signal spectrum in band-limited channels. And this spectrum efficiency will reduce the high
frequency crosstalk noise between the signal lines which may improve the performance of the
multi-port serial communication links. In addition, dc-free signaling based on the HSRC-OQPSK
modulation has been introduced. The dc-free signaling is expected to have good performance in
ac coupled channel applications including a flip-chip ACCI.
Measurement results verified that the HSRC-OQPSK modulation can be effectively used
in band-limited wire-line applications requiring spectral efficiency, such as the backplane serial
link. Moreover, because it requires only a two-level decision, the HSRC-OQPSK transmitter can
be implemented in a simpler architecture than PAM-4 and is suitable for low-voltage systems. In
addition, a QPSK carrier recovery structure can be used for the HSRC-OQPSK modulation
which enables flexible design of the receiver, which will be discussed in Chapter 4.
For the HSRC-MSK modulation, it can greatly minimize crosstalk noise compared to the
conventional ones, since the high frequency components are further suppressed [14].
53
CHAPTER 3 HSRC-OQPSK TRANSMITTER
3.1 Transceiver Architecture
3.1.1 A Conventional Serial Link Transceiver Architecture
Prior to the HSRC-OQPSK transmitter detail, the conventional transceiver and a
conceptual HSRC-OQPSK transceiver need to be investigated. Conventional quadrature
modulation transceiver architectures are investigated in [20-21]. Figure 3-1 shows the simplified
transceiver structure of a conventional serial link. The transmitter has a serializer which converts
the parallel data into serial data using a clock generated from a phase-locked loop (PLL). An
output buffer amplifies the converted serial data for driving a channel. The receiver has a clock
and data recovery (CDR) circuit that includes a phase and frequency detector (PFD). Besides a
CDR, the receiver includes a retimer, and a deserializer. Passing through the channel, the
transmitted signal is amplified with a limiting amplifier allowing the signal to travel through a
CDR. In the CDR circuit, the incoming signal restores a clock used as the clock of the decision
circuit. After the decision, the data may convert to parallel data by a deserializer. Typically, a
reference clock for precise frequency detection is also used to avoid false locking conditions,
which is not depicted in Figure 3-1.
3.1.2 A Conceptual HSRC-OQPSK Transceiver Architecture
Figure 3-2 shows a conceptual HSRC-OQPSK transceiver structure. The signal modulation
uses two mixers and one combiner circuit while two mixers, matched filters and decision circuits
are used for demodulation. This system architecture is basically the same as conventional QPSK
modulation and demodulation system. The quarter-rate clock and data recovery (CDR) is
incorporated with the HSRC-OQPSK receiver because the frequency of the carrier signal is half-
symbol-rate which is comparable to the quarter-data-rate of the system.
54
n
Transmitter
LimiterJittered
DataPLL CDR
F/Fn
Receiver
Phase Detector
Low-Pass Filter VCO
Data CK
Serializer Deserializer
Channeln
Transmitter
LimiterJittered
DataPLL CDR
F/Fn
Receiver
Phase Detector
Low-Pass Filter VCOVCO
Data CK
Serializer Deserializer
Channel
Figure 3-1 A simplified conventional transceiver for a serial data link.
Though a matched filter for the QPSK signal demodulation improves system performance,
it is hard to implement the matched filter operating at giga-hertz frequency range. So, the
matched filter should be replaced by other circuits which allow the high-speed operation. A high-
speed flip-flop (F/F), and appropriate retiming circuit for the incoming data can replace the
matched filter. The detailed transmitter architecture is discussed in this chapter and the detail
receiver architecture is presented in Chapter 4.
Serial to
Parallel
I
Q
LO
90°
T
Q
LO
90°
T
In
Out
Transmitter
Receiver
I dt
dt
Parallelto
Serial
Quarter-Rate CDR
Quarter-Rate CDR
RxOut
TxIn
Channel
Channel
Linear Amplifier
Serial to
Parallel
I
Q
LO
90°
T
I
Q
LO
90°90°
TT
Q
LO
90°90°
TT
In
Out
Transmitter
Receiver
I dtdt
dtdt
Parallelto
Serial
Quarter-Rate CDR
Quarter-Rate CDR
RxOut
TxIn
Channel
Channel
Linear Amplifier
Figure 3-2 A conceptual HSRC-OQPSK transceiver architecture.
55
3.2 HSRC-OQPSK Transmitter Architecture
Figure 3-3 shows the simplified HSRC-OQPSK transmitter architecture which is basically
the same as the conventional OQPSK modulation system architecture. The received data are
separated into the I and Q channels with 1 bit-time offset by a serial-to-parallel logic which is
comprised of two double-edge-triggered (DET) F/Fs, as shown in Figure 3-3. The separated data
are mixed with the quadrature HSRC signals of each channel and then combined by wiring
outputs of the I/Q mixers for generating the modulated signal, as shown in Fig. 2. For the bit
error rate (BER) test purposes, the HSRC signal is generated by an injection-locked LC voltage
controlled oscillator (VCO) whose injection clock is also used in the clock of the external 2:1
multiplexer (serializer) of the receiver, which will be discussed in Chapter 4.
Data In
Injection-Locked VCO
90o
I Channel
Q Channel
DET F/F
Delay
Delay
Transmitted Signal Out
DET F/F
Injection Clock
Serial to Parallel with 1-bit offset
Figure 3-3 A HSRC-OQPSK transmitter architecture.
In this transmitter architecture, the phase synchronization of the clock and data is crucial to
produce an undistorted modulation signal. To maximize the modulated signal spectrum
bandwidth efficiency, the data should be synchronized with the carrier signal of each channel.
Synchronization mismatch caused from the clock to data output delay of the DET F/F should be
cancelled out by inserting a delay component between the VCO outputs and the mixer inputs, as
shown in Figure 3-4(a). Most of the circuits in this transmitter design have been implemented
with current mode logic (CML) circuits which are discussed in section 3.2.1 in more detail. CML
56
circuits offer low delay variation due to its supply independent low-swing voltage characteristic
[22]. From the simulation results, the delay variation is less than 10% of the various supply
voltages and processes. Synchronized delay lines or RC delay circuits could be reasonable
solutions, as shown in Figure 3-4(a). However, a delay line for several tens of pico-seconds is a
long line to be integrated and makes severe signal attenuation. Rev.1 transmitter implemented
TSMC 0.18μm CMOS technology uses a RC delay circuit for the synchronization. However,
delay mismatch might occur because the flip-flop delay is not fixed over the various voltage,
temperature, and process conditions during the operation. In general, a buffer as a delay unit can
be an effective solution for the compensation of the delay mismatch problem [6]. Rev. 2
transmitter using UMC 0.18μm CMOS technology employs a buffer as a delay unit. Since a
delay of the DET F/F is mainly determined by a MUX, a matching delay buffer can be
implemented by inserting the same MUX to the signal path, as shown in Figure 3-4(b). The
MUX input ports are tied together and the selection port is logically fixed to select one of the two
inputs. Consequently, equal delays can be inserted in the signal paths.
F/F
Clock (Sinusoidal)
I/Q Data
Delayed Data
Delay
F/F
Clock (Sinusoidal)
I/Q Data
Delayed Data
Delay
(a)
Figure 3-4 A structure of the DET F/F and data and clock synchronization by inserting (a) delay unit (b) a MUX as a delay unit.
57
D
Clock (sinusoidal)
DET F/F
Q
Logical 0 or 1
I/Q Channel Signal
MUX
F/F
F/F
MUX
(b) Figure 3-4 (continued).
3.2 Circuit Implementation
3.2.1 Current-mode-logic (CML) Circuit
A fully differential CML type circuit is widely used for the lower signal voltage and
high-speed digital system. As discussed and analyzed in [22], the CML logic has several
advantages over conventional digital logic. The logic has supply voltage independent output
swing. The differential pair with low input and output voltage swing offers high-speed operation.
Figure 3-5 shows a CML buffer circuit and its characteristic of output voltage versus input
voltage. The detailed analysis of the basic differential pair with resistive loads is presented in
[23]. The maximum output voltage swing is determined by tail current ISS and load resistance
RD, which varies VDD to VDD-RDISS as the differential input varies -∞ to ∞, as shown in Figure 3-
4. The NMOS logic parts are pulled up with load resistors.
The minimum and maximum input common mode level which allows M1, M2 to stay in
the saturation region is analyzed in (3-1) [23].
58
Vin1 Vin2
Vout2Vout1
ISS
RD RD
P
VDD
(a)
VDD Vout1 Vout2
VDD-RDISS
RDISS
Vin1 – Vin2
(b)
Figure 3-5 A fully differential (a) CML buffer and (b) differential input voltage versus output voltages.
( ) ⎥⎦
⎤⎢⎣
⎡ +−≤≤++ DDTHSS
DDDCMinGSGSGS VVI
RVVVVV ,2
min,331 (3-1)
We have Vout1=VDD-RDID1 and Vout2=VDD-RDID2 and Vout1-Vout2=RD(ID2-ID1). Since the virtual
ground node, P, is equal to Vin1-VGS1 and Vin2 – VGS2, we get equation (3-2).
Vin1 – Vin2 = VGS1 – VGS2 (3-2)
59
The relationship between VGS and ID is represented as (3-3) for a square-law device, where
μn is the mobility of the NMOS device, Cox is the gate oxide capacitance, W is the device width,
and L is the device length.
( )
LWC
IVVoxn
DTHGS
μ21
2 =− (3-3)
Using (3-3), (3-2) can be represented as (3-4).
LWC
I
LWC
IVV
oxn
D
oxn
Dinin
μμ
2121
22−=− (3-4)
Squaring two sides of (3-4) with the constraints of ID1 + ID2 = ISS, we get (3-5).
( ) ( )212
21 22DDSS
oxn
inin III
LWC
VV −=−μ
(3-5)
Squaring the two sides again and then, we finally get the equation which represents the
relationship between the output current difference, (ID1 – ID2), and the input voltage difference,
(Vin1 – Vin2), given in (3-6).
( ) ( )2212121
421
inin
oxn
ssininoxnDD VV
LWC
IVV
LWCII −−−=−
μμ (3-6)
By differentiating the two sides of (3-6), transconductance, Gm, is obtained as (3-7) where ΔVin =
(Vin1 – Vin2).
2
2
4
24
21
inoxn
SS
inoxn
SS
oxnin
Dm
VLWC
I
VLWC
I
LWC
VI
GΔ−
Δ−=
Δ∂Δ∂
=
μ
μμ (3-7)
60
Equation (3-7) implies that Gm drops to zero for ( )LWCIV oxnSSin μ2=Δ . What if ΔVin
exceeds the value which makes Gm to be zero? In this case, one transistor drives the total tail
current, ISS, input because the other transistor is approaching the turn-off mode. Thus, ID1 = ISS
and ΔVin1 = VGS1 - VTH where ( )LWCIV oxnSSin μ21 =Δ and M2 is turned off for ΔVin > ΔVin1.
Figure 3-6 shows the relationship between the ID and ΔVin and the characteristic of Gm.
+ΔVin1
Gm
-ΔVin1 ΔVin
(a) (b)
Figure 3-6 Characteristics of a differential pairs versus differential input voltage (a) drain currents (b) transconductance [19].
As analyzed so far, the differential pair shown in Figure 3-4(a) can be used for a small
signal amplifier whose maximum differential input voltage is ∆Vin1. Within ∆Vin1, the differential
amplifier could have a high small gain which is dependant on RD and ISS. In case of using it as a
digital logic which is called CML, it is better to guarantee ∆Vin > ∆Vin1 for the maximum signal
output. Typically, the value of ∆Vin1 does not exceed several-hundred mV for the high-speed
operation. Therefore, the differential CML logic uses a smaller input signal than a conventional
logic. Since the differential structure cancels the even mode harmonic terms, it is obvious that
the differential CML buffer is more linear than conventional CMOS logic and not easily affected
by common mode noise, which becomes more important in the low-voltage systems. The
differential structure gives us a one-stage buffer while the conventional CMOS needs a two-
61
stage, greatly reducing the delay of the buffer. Moreover, the characteristics of the CML logic
are strongly related to the tail current ISS and use a smaller logic signal. Delay variation due to
voltage, temperature, and process could be very small compared to conventional CMOS logic.
3.2.2 CML Double-Edge Triggered D flip-flop
A CML is widely used in high-speed digital logic because its low-swing voltage enables
high-speed operation [22], [24]. For this reason, most of the circuits used in this transceiver
design are CML circuits.
A CML DET F/F consists of a CML latch and a CML-style analog MUX, as shown in
Figure 3-7(a). The basic structure of the CML DET F/F is the same as a conventional one. Two
latches are selected by an analog multiplexer with a clock signal, shown in Figure 3-5(c). Due to
its high-speed and low delay variation characteristics, the CML latch offers good system
performance. Input transistors sense and track the input data differentially and cross-coupled
transistors store that data [24]. The clock signal selects tracking modes and storing modes. The
input transistors are tracking the input signal when the clock is high and cross-coupled transistors
are storing the input data when the clock signal is low.
CLK-CLK+
Vout+Vout-
Vin+
Vin-
RD RD
ISS
sel-sel+
Vout+Vout-
Vin1+
Vin1-
Vin2-
RD RD
ISS
Vin2+
(a) (b)
Figure 3-7 CML Circuits (a) D-latch (b) analog multiplexer (c) double-edge triggered flip-flop.
62
MUX
D Q
D QData
CLK
Out
(c)
Figure 3-7 (continued).
The MUX also can be implemented with CML style digital logic which offers a more
flexible interface with CML latches than a conventional full-swing high-speed logic as well as
high-speed operation. The clock signal of the MUX selects one of the latches which stores the
previous data, so that the DET F/F can transfer the data when both the rising-edge and the
falling-edge clock signals occur.
3.2.3 Resistive Load Gilbert Mixer
One major difference between the conventional serial link transmitter and the HSRC-
OQPSK transmitter is mixing the data with the carrier signal using an analog mixer shown in
Figure 3-3. I and Q channel mixers generate an analog signal instead of a digital signal like NRZ.
Since the data input encompasses wide-band signals up to several GHz, a wide band mixer
should be used in this system. A resistive load Gilbert mixer has been chosen for this system
because it has wide bandwidth operation. It offers a direct output-to-input interface without any
voltage level shifting because it has basically the same structure as a CML circuit. Moreover, I
and Q channel signal combining can be obtained by connecting the outputs of the mixer in the
channels, which is discussed in section 3.2.2.5. The load resistor, RD uses the value of 2.5KΩ for
both Rev. 1 and Rev.2 transmitter. Figure 3-8 shows a resistive load Gilbert mixer.
63
Vin1-Vin1+
Vout+Vout-
Vin2+
Vin2-
Vin2+
RD RD
ISS
Figure 3-8 A resistive load Gilbert mixer.
3.2.4 Quadrature Phase Clock Generator
Quadrature-phase carrier signals whose frequency is half-symbol-rate are needed for the
modulation. This can be simply implemented by using a two stage differential ring oscillator as
shown in Figure 3-9(b). To control the delay of each stage to varying the clock frequency, there
are two ways of controlling the propagation delay. One is the current starved approach and the
other is the shunt capacitive approach [25]. Figure 3-8 shows the current-starved and the shunt
capacitive inverter. In the current-starved inverter, Vctl controls the resistance of M4 through
current mirroring. This variable resistance controls the charging and discharging timing. In the
shunt capacitor inverter, control voltage, Vctl, adjust the resistance of M3 which is connected to
the output of the inverter. The other output of M3 is connected to a load capacitor. Therefore, the
shunt resistance of M3 controls the effective load capacitance seen by the output node of the
inverter. Decreasing the resistance of M3, the effective load capacitance seen by the output node
becomes large, producing more delay. From [25], the shunt capacitance topology has better
64
linear and noise rejection characteristics than the current-starved topology. However, the shunt
capacitance topology occupies a larger area due to the lumped capacitor.
Vctl
Vin
M1
M2
M3
M4
Vout
M1
Vctl
Vin VoutM2
M3
(a) (b)
Figure 3-9 Two different delay control circuit (a) a current-starved inverter (b) a shunt capacitive inverter.
Figure 3-10 shows fully differential a shunt capacitive type inverter and two stage ring
oscillator. It is common that the fully differential circuit has better power supply insensitivity.
Each differential inverter has cross-coupled PMOS load and shunt capacitor with a control
NMOS. The phase difference of this adjacent node is 90°.
It is known that LC oscillators allow large output swing at higher frequency with lower
voltage and make less phase noise than ring oscillators described in this section do [6]. For these
reasons an LC VCO, especially, an injection-locked quadrature-phase LC QVCO has been
chosen in this work. For the bit-error-rate (BER) test, the HSRC-OQPSK receiver needs an
external 2:1 mux for serializing I and Q channel data, which will be discussed in detail in
Chapter 4. To synchronize both the transmitter and the receiver outputs for the BER test, the
injected clock signal can also be used as an external reference clock. Moreover, the injection
locked clock signal also helps to overcome failure in locking the receiver’s CDR loop that comes
65
from the frequency mismatch between the transmitter and the receiver due to the design variation
(e.g., process variation).
M1
Vin+
+Vout
-M2
M3
Vin-
Vctl
M1
M2
M3
(a)
Vin+
Vin-
Vout+
Vout-
Vctl
Vin+
Vin-
Vout+
Vout-
VctlVctl
90o 270o 180o 0o
(b)
Figure 3-10 A fully differential (a) shunt capacitor inverter with cross-coupled PMOS active load and (b) two-stage ring oscillator.
An injection-locked LC divider is introduced as a high frequency divider for the phase-
locked loop or low-power quadrature LO generation [26]. An external 5GHz clock is injected
into the VCO for generating 2.5GHz quadrature clock signals by which data modulation
performed. Figure 3-8 shows the structure of an injection-locked quadrature phase VCO [26].
The Q of the inductor for the LC tanks is approximately 8 and its value is 3.8nH. The varactor
value is 677fF with a fixed MIM capacitor of 329fF which offers approximately 20% tuning
66
range with a simulated 2mA tail current. The outputs of each stage are followed by a voltage
follower buffer not shown in Figure 3-11.
Vinj+
VQout-VIout-
Vcnt
VIout+ VQout+
-
Figure 3-11 Injection-locked LC QVCO.
3.2.5 I/Q Channel Signal Combining
The basic architecture of the HSRC-OQPSK transmitter follows that of a QPSK
modulator. Therefore, both I and Q channel signals must be combined together to generate the
HSRC-OQPSK signal. Since the mixer is operated in current mode, a combined signal of the I
and Q channels can easily be implemented by wiring both outputs of the I/Q channel mixers, as
shown in Figure 3-12. This makes the transmitter structure simple to implement.
3.2.6 Output Buffer
An output buffer of Rev. 1 transmitter has been designed with an open-drain structure as
shown in Figure 3-13. The output buffer has a differential three-stage cascaded structure
enabling the output buffer to have enough current to drive the 50Ω load. The last-stage of the
open drain buffer is pulled up with a 50Ω external resistor for the measurement. The resistor
values of each stage, R1, R2 are 550Ω, 140Ω, respectively which are implemented with on-chip
poly resistors. The DC bias currents, I1, I2, I3, of the buffer are 1.5mA, 6mA, 15mA
respectively.
67
Vin1-Vin1+
Vout+Vout-
Vin2+
Vin2-
Vin2+
RD RD
ISSVin1-Vin1+
Vout+Vout-
Vin2+
Vin2-
Vin2+
RD RD
ISS
- Signal Out +
Figure 3-12 Combining I and Q channel signal by direct connecting outputs.
Vin
Vout
I1
R1 R1
I2
R2 R2
+
-
I3
-
+
Figure 3-13 Three stage output buffer with open drain output stage.
The high impedance output of the output buffer used in Rev.1 transmitter may cause the
inter-symbol-interference (ISI) due to the mismatches [6], [27]. In order to minimize the
mismatch between the near-end (transmitter) and the far-end (receiver) and improve the signal
quality, an on-chip resistor of 60Ω is used in the Rev. 2 transmitter. Figure 3-10 shows the
differential output buffer with an on-chip terminated resistor. A drawback of the double
termination is unavoidable increasing power consumption. It would double the power dissipation
in order to deliver the same voltage swing at the receiver end because the buffer needs twice the
tail current compared to the open-drain structure.
68
For the HSRC-OQPSK signal, linear amplification (without limiting output with limiting
amplifier [28]) is needed for generating the modulated signal since the modulated signal should
be kept undistorted. Therefore, a buffer is designed with the constraints of limited voltage gain
and maximum current gain. The resistor values of each stage, R1, R2, and R3 are 550Ω, 140Ω,
and 60Ω, respectively which is implemented with on-chip poly resistors. The DC bias currents,
I1, I2, I3, of the buffer are 1.5mA, 6mA, 15mA respectively. The DC coupled output signal is
directly interfaced with the inputs with the pull-up of the receiver which enables double
termination. The architecture of the transceiver and detail test setup is discussed in Chapter 4.
Vin
Vout
I1
R1 R1
I2
R2 R2
+
-
I3
-
+
R3 R3
(a)
Transmitter
Channel
Receiver
+Vin-
ISS
RD RD
VDD
RL RL
(b)
Figure 3-14 Output buffer (a) differential three-stage output buffer (b) doubly terminated structure.
69
3.3 Chip Design
3.3.1 Rev. 1 Transmitter
An integrated HSRC-OQPSK transmitter (Rev. 1) was designed and fabricated using
TSMC 0.18um CMOS technology. The chip includes a serial-to-parallel logic, an injection-
locked LC VCO, mixers, and output buffers. Total chip size is 2000μm X 2000μm which
includes a transmitter and a receiver. The transmitter core without pads occupies 598μm X
575μm. Figure 3-15 shows the entire HSRC-OQPSK transceiver chip. The transmitter is
located at the lower right corner of the chip. The design includes a transmitter which modulates
the binary signal into HSRC-OQPSK signal. The transmitter consists of DET F/Fs, mixers, an
injection-locked VCO, and output buffers.
Receiver (Demodulator)
Transmitter (Modulator)
Receiver (Demodulator)
Transmitter (Modulator)
Figure 3-15 HSRC-OQPSK transceiver chip using TSMC 0.18μm CMOS technology.
The time domain simulation of the Rev.1 transmitter is performed using Cadence Spectre.
For the transmitter simulation, a random bit stream in the Cadence adhl library is used for
generating 10Gbps random data.
70
1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5-0 . 8
-0 . 6
-0 . 4
-0 . 2
0 . 0
0 . 2
0 . 4
0 . 6
0 . 8
Vou
t (V
)
T i m e ( n s )
(a)
0 5 10 15 20-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
Frequency (GHz)
Spe
ctru
m (d
B)
SimulationTheoretical
(b)
Figure 3-16 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum.
A 5GHz reference clock is injected into the transmitter for locking the VCO. The
generated 10Gbps serial data fed into the transmitter are separated into I and Q channel data. The
clock frequency is half-symbol-rate of the channel data, therefore, a double-edge triggered flip-
flop (DETFF) is used as a serial-to-parallel logic for each channel. The simulated time domain
71
waveforms and their spectrum without an external load are shown in Figure 3-16. The
spectrum’s first generated signal null is approximately 6.7GHz which is a little bit lower than
theoretical value of 7.5GHz while the difference between the main lobe and the second lobe is
less than 20dB which is higher than the theoretical value of 23dB as shown in Figure 3-16(b).
3.3.2 Rev. 2 Transmitter
Rev. 2 transmitter has been designed and fabricated in UMC 0.18um CMOS technology.
The chip occupies 1130μm X 1240μm. Figure 3-11 shows a simulation structure for the
transmitter. As discussed earlier, the design includes a transmitter which modulates the binary
signal into the HSRC-OQPSK signal. The transmitter consists of flip-flops, mixers, an injection-
locked VCO, and output buffers.
Modulator Logic
Varactors
Injection-Locked LC VCO
DC Blocking Cap.
gndvbmod Din+ Din-
Out+
Out-
Osc- Osc+vbovboc
ckin+
ckin-
vbIL vbvco vcnt
gnd
gnd
gnd
gnd
gnd
vdd
vdd
vdd
vdd
vdd
Figure 3-17 Transmitter die photo implemented by UMC 0.18μm CMOS technology.
72
The power and ground rings made by metal 5 are placed around the chip. To protect
circuits, the electrostatic discharges (ESD) circuits implemented by MOS devices are attached to
the DC bias lines. Octagon shape pads are used for the high speed signal. Pads for output signals
depicted as “Out+” and “Out-‘ are placed as close to the modulator logic as possible.
The architecture of the injection-locked LC VCO for Rev. 2 transmitter also has the same
architecture as shown in Figure 3-11. The Q of the inductor for the LC tanks is approximately 8
and its value is 3.8nH. The varactor value is 677fF with a fixed metal-insulator-metal (MIM)
capacitor of 329fF which offers approximately 20% tuning range with a simulated 2mA tail
current.
Similarly, the simulation has performed for the Rev.2 transmitter implemented by UMC
0.18μm CMOS technology. The conversion gain and input referred 1dB compression point of
the mixer are simulated using the Cadence Spectre [29] with the port resistance of 2.5KΩ
because a high impedance logic interface, rather than a 50Ω, is employed in the digital system.
Up-conversion gain and 1dB gain compression are simulated as shown in Figure 3-7.
Conversion gain is less than -1dB if the LO power is larger than -20dBm which roughly
corresponds to a single-ended peak-peak voltage amplitude of 230mV in a 2.5KΩ system. Figure
3-18(b) shows the conversion gain as the input RF frequency increases. For the 4GHz input, the
conversion gain is -1.03dB. The input referred 1dB compression is -23.08dBm with the port
resistance of 2.5KΩ, LO frequency of 2.5GHz, RF input frequency of 3GHz, and output
frequency of 5.5GHz.
For the transmitter simulation, a random bit stream in the Cadence adhl library is used for
generating 10Gbps random data. A 5GHz reference clock is injected into the transmitter for
locking the frequency of VCO. The generated 10Gbps serial data fed into the transmitter are
73
separated into I and Q channel data. The clock frequency is half-symbol-rate of the channel data,
therefore, a double-edge triggered flip-flop (DETFF) is used as a serial-to-parallel logic for each
channel.
-45 -40 -35 -30 -25 -20 -15 -10 -5 0 5-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Port Resistance=2.5Kohm
RF Input Frequncy=3GHz
Con
vers
ion
Ga
in (d
B)
LO Power (dBm)
1.0 1.5 2 .0 2.5 3.0 3.5 4.0-1.1
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
LO Power=-10dBm (2.5GHz)(Port Resistance=2.5Kohm)
Up-
Con
vers
ion
Gai
n (d
B)
RF Input Freqeuncy (GHz) (a) (b)
-50 -40 -30 -20 -10-55
-50
-45
-40
-35
-30
-25
-20
Output Freqeuncy=5.5GHzLO Freqeuncy=2.5GHz
Port Resistance=2.5Kohm
Input Referred 1dB Compression=-23.80dBm
Out
put
Pow
er (
dBm
)
Input Power (dBm) (c)
Figure 3-18 Linearity simulation of resistive Gilbert mixer using UMC 0.18μm CMOS technology (a) conversion gain vs. LO power, (b) conversion gain vs. RF input frequency, (c) input referred 1dB compression.
The time domain simulation of the HRSC-OQPSK transmitter is performed using the
Cadence Spectre. The simulated time domain waveforms and their spectrum without an external
load and channel are shown in Figure 3-19. The spectrum’s first generated signal null is 7.5GHz
74
while the first null point of 10Gbps NRZ data spectrum is 10GHz. The signal spectrum
bandwidth is reduced and the side lobes of the spectrum are greatly suppressed as well. The
difference between the main-lobe and the second-lobe of the spectrum is more than 20dB, which
agrees with the theoretical analysis of the spectrum of HSRC-OQPSK.
1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6
- 0 . 4
- 0 . 3
- 0 . 2
- 0 . 1
0 . 0
0 . 1
0 . 2
0 . 3
0 . 4
Vou
t (V)
T im e ( n s ) (a)
(b)
Figure 3-19 HSRC-OQPSK modulation signal (a) time domain waveforms (b) signal spectrum.
Figure 3-20 shows that the time domain waveforms of the dc-free signal using HSRC-
OQPSK transmitter. The spectrum’s first generated signal null is 5GHz which agrees with the
75
value of the theoretical spectrum. DC components of the signal have been reduced more than
theoretical values because the I and the Q channel data have been correlated every other bit due
to the fact that the 2.5Gbps data are being injected to I and Q channel simultaneously with just
half bit time data offset by serial-to-parallel logic. However, it is quite well-matched with
theoretical values to be considered 5Gbps signal effectively. The difference between the main
lobe and the second lobe is approximately 20dB while the difference is 13dB for the NRZ, which
agrees well with the analytical form of the dc-free spectrum derived as (2-21).
5 0 . 0 5 0 . 5 5 1 . 0 5 1 . 5 5 2 . 0
-0 . 4
-0 . 3
-0 . 2
-0 . 1
0 . 0
0 . 1
0 . 2
0 . 3
0 . 4
Am
plitu
de (
V)
T i m e ( n s ) (a)
0 5 10 15 20-90
-80
-70
-60
-50
-40
-30
-20
Frequency (GHz)
Sig
nal S
pect
rum
(dB
)
SimulationTheoretical
(b)
Figure 3-20 Simulated dc-free signaling (a) time domain waveforms (b) signal spectrum
76
3.4 Measurement
3.4.1 Rev.1 transmitter
Figure 3-12 shows the simplified evaluation board structure and an actual photograph. A
chip has attached to the pad on the PCB board using conductive epoxy as shown in Figure 3-20.
The pad is connected to the backside ground plane through via hole. And the signals of the chip
are connected directly to the PCB trace via wire-bond. All the ground pads are down bonded to
the pad. Thermal epoxy covers the chip for the purpose of protection. Rev. 1 transmitter’s output
buffer structure is open drain, hence, external chip resistors of 62Ω are attached to the output
signal lines, as shown in Figure 1-13. 110Ω chip resistors are attached to differential signal lines
of data input and injection clock inputs.
Chip
Ground Down Bonding
PCB FR4 BoardVia Hole
Chip PadSignal Trace
Ground Plane
Thermal epoxy(encapsulating)
Signal wire bonding
(a)
(b)
Figure 3-20 Test board for the Rev. 1 HSRC-OQPSK transmitter (transceiver) implemented by TSMC 0.18μm CMOS technology.
77
From the measurement results, the measured frequency tuning range of the VCO is
2.28GHz ~ 2.58GHz, which is approximately 12.3% from the center frequency 2.43GHz. The
center frequency of the VCO has shifted lower from the simulated center frequency
approximately 2.8%, which is caused from the layout parasitics such as routing metals, which are
not considered in the simulation phase. Figure 3-21 shows the QVCO’s signal spectrums for both
free-running and injection-locked states. Figure 3-21(a) shows the spectrum of the VCO in the
free running state. The center frequency is 2.5GHz with 5MHz span. Figure 1-14(b) shows the
spectrum of the VCO when the 5GHz clock is injected for the injection-locking of the QVCO.
The injection clock signal is generated from the Agilent E8254A signal generator. The carrier
power is measured approximately -5dBm with single-ended output. However, the carrier power
estimated -3dBm if the PCB trace and cable loss are taken into account. The characteristic of the
noise floor in the injection-locked mode is much lower than that in the free-running mode.
(a)
Figure 3-21 Measured spectrums and phase noise of the transmitter’s QVCO implemented by TSMC 0.18μm CMOS technology (center frequency of 2.5GHz with 5MHz span and 47 KHz RBW) (a) free-running mode (b) injection-locked mode (c) comparison of the phase noises between free-running and injection-locked modes.
78
(b)
10K 100K 1M-160
-140
-120
-100
-80
-60
-40
Frequency Offset (Hz)
Pha
se N
oise
(dB
c)
free-runninginjection-locked
(c)
Figure 3-21 (continued)
The spectrums show that the noise floor characteristic has been improved more than -
30dB. The phase noise has been measured by the Agilent E4448A spectrum analyzer that offers
the phase noise measurement mode. Figure 3-21(c) shows the phase noise comparison of the two
79
states which are the free-running and the injection-locked state. Measured results show that the
phase noise of free-running and injection-locked QVCO signal is -111dBc and -136dBc at 1MHz
frequency offset, respectively.
Agilent 86100B wideband oscilloscope has been used to get the eye-diagram of the signal.
The simplified test setup for 2.5Gbps and 10Gbps BER test are shown in Figure 3-22(a), (b),
respectively. Since 2.5Gbps random input is injected into both I and Q channel simultaneously,
the transmitted signal can be characterized as a 5Gbps signal equivalently even though the data
of I and Q channel are correlated to every other bit.
Wideband Oscilloscope
CK
Data In
Transmitter
Signal Out
Channel
Trigger In
50O
2.5GHz VCO Signal
Spectrum Analyzer
Signal Generator
VCO OutExternalClock In
5GHz Clock
2.5Gbps
Trigger Out
BERT
(a)
Wideband Oscilloscope
CK
Data In
Transmitter
Signal Out
Channel
Trigger In
50OSpectrum Analyzer
VCO Out
5GHz Clock
10Gbps
Trigger Out 1/2 sub clock
BERT
Phase Shifter
(b)
Figure 3-22 Simplified test setups for (a) 2.5Gbps (5Gbps equivalent) (b) 10Gbps random input for the transmitter.
80
For the 2.5Gbps measurement, 5GHz clock signal from the signal generator has been
injected to the transmitter for the VCO locking and a half frequency signal generated from the
VCO of the chip is fed into the Agilent 4903A BERT for the external clock. Then BERT
generated the 2.5Gbps synchronized to the clock inside the chip. 10Gbps test setup is more
simple because the 1/2 sub-rate clock from the BERT can be used as an injection clock of the
transmitter. Since the sub clock output of the BERT has the fixed phase with the data output, a
phase shifter between the sub clock signal output of the BERT and the clock input of the
transmitter for the timing offset between the input data and the clock.
The eye-diagram of the transmitter signal is shown in Figure 3-23. However, the
measurement could not get the proper eye-opening of the transmitted signal. Despite the
reasonable simulation results, the transmitted signal suffers from huge jitter components and two
eye-openings depicted in Figure 3-23 have different shapes even in 2.5Gbps data-rate due to the
delay mismatch between the data and the clock. The measured eye-diagram of the modulated
signal is shown in Figure 3-23. The delay mismatch is mainly caused from a delay unit
composed by a RC. The RC delay unit shown in Figure 3-4(a) does not compensate the delay
mismatch effectively because its characteristic varies much with the temperature and the voltage
and the process conditions. ISI noise due to the reflection of the high impedance node of open
drain output buffer could be another reason for this result. For the 10Gbps transmitted signal,
jitter components are introduced to the modulated signal, something that is not shown in this
dissertation. The eye-diagram of the HSRC-OQPSK signal is different from that of the NRZ
signal. As analyzed in Chapter 2, the low-energy symbol signal that practically determines the
BER performance also affects the eye-opening size directly.
81
Two eye-openings in Figure 3-23 are not identical to each other because the delay
mismatch between the clock and the data signals. A RC delay unit which is used in Rev. 1
transmitter offers a fixed delay. The limitation of the delay matching comes from the variation of
the resistive value due to the process conditions or the delay variations of the F/F over various
voltage, temperature, and process conditions.
45mV/div
50ps/div
45mV/div
50ps/div
Figure 3-23 Eye-diagram of the HSRC-OQPSK transmitted signal implemented by TSMC 0.18μm CMOS technology.
3.4.2 Rev. 2 transmitter
Rev. 2 transmitter has been designed and fabricated separately with the receiver. Figure 3-
14 shows a die photo of the transmitter test board. The chip is attached to the chip pad which is
also used down bond ground. The signals are connected to the PCB signal traces directly via
wire-bond. The down bonded grounds are connected to the backside ground plane. Thermal
epoxy covers the chip for the protection purpose. Surface mount type capacitor of
approximately100μF as bypass capacitors are attached between the power and the ground as
82
shown in Figure 3-24. Data and clock input signals are terminated with the external 50Ω
resistors. The board has oscillator signal outputs for the purpose of monitoring as well as
modulated signal outputs.
Figure 3-24 Test board for the Rev. 2 transmitter implemented by UMC 0.18μm CMOS technology.
Figure 3-25 shows signal spectrum of the Rev. 2 transmitter’s VCO. The measured tuning
range of the VCO is approximately 2.18GHz ~ 2.44GHz, which is representing the tuning range
of 12% frequency. The center frequency of the VCO has been shifted to approximately 10%
lower frequency than simulation. It is caused from the parasitics such as a routing metal
capacitance and resistors during the layout, which are not considered in the simulation phase.
Post-layout simulation with equivalent circuits modeled layout parasitics would improve the
mismatch problem. Figure 3-25(a), (b) show the frequency spectrum of the VCO both free-
running and injection-locked states, respectively. As is the case of Rev. 1, we can investigate the
noise floor of the spectrum of the injection-locked state that has been lowered than that of the
free-running state. The measured phase noise of the VCO is shown in Figure 3-25(c). To
measure the phase noise of the VCO, Agilent E4448A spectrum analyzer is used. The phase
noise performance of the VCO in the free-running state is approximately -110dBc/Hz at 1MHz
83
offset, while the -140dBc/Hz at 1MHz offset when the VCO is locked with the injection clock.
The phase noise performance of the VCO of the Rev. 2’s transmitter is almost the same as that of
Rev.1’s VCO implemented using TSMC 0.18μm CMOS technology.
(a)
(b)
Figure 3-25 Measured spectrums and phase noise of the transmitter’s QVCO implemented by UMC 0.18μm CMOS technology (center frequency of 2.25GHz with 100MHz span and 910 KHz RBW) (a) free-running mode (b) injection-locked mode (c) comparison of the phase noises between the free-running and the injection-locked modes.
84
10K 100K 1M-160
-140
-120
-100
-80
-60
-40
Offset Frequency (Hz)
Pha
se N
oise
(dB
c)
free-runninginjection-locked
(c)
Figure 3-25 (continued).
Figure 3-26 shows the measured eye-diagram of the transmitted signal where the 2.43Gbps
231-1 pseudo random bit streams (PRBS) are injected into the transmitter that generates 4.86Gbps
transmitted signal equivalently. From the measurement results, the clock and data
synchronization using a buffer insertion depicted in Figure 3-4 can effectively be working to
generate the HSRC-OQPSK modulated signal. Compared to Rev.1 transmitter using a RC delay
unit for compensating delay mismatch, a clear eye-opening has been obtained. The buffer
insertion as a delay unit discussed in section 3.2.1 can effectively make good compensation of
the delay mismatch while the RC delay unit used in Rev.1’s transmitter did not compensate the
delay mismatch effectively.
SMA connectors are used to connect the channels in the test board shown in Figure 3-24.
The characteristic impedance of 50Ω channel 6.2mil FR-4 PCB board and tangential loss is
approximately 0.023. Since the PCB channel has a low-pass characteristic as discussed in
85
Chapter 1, the detected signal power at the receiver end drops as the channel length increases.
Therefore, the eye-opening is getting smaller as the channel increases and eye-opening would be
closed after tracing a long channel.
Figure 3-26 shows the measured channel characteristics used in the measurement. Three
different lengths of PCB trace and one SATA of 19” length cable are used to compare the
performances. The measured results show that 20” trace has a loss of 13dB at 6GHz while the 5”
channel is approximately 3dB.
0 2 4 6 8 10 12-50
-40
-30
-20
-10
0
10
Frequency (GHz)
S21
(dB
)
PCB-5"PCB-10"PCB-20"SATA-19"
Figure 3-26 Characteristics of channels used in the measurement.
The measured peak-to-peak small eye-opening of the transmitted signal after tracing 2”
PCB trace with a SMA cable is about 300mV without equalization of the signal at the trace end.
Peak-to-peak eye-opening of the flat signal which has the largest symbol energy (Es,f) is
approximately 400mV. The eye-opening after tracing the 10” channel is reduced to 150mV. And
less than 80mV eye-opening has been obtained after 20” trace. Another serial link channel,
86
serial-ATA (SATA) cable, has been used for this experiment to evaluate the performance of the
transmitter. A 19” SATA cable with 2” PCB trace to connected transmitter is used to obtain the
eye-diagram. Figure 3-16(d) shows the eye-diagram after 19” SATA cable trace. More balanced
eye-diagram has been obtained compared to PCB trace because the differential signals are
strongly coupled than PCB channels used in the measurement.
60mV/div
50ps/div
60mV/div
50ps/div
(a)
60mV/div
50ps/div
60mV/div
50ps/div
(b)
Figure 3-27 Eye-diagram of HSRC-OQPSK transmitted signal implemented by UMC 0.18μm CMOS technology after (a) 2” PCB trace, (b) 5” PCB trace, (c) 10” PCB trace, (d) 20” PCB trace, (e) 19” SATA cable, in response to 4.86Gbps (both I and Q channel input with 2.43Gbps pseudo random bit stream (PRBS) sequence of 231-1).
87
60mV/div
50ps/div
60mV/div
50ps/div
(c)
60mV/div
50ps/div
60mV/div
50ps/div (d)
60mV/div
50ps/div
60mV/div
50ps/div (e)
Figure 3-27 (continued).
88
Figure 3-28 shows spectrum of the 4.86Gbps dc-free signal. High frequency components
of the signal are suppressed due to the signal loss at the test board and the limitation of the
operating frequency of the circuit. However, the nulls at dc and the other frequency of the
spectrum are quite well matched with the theoretical values.
0 5 10 15-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
Frequency (GHz)
Sig
nal S
pect
rum
(dB
m)
MeasurementTheoretical
Figure 3-28 Spectrum of 4.86Gbps dc-free signal.
Figure 3-29 shows the measured eye-diagram of the HSRC-OQPSK signal in response to
9.72Gbps PRBS sequence of 27-1. The measured eye-diagram shows that the HSRC-OQPSK
signal generates the similar eye-diagram shape to that of the duobinary signal [30]. A major
difference of the signal eye-diagram between the HSRC-OQPSK and duobinary signals is that
HSRC-OQPSK has no decision references because it uses only a two-level decision while the
duobinary signal needs the two decision level to decide the logical value of the signal [9], [30-
31]. Therefore, it is better for the HSRC-OQPSK signal to open the side eye-diagram wide
enough depicted with a blue diamond shape (ideal eye-opening). Actually, the HSRC-OQPSK
89
signal can be obtained based on the duobinary decoding scheme assuming the high frequency
components of the signal are filtered out at the band-limited channel. However, every 3rd and 4th
bit data should be reversed to get the proper HSRC-OQPSK signal.
60mV/div
20ps/div
ideal eye-opening
60mV/div
20ps/div
60mV/div
20ps/div
ideal eye-opening
(a)
100mV/div
100ps/div
100mV/div
100ps/div
(b)
Figure 3-29 Eye-diagram of the HSRC-OQPSK transmitted signal with 9.72Gbps PRBS sequence of (a) 27-1 (ideal eye-opening is depicted with blue line), (b) 231-1.
As discussed in Chapter 2, the consecutive transition signal which has low signal energy
makes the diamond shape eye-diagram depicted with a blue line in Figure 3-29(a). The signals
90
suffer from severe attenuation of the signal energy as shown in Figure 3-30. The small eye-
opening is less than 60mV which is smaller than the simulation results which will affect the BER
performance of the transceiver. The BER performance will be discussed in Chapter 4. The
attenuation of the signal mainly comes from the limit of the circuit’s operating frequency. And
the delay mismatch also prevents enlarging the eye-opening of the signal. Broadband circuit
techniques such as a fT doubling of the output buffer are needed to increase the signal quality and
maximize the eye-opening. The spectrum shown in Figure 3-27(c) also represents the high
frequency attenuation of the signal and there are no side lobes of the signal above 10GHz which
are supposed to follow the theoretical spectrum corresponding to the red line. The performance
of the HSRC-OQPSK transceiver associated with the transmitter is discussed in Chapter 4.
Figure 3-30 Signal spectrum in response to9.72Gbps PRBS sequence of 27-1.
91
CHAPTER 4 HSRC-OQPSK RECEIVER DESIGN
4.1 Receiver Architecture
A conceptual HSRC-OQPSK receiver architecture which is based on that of a QPSK has
been depicted in Figure 3-2. Different from the conventional serial link receiver that uses a PAM
signal, the HSRC-OQPSK receiver uses a carrier signal which is quarter data-rate frequency for
the demodulation. Therefore, a quarter-rate CDR must be incorporated with the receiver. A
quarter-rate PD as a CDR for the conventional PAM signal has been introduced and
demonstrated [32]. The HSRC-OQPSK receiver (Rev. 1) designed with TSMC 0.18μm CMOS
technology uses the same PD architecture introduced in [32].
To improve the performance of the proposed HSRC-OQPSK receiver, a new CDR
architecture has been proposed for the Rev. 2 receiver and implemented using UMC 0.18μm
CMOS technology. The proposed CDR has been modified from a Costas loop which is often
used for the carrier recovery loop for the BPSK and QPSK signal. The details are discussed in
section 4.3.
4.2 HSRC-OQPSK Receiver (Rev. 1)
Figure 4-1 shows the HSRC-OQPSK receiver architecture with a quarter-rate CDR. The
input buffer amplifies the incoming signal followed by I and Q channel mixers. As described in
the conceptual receiver architecture, the receiver has I and Q channels. I and Q channel mixers
are demodulating the received signal using the quarter data-rate carrier signals recovered by a
CDR loop. DET F/Fs followed by I/Q mixers determine the retimed data of I and Q channels. To
recover the clock which is quarter data-rate, a conventional quarter-rate PD [32] has been
adopted for the Rev. 1 receiver. Originally, the quarter-rate PD has been proposed for the
40Gbps NRZ signal relaxing timing requirements and reducing the cost of fabrication [32].
92
Signal in
VCO
DET F/F
DET F/F
90o
I
Q
e
IData
QData
LF
CI
CQ
Quarter-rate PD
Figure 4-1 HSRC-QOPSK receiver (Rev. 1) architecture incorporated with quarter-rate PD.
Figure 4-2(a) shows the phase detector (PD) architecture employed in the Rev. 1 receiver.
The PD is introduced in [32]. F/Fs strobe the data by using multi-phase VCO signal and
determine the polarity of the phase error by using XOR gates. The outputs of two consecutive
XOR gates are connected to the differential V/I converters which determine the phase error.
Figure 4-2(b) shows the timing diagram of the PD.
(a) (b)
Figure 4-2 Quarter-rate phase detector (a) architecture (b) waveforms (for 40Gbps NRZ) [32].
The Rev. 1 receiver has been fabricated with TSMC 0.18μm CMOS technology. The
simulated maximum current of the PD in the Rev.1 receiver is approximately 200μA.
93
In the measurement, however, the PD has failed to appraise the performance of the receiver
for the HSRC-OQPSK signal. There might be several reasons. First, the transmitter signal itself
was not good enough for the receiver due to the limited performance of the transmitter. Second,
the PD employed in the receiver is originally for the NRZ signal. The PD has the best
performance when the signal has a sharp transition like the NRZ signal and not like the HSRC-
OQPSK signal. Since the meta-stable behavior of the F/F will lead to the finite gain of the PD
[32], the HSRC-QOPSK signal having no discrete transition like NRZ would increase the meta-
stable behavior in F/Fs. Consequently, the PD gain might be decreased significantly.
4.3 HSRC-OQPSK Receiver (Rev. 2)
Figure 4-3 shows the proposed HSRC-OQPSK receiver structure. The receiver is based on
a Costas loop (often used as a carrier recovery loop of a conventional QPSK demodulator) [33-
34]. Two mixers separate the incoming modulated signal into the I and Q channel for the signal
demodulation. After passing through the mixer, the I/Q channel signals are fed into the DET F/Fs
clocked with quarter data-rate frequency carrier signals recovered by the CDR loop. The loop
also allows the retimed I/Q channel data. Generally, a carrier recovery loop as well as a Costas
loop has LPFs in order to get rid of the high frequency components in the I and Q channel path
and get the phase error to control the VCO of the receiver. Unlike a conventional carrier
recovery loop, the proposed CDR does not include LPFs. Since the carrier recovery of the
HSRC-OQPSK receiver is basically the same as the symbol synchronization of the QPSK
demodulation process, it is expected that the proposed CDR loop (algorithm) can be effectively
applied for the symbol synchronization loop of the QPSK demodulation as well. The detailed
analysis of the proposed receiver integrated with a CDR loop will be discussed.
94
Signal In
VCO
DET F/F
PP S/H
DET F/F
PP S/H
90o
LF
I
Q
e-
+
Is
Qs
I Data
Q Data
Figure 4-3 HSRC-OQPSK receiver architecture incorporated with a CDR.
4.3.1 Polarity-Type Costas Loop for Carrier Synchronization
A Costas loop is commonly used as a carrier recovery loop for the QPSK type modulation
signal. The Costas loop was first introduced in [35]. A couple of modified Costas loops have
been proposed and their performances analyzed in [33-34]. Other structures for the carrier
recovery loops for the QPSK signals are introduced and analyzed in [36-41].
Figure 4-4 shows a polarity-type Costas loop for the QPSK type signal proposed in [33].
The polarity-type Costas loop is a kind of hard-limited carrier recovery loop which is known to
have a better performance than that of the non-limited type carrier recovery loops in a higher
signal-to-noise ratio (SNR) situation [10], [34]. Input signals of the polarity-type Costas loop are
mixed with quadrature carriers generated from a quadrature VCO (QVCO) and separated into the
I and the Q channel by the mixers. The I/Q channel signals pass through low-pass filters (LPFs)
to get rid of the high-frequency components which have no significance for generating the
control signal. These signals are mixed again with the limited signals from the other channel, as
shown in Figure 4-4.
95
Signal in
VCO90o
LPF
LPF
Loop Filter
-1
+1
-1
+1
-
+
Figure 4-4 Polarity-type Costas loop for QPSK signal carrier recovery.
In QPSK modulation, the signal coming into the Costas loop can be defined as (4-1),
where S is the average received signal power, mI(t), mQ(t) are the data sequences of ±1 of I/Q
channel, ωc is the carrier frequency and θi is the phase of the signal.
( ) ( ) ( ) ( ) ( )[ ]icQicI ttmttmSts θωθω +⋅++⋅= cossin (4-1)
The phase error signal controlling the VCO frequency is generated by subtracting these
two signals from each channel. Assume VCO signal has an amplitude of S1 and a frequency
of ωc, then the low frequency output of the polity-type Costas loop can be represented using
trigonometric operations as (4-2), where Ф=θi-θo, θo is the phase of the VCO signal [42].
( ) ( ) ( )[ ] ( ) ( )[ ]( ) ( )[ ] ( ) ( )[ ]φφφφ
φφφφ
cossinsgnsincos
sincossgncossin21
tmtmtmtm
tmtmtmtmte
QIQI
QIQI
+−−
−+= (4-2)
Then the low frequency phase error can be rewritten as (4-3).
96
( )
⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
≤<−
≤≤−
−<≤−
=
43
4cos
44sin
443cos
πφπφ
πφπφ
πφπφ
te (4-3)
4.3.2 A New Clock and Data Recovery (CDR) based on the Modified Costas Loop
Figure 4-5 shows the proposed CDR loop which is basically the same as the HSRC-
OQPSK receiver structure. Since the CDR offers retimed data similar to other CDRs do, it can be
used as a receiver. The proposed CDR loop for the HSRC-OQPSK modulation and its analysis
and simulation results are presented in this section.
Note that the HSRC-OQPSK modulation inherits the properties of the QPSK modulation
even though its carrier frequency is lower than the data-rate. Therefore, it is expected that the
polarity-type Costas loop shown in Figure 4-4, can be used as a clock (carrier) recovery loop for
the HSRC-OQPSK signal. However, there are a couple of limitations in implementing a CDR
loop and demodulating the HSRC-OQPSK signal. First, since the data-rate HSRC-OQPSK
signal is higher than its carrier frequency, LPFs in I/Q channels selecting low frequency
components cannot be used for the phase detector output in the Costas loop. Second, a coherent
demodulation of the QPSK signal with a matched filter consisting of an integrate/dump and a
decision circuit is very difficult to implement in the GHz range. Also, a bit-time delay between
the I and the Q channel data should be properly compensated for the phase error detection as
well as the demodulation. Consequently, the conventional Costas loop should be modified for the
CDR of HSRC-OQPSK signal. A new CDR loop for HSRC-OQPSK signal modified from the
Costas loop is proposed and shown in Figure 4-5.
97
Signal in
VCO
DET F/F
PP S/H
DET F/F
PP S/H
90o
I
Q
e-
+
IS
QS
IF
QF
LF
CI
CQ
Figure 4-5 A modified Costas loop for the HSRC-OQPSK signal clock and data recovery.
The modulated signals fed into the CDR are split into the I/Q channels and mixed with
quadrature carrier signal generated from QVCO. The LPFs shown in Figure 4-2 are removed and
the limiters are replaced by DET F/Fs. Sample/hold (S/H) circuits sampling both clock edges
hold the signal of each channel by 2 bit-time for the proper evaluation of the phase error. The
demodulated signals, I and Q, are sampled by sample/holds and DET F/Fs. The sampled signals,
IS and QF, QS, and IF, are mixed for the final evaluation of the phase error. The sampling time of
the I and Q channel are offset by 1 bit-time. Therefore, the CDR loop evaluates the phase error
every 1 bit-time. The details are analyzed and a behavioral model simulation will be presented.
4.3.2.1 Phase detector characteristics
The received HSRC-OQPSK signal can be represented as (4-4) [43], where Tb is a bit time
and θi is an arbitrary phase of the incoming signal.
( ) ( ) ( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+⋅+⎟⎟
⎠
⎞⎜⎜⎝
⎛+⋅= i
bQi
bI T
ttmTttmts θπθπ
2cos
21
2sin
21 (4-4)
98
For the QVCO signals of the CDR, they can be assumed as (4-5), where θo is the initial phase of
the QVCO signals.
( ) ( ) ⎟⎟⎠
⎞⎜⎜⎝
⎛+=⎟⎟
⎠
⎞⎜⎜⎝
⎛+= o
bQo
bI T
ttcTttc θπθπ
2cos2,
2sin2 (4-5)
Then I/Q signals can be obtained as (4-6), (4-7) by multiplying two signals represented as (4-4),
(4-5) using trigonometric operations.
( ) ( ) ( )
( ) ( )⎥⎥⎦
⎤
⎢⎢⎣
⎡−−⎟⎟
⎠
⎞⎜⎜⎝
⎛++⋅+
⎥⎥⎦
⎤
⎢⎢⎣
⎡−−⎟⎟
⎠
⎞⎜⎜⎝
⎛++⋅−=
oioib
Q
oioib
I
Tttm
TttmtI
θθθθπ
θθθθπ
sinsin21
coscos21
(4-6)
( ) ( ) ( )
( ) ( )⎥⎥⎦
⎤
⎢⎢⎣
⎡−+⎟⎟
⎠
⎞⎜⎜⎝
⎛++⋅+
⎥⎥⎦
⎤
⎢⎢⎣
⎡−+⎟⎟
⎠
⎞⎜⎜⎝
⎛++⋅=
oioib
Q
oioib
I
Tttm
TttmtQ
θθθθπ
θθθθπ
coscos21
sinsin21
(4-7)
Since the samplings of S/Hs and F/Fs are taking place at the zero crossing points of carrier
signals defined in (4-5), one can obtain the sampling time of each channel by setting
cI(tQ)=cQ(tI)=0. Therefore, the sampling time for the I/Q channels are defined as (4-8).
⎟⎠⎞
⎜⎝⎛ ⋅−=⎟
⎠⎞
⎜⎝⎛ ⋅−=
πθ
πθ o
bQo
bI TtTt 2,21 (4-8)
Now, one can define the sampled signals using (4-8). The sampled signals, IS(t) and QS(t) shown
in Figure 4-3, can be calculated as (4-9), (4-10) by substituting (4-8) into (4-6), (4-7)
respectively, where Ф=θi-θo.
99
( ) ( ) ( ) φφ sincos ⋅−⋅= IQIIS tmtmtI (13)
( ) ( ) ( ) φφ cossin ⋅+⋅= QQQIS tmtmtQ (14)
Similarly, IF and QF signals can be determined by limiting the sampled signals which are
obtained by taking sgn[Is(tI)], sgn[Qs(tQ)]. For these signals, the phase difference between the
received signal and the carrier signal determines the values of IF and QF. Therefore, IF and QF are
represented as (4-11), (4-12), respectively.
( )
( )
( )
( )⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
<≤−
<≤−
−<≤−
=
43
4
44
443
πφπ
πφπ
πφπ
IQ
II
IQ
IF
tm
tm
tm
tI (4-11)
( )( )( )( )
⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
<≤
<≤−
−<≤−−
=
43
4
44
443
πφπ
πφπ
πφπ
QI
QI
QF
tm
tm
tm
tQ (4-12)
The data sequences of mI and mQ should be specified for determining the phase error, e(t).
Figure 4-4 illustrates the early and late sampled I/Q channel data when the phase difference, Ф, is
either positive or negative. When Ф<0, the sampling time is earlier than the ideal sampling time
while the sampling time is later than the ideal sampling time when Ф<0, as shown in Figure 4-6.
Consequently, data constraints related to the phase difference can be stated as (4-13).
( ) ( )( ) ( )⎩
⎨⎧
<=≥=
00
φφ
QIII
QQIQ
tmtmtmtm
(4-13)
100
mI
mQmQ(tI) mQ(tQ)
mI(tI) mI(tQ)Ф<0Ф>0
mI
mQmQ(tI) mQ(tQ)
mI(tI) mI(tQ)Ф<0Ф>0
Figure 4-6 Early and late sampling time of I/Q data.
Now, the phase error e(t), represented as (4-14), can be estimated. The CDR loop evaluates
the phase error every bit-time because the IS(tI) and QF(tQ) or QS(tQ) and IF(tI) are overlapped by
a bit time.
e(t)= QS(t)IF(tI) - IS(t)QF(tQ) (4-14)
With the data constraints in (4-13), the phase error, e(t), is obtained as (4-15) if it is assumed that
the amplitude of the mI, mQ are unity.
( )
( ) ( )( )( ) ( )( )( ) ( )( )( ) ( )( )⎪
⎪⎪⎪
⎩
⎪⎪⎪⎪
⎨
⎧
≤<⋅⋅+−
≤≤⋅⋅+
<≤−⋅⋅+
−<≤−⋅⋅+
=
43
4cos1
40sin1
04
sin144
3cos1
πφπφ
πφφ
φπφ
πφπφ
QIII
QIII
QQIQ
QQIQ
tmtm
tmtm
tmtm
tmtm
te (4-15)
Still, the values of mQ(tI)·mQ(tQ) when Φ<0 and mI(tI)·mI(tQ) when Φ>0 cannot be fixed to
finalize e(t) because the random data sequences are uncorrelated. The values can be either -1 or 1
which is dependant on the data sequences. The undetermined value of -1 or 1 leads to two
101
possible results of e(t). The coefficients of each term of (4-15) will be zero or ±2 when the value
is -1 or 1, respectively. Then, the averaged phase error can be rewritten as (4-16) with the
assumptions that I/Q channel data sequences occur equally likely with symbol time and the phase
error process is changing slowly over the large number of symbol periods. Consequently, the
averaged phase error is equivalent to that of the polarity-type Costas loop. Its plot is shown in
Figure 4-7.
( )
⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
≤<−
≤≤−
−<≤−
≅
43
4cos
44sin
443cos
πφπφ
πφπφ
πφπφ
te (4-16)
π/4 π/2
e
3π/4-π/4π/2-3π/4 Фπ/4 π/2
e
3π/4-π/4π/2-3π/4 Ф
Figure 4-7 Averaged phase detector characteristic of the proposed CDR loop.
The proposed CDR loop based on the polarity-type Costas loop can be characterized as a
linear phase detector, as shown in Figure 4-5. A linear phase detector (PD) generates an error
signal linearly proportional to phase error. The output of the PD goes to zero when the loop is
locked while a non-linear PD is pumping the charge even with the loop in a locked state. It is
known that a linear PD produces lower jitter compared to non-linear PD due to less charge pump
102
activities [44-45]. Therefore, the proposed CDR is expected to generate less clock jitter noise
compared to non-linear type PD. Moreover, the carrier frequency of the proposed CDR loop for
HSRC-OQPSK signal is quarter data-rate, hence, the loop is equivalent to quarter-rate CDR for
NRZ signal. As a result, the proposed CDR can relax the timing constraints of the receiver
system. In addition, the proposed CDR allows retimed I/Q channel data as shown in Figure 4-1,
similar to that of other CDRs [6]. In addition, although the proposed CDR has been developed
for the clock recovery of the serial link transceiver system, the concept can also be applied to the
symbol synchronization of the QPSK signal in wireless communications.
One drawback of the proposed CDR is that there are four stable locking points over the π
radian period, only one of which has proper phase information. A differential encoding in the
transmitter can resolve this four-fold phase ambiguity problem at the cost of 3dB reduced signal
power [10]. And, other methods for phase ambiguity resolution have been introduced in [46].
However, this four-fold ambiguity issue is for future work.
4.3.2.2 Loop analysis
The modified Costas loop can be represented by the equivalent model, as shown in Figure
4-8. The Ka is the gain of the combiner, Kv is the VCO gain, and F(S) is the function of the loop
filter. Transient response of the loop cannot be characterized easily; however, the loop can be
modeled as a linear system with assumptions that the phase error, Ф, changes slowly over a large
amount of the symbol period [40].
Assuming no noise is added in this loop, then the overall transfer function of the closed
loop is calculated as (4-17).
( ) ( )( )
( )( )sFKKs
sFKKss
sHva
va
i
o
+==
θθ
(4-17)
103
VCO
Ka F(s)+
-
Kv/s
ni
e
0o
0i O/
Figure 4-8 Equivalent linear model of proposed CDR for HSRC-OQPSK.
Since the transfer function of the loop filter can affect the overall transfer function of the
system, the loop filter should be carefully chosen to stabilize the system. A lead/lag network is
widely used as a loop filter because it offers an increased open loop phase margin of the system
by inserting zero to the transfer function [6]. The transfer function can be rewritten by using the
parameters from circuit implementation. Ka=180μA/V is obtained from the circuit simulation and
Kv=120MHz/V, as shown in Figure 4-18. A lead/lag network with Rp=7KΩ and Cp=30pF is used
for the simulation purpose to reduce the simulation time and the required memory. With these
parameters, the closed loop gain of the system is represented as (22). The zero of the closed loop
of the transfer function is located at 1/RpCp. In real design for the measurement, the closed loop
bandwidth of 1MHz has been chosen which is examined in a later section.
( )( )
z
vapva
ppz
va
CKKsRKKs
sCRC
KK
sH++
+=
2
1 (4-18)
104
The stability issues of the type I and type II PLL are discussed thoroughly in [6], [47-48].
The phase margin of the system’s open loop transfer function is often used to examine the
stability of the system shown in Figure 4-7. The characteristics of the open loop transfer function
show an approximately 90° phase margin at the gain crossover which will lead to stable locking
of the system.
100 102 104 106 108 1010-100
0
100
200
300
400
Ope
n Lo
op G
ain,
|Hop
en| (
dB)
100 102 104 106 108 1010
-180
-160
-140
-120
-100
-80
Frequency (Hz)
Pha
se, ∠
Hop
en (d
eg)
-40dB/dec
-20dB/dec
Figure 4-9 Open loop gain characteristics of the proposed CDR loop.
4.3.2.3 Noise characteristics
The phase error characteristic, S-curve, which is expressed in terms of signal-to-noise ratio
(SNR), can be calculated by averaging the value of the phase error as (4-19) [33]. Obviously, the
loop of the system includes the noise term depicted in Figure 4-6.
( ) ( )[ ]φφ |teEg = (4-19)
As we have discussed in the previous section, the phase error of the proposed CDR loop
based on the modified Costas loop is equivalent to that of the polarity-type Costas loop.
105
Therefore, the averaged phase error of the proposed CDR can also be considered to have the
same value as that of the polarity-type Costas loop. Consequently, the phase error characteristic
can be represented as the equivalent form as derived in [33]. The S-curve for the QPSK signal,
that is M=4 in [33], is represented as (4-20), where R=S/2N0B, S is the signal power, N0 is the
Gaussian noise spectral density, B is the noise bandwidth, am=sin[(2m-1)π/4], bm=cos[(2m-
1)π/4], and ( ) ( )∫∞
−=x
dxxxQ 2/exp21 2
π.
( ) ( )
( )[ ] ( )[ ] ( )
( )[ ] ( )[ ] φφφφ
φφπφφφφ
φφπφ
sincos2sincos2
cossin4
sin41
sincos2sincos2
cossin4
sin41,
4
1
4
1
llll
lll
llll
lll
baRQbaRQ
ba
baRQbaRQ
baRg
+−−−⋅
−⎟⎠⎞
⎜⎝⎛+
−−+−⋅
+⎟⎠⎞
⎜⎝⎛=
∑
∑
=
=
(4-20)
The phase error gain of the CDR loop is dependant on the SNR, as shown in Figure 4-8. In low
SNR, the S-curve performs like as sin4Ф [33].
-150 -100 -50 0 50 100 150-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Phase Error (deg)
Nor
mal
ized
S-C
urve
0dB10dB20dB30dB∞dB
Figure 4-10 Phase error characteristic with SNR (S-curve) of the proposed CDR loop.
106
The S-curve gives the ability to estimate the characteristics of the CDR loop when the
noise is injected. However, the HSRC-OQPSK signal is used as a wide-band signal utilizing a
band-limited channel such as a PCB board trace. The band-limited channel having low-pass
characteristics may affect the S-curve behaviors.
4.3.3 Behavioral Model Simulations
4.3.3.1 Phase error
To verify the functionalities of the proposed CDR, the proposed CDR is designed by
behavioral models using MATLAB Simulink. A transmitter generating the HSRC-OQPSK
signal is also modeled, as shown in Figure 4-11.
HSRC-OQPSK TransmitterModified Costas Loop Structure
Integrator
HSRC-OQPSK TransmitterModified Costas Loop Structure
Integrator
Figure 4-11 Phase error simulations of the CDR for the HSRC-OQPSK signal with MatLab Simulink behavioral models.
The transmitter and the receiver structures modeled by behavioral components are
basically the same as described in the previous section. The transmitter generates HSRC-OQPSK
signals using random data. The generated HSRC-OQPSK signal is fed into the receiver directly.
A F/F in the receiver is modeled by a S/H and a limiter, as shown in Figure 4-11.
For the phase error simulation, the QVCO signals modeled with ideal sinusoidal sources
with phase offset of 90° are used in both the transmitter and the receiver. An integrator of the
107
CDR accumulates the phase error generated from the phase mismatch of the carrier signals
between the transmitter and the CDR loop. The phase mismatch can easily be modeled by
changing the phase of the carrier signal. The simulation result of the averaged phase error fits
well with the analytical form obtained in (4-16), as shown in Figure 4-12.
- 2.0 - 1.5 -1. 0 - 0.5 0.0 0. 5 1.0 1.5 2.0
- 0.8
- 0.6
- 0.4
- 0.2
0.0
0.2
0.4
0.6
0.8
e (N
orm
aliz
ed P
hase
Gai
n)
T heta (Phas e D if ferenc e)
Figure 4-12 Behavioral model simulation result of the phase error for the proposed CDR using MATLAB.
4.3.3.2 Time domain simulation
The system is modeled with data-rate of 1bps and the frequency of the carrier is 0.25Hz.
The reduced data-rate and the carrier frequency can be considered as 10Gbps and 2.5GHz
respectively in actual implementation.
Two VCOs with a phase difference of 90º replaced the ideal carrier signals in order to
model a QVCO, as shown as Figure 4-13. And the loop filter (LF) is characterized with a
transfer function which is equivalent to the characteristics of a series RC network given in the
loop analysis section.
108
The phase error signal, e(t), changes the frequency of the modeled QVCO. Figure 4-14
shows the simulation result of the phase error, e(t), which controls the frequency of the QVCO.
The initial frequency of the QVCO is 0.247Hz with a gain of 0.012Hz/V which are comparable
to 2.47GHz and 120MHz/V in a 10Gbps system, respectively.
Quadrature VCO
Loop Filter
Quadrature VCO
Loop Filter
Figure 4-13 HSRC-OQPSK Transceiver Model with QVCO for Time-Domain Simulation.
Figure 4-14 Time-domain response of phase error signal for the VCO frequency control.
109
In the locking state, approximately after 3700 time steps in Figure 4-14, the control voltage
is not changing because no error signal is generated from the loop. Ideally, the phase detector
(PD) of the loop would not generate an error signal while the non-linear PDs, such as a bang-
bang PD, have a charge injection even in the locking state, which causes large control voltage
transitions in a type II PLL [6], [47]. However, high frequency components might be injected at
this control signal because of unavoidable mismatches in circuits, such as a device and an I/Q
mismatches in actual circuits.
Phase differences are added to one of the VCOs in order to observe the I/Q mismatch-
effects. Figure 4-15 illustrates the simulation of phase error, e(t), when the case of the phase
mismatch is 10°. The locking time and ripple voltage of the phase error signal increase, as shown
in Figure 4-15. The ripple voltage directly affects the clock jitter making it degrade the system
performance.
Figure 4-15 Time-domain response of phase error signal for the VCO frequency control with 10° I/Q mismatch.
110
Figure 4-16 shows the normalized locking time and peak-peak ripple voltage in the locking
process. Since the locking time changes for random data sequences, the simulation results are
obtained from the average value of 5-time repeated simulation results. t0 is the average locking
time of control voltage when no I/Q mismatch has occurred. From the simulation results shown
in Figure 4-16, the locking time and peak-peak ripple voltage are almost proportional to the
amount of I/Q mismatch. Needless to say, it is important to reduce the ripple voltage because it
directly affects the QVCO’s phase noise.
0 2 4 6 8 10
0
1 0
2 0
3 0
4 0
5 0
I/Q Mismatch (deg)
Nor
mal
ized
Lo
ckin
g T
ime
(t-t 0)
/t 0
0.00
0.01
0.02
0.03
0.04
Ripple V
oltage in locking S
tate (V)
Figure 4-16 Normalized settling time and peak-peak ripple voltage in locking state vs. I/Q mismatch.
4.4 Chip Design (Rev. 2)
Since all the components can be characterized as a linear model in the behavioral model
simulation, the simulation is well-matched with the theoretical results. However, there are many
non-linear factors in circuit implementation such as a VCO gain, a clock jitter, or a clock feed
through of a S/H circuit.
111
In this chapter, the proposed receiver combined with a CDR is implemented and simulated
with UMC 0.18μm CMOS technology. The receiver consists of an input buffer, mixers, S/Hs,
F/Fs, a V/I converter, and a QVCO. Most of the circuits are designed with CML style circuits;
this is much the same for the transmitter design.
4.4.1 Circuit Implementation
4.4.1.1 Sample/hold circuit
[49] proposed a high speed S/H circuit, sampling bandwidth up to 7GHz with 0.25μm
CMOS technology, as shown in Figure 4-17. In tracking mode where the clock is high, the S/H
circuit operates as a differential amplifier. In the sampling mode when the clock falls, PMOS
loads and tail current source are turned off making the output nodes isolated so that the S/H
circuit is holding the sampled signal. M2 provides a low resistance differential load for wide
bandwidth operation. M1 pulls up the tail node to quickly turn off the input transistors, which
allows the amplifier bandwidth to be close to the sampling bandwidth [49].
Vin
clk
bias
Vref
outPoutM
clkb
M2
M1
Figure 4-17 A high-speed differential sample/hold (S/H) circuit [49].
As mentioned in the previous section, a S/H circuit for the proposed CDR loop should
sample the input signal at both clock edges and maintain the signal until the next clock edge
112
(either rising or falling) occurs because the clock frequency of the loop for each channel is half-
symbol-rate. A ping-pong (PP) structure S/H circuit [50] can be used for this purpose. An analog
MUX selects one of S/Hs which are tracking the input signal alternately.
Figure 4-18 shows a differential double clock edge sampled S/H circuit based on the PP
structure S/H. The structure of the S/H shown in Figure 4-18 is equivalent to that of DET F/F.
However, the analog multiplexer of the S/H should linearly amplify the sampled signal without
limiting the output. Since the analog multiplexer shares the same structure of the mixer shown in
Figure 3-6, the linearity characteristics can be applied for the analog MUX.
Analog MUX
S/H
S/HData
CLK
Out
Figure 4-18 A ping-pong structure differential sample/hold circuit.
4.4.1.2 Quadrature VCO (QVCO)
As discussed in Chapter 3, a two-stage ring oscillator using a current-starved inverter or
shunt capacitor inverter can generate the quadrature clock signal. However, a LC QVCO has
been designed for the receiver to improve the phase noise of the carrier signal, as is the same
reason for that of the transmitter design. The proposed CDR loop is comparable to the quarter-
rate CDR of the NRZ signal. Typically, a quarter-rate CDR needs multi-phase clock signals for
the proper phase error estimation [32]. However, the proposed CDR for the HSRC-OQPSK
modulation uses quadrature-phase clock signals. Figure 4-19 shows the LC-QVCO structure [6].
A cross-coupled NMOS generates a negative resistance increasing the Q of LC tanks. The
113
outputs of one VCO, I+ and I-, are fed into the inputs of the other VCO, which generates
quadrature-phase outputs; Q+ and Q-. The Q+ and Q- are also fed into the inputs of the other
VCO. Detail analysis of the QVCO is found in [6].
Vb
I-
Q-
I+
c cQ+
Q-
I+
Q+
c cI-
Vc
Figure 4-19 LC quadrature VCO (LC-QVCO).
The Q of inductor is approximately 8 with a value of 3.9nH. A higher value inductor has
chosen to get a large voltage swing to provide a clock signal for the appropriate operation of the
S/H circuit. The varactor value of 730fF with a fixed MIM capacitor of 320fF is used. The
frequency of VCO is controlled by a voltage of node vc, which changes the capacitances of the
varactors.
Figure 4-20 shows simulated QVCO’s tuning range and its gain. The QVCO achieves a
tuning range of approximately 10% of the center frequency, 2.5GHz, and a maximum gain of
120MHz/V in the Cadence Spectre simulation. The VCO gain is relatively small, but a varactor
diode is chosen to get more linear tuning performance instead of using a MOS varactor. The
pull-in range is limited due to the small QVCO tuning range and its gain. However, the linear
tuning performance of the QVCO and low phase noise improve the system reliability as well as
114
reduce the jitter noise. The tail current of each NMOS is 2mA, therefore, each VCO stage
consumes 4mA. A voltage follower is used as an output buffer of the QVCO, which is not shown
in Figure 4-19. The phase noise of -117dBc/Hz at 1MHz offset is achieved in the Cadence
Spectre simulation.
-0. 2 0.0 0.2 0.4 0.6 0. 8 1 .0 1 .2 1 .4 1 .6
2 .42
2 .44
2 .46
2 .48
2 .50
2 .52
2 .54
2 .56
2 .58
2 .60
2 .62
Kvco=120MHz/V
Freq
uenc
y (G
Hz)
Contro l Voltage (V)
Figure 4-20 Simulated QVCO’s tuning range and its gain.
4.4.1.3 Voltage-to-current (V/I) converter
A simple differential input to single ended output V/I converter is designed which is
illustrated in Figure 4-21. The simulated current gain is approximately 180μA/V. A lead/lag
network as a loop filter is attached to the output node of the V/I converter. For more flexibility
to choose the loop filter, the VCO control line can be externally accessed. Therefore, the value of
the components of a loop filter can easily be replaced.
115
Vin+
bias
Vin-
Iout
Figure 4-21 A differential to single-ended V/I converter.
4.4.2 Circuit Simulations
Figure 4-22 shows the detailed receiver structure. A buffer is inserted as a delay unit to
compensate the delay between the mixer output and the clock signal of the PP S/H, DET F/F.
The I/Q mixer outputs are tied directly together for combining the signal and followed by a
differential to single-ended V/I converter. The lead/lag type loop filter is attached to the control
node of the VCO.
Signal in QVCO
DET F/F
PP S/H
DET F/F
PP S/H
90o
I
Q
Vc
IS
QS
IF
QF
CI
CQ
V/I Converter
wired
delaydelay
Input Buffer
I data
Q data CpCz
Rz
Figure 4-22 A detailed receiver architecture.
116
For the receiver simulation, the transmitter and the receiver are connected via a channel of
10cm transmission line with 50Ω characteristic impedance modeled with RLC elements. Figure
4-23 shows the simplified simulation setup.
CK
Data In
Transmitter
Signal Out D
Receiver
Channel 50O I
QQVCO
Rz
CzCp
CDR
Figure 4-23 Time-domain simulation setup with a HSRC-OQPSK transmitter and 10cm transmission line with characteristic impedance of 50Ω.
Since the output buffer of the Rev. 2 transmitter has been terminated with the on-chip
resistor, the external 50Ω pull-up resistor has been attached to the receiver input. Both the source
and the end termination structure can minimize the signal reflections; however, the power would
be increased to transfer the signal compared to the open-drain structure which is used in Rev.1’s
transmitter. As used in the behavioral model simulation, a LF with Rz=7KΩ, Cz=30pF and
Cp=2pF is attached to the VCO control node for the simulation purpose. To decrease the ripple of
the control voltage distorting the phase of VCO, a small value of a capacitor is added to the node
in parallel. A 2pF capacitor is attached for this reason, as shown in Figure 4-23. Note that this
would not much change the characteristics of the closed loop time and frequency responses [6].
However, the much lower loop bandwidth has been realized in actual design to avoid high
frequency jitter noise. The loop parameters are chosen to ensure zero of a loop transfer function
located at lower frequency than the closed loop pole. These values are Cp=12nF, Cz=150nF,
117
Rz=55Ω which are externally added to the test board. In this condition, the closed loop bandwidth
is approximately 200KHz and the phase margin is more than 60°.
Figure 4-24 shows the simulated phase error signal, e(t), which illustrates the locking
behavior of the CDR. As discussed in behavioral simulation, if the I/Q channels are perfectly
matched, there is no charge injection from the PD output when it is locking. However, a circuit’s
non-linearities make the I/Q mismatch which introduces high-frequency noises, that is, creates
the difference between behavioral and circuit simulations. From the result, the estimated locking
time of the CDR loop is approximately 500ns with the loop filter in Figure 4-24. The tuning
range of less than 50MHz is achieved by the simulation.
0.0 0.5 1 .0 1.5 2.0 2 .50 .70
0 .75
0 .80
0 .85
0 .90
0 .95
1 .00
Vcn
t (V
)
Time (us)
Figure 4-24 Simulation of the locking behavior of the proposed CDR loop.
Since the receiver has no multiplexer for serializing retimed I/Q data, the I/Q data of the
transmitter and the receiver are compared, as shown in Figure 4-25. The transmitted data are
118
recovered by a demodulation process in the receiver after approximate 1ns delay. Figure 4-25
shows the simulation results where the CDR locked the loop with the proper phase.
Transmitter Data Q Channel
Transmitter Data I Channel
Receiver Out Q Channel
Receiver Out I Channel
Figure 4-25 I/Q data of the transmitter and the receiver in the proper phase locked state.
As mentioned in the previous section, the HSRC-OQPSK CDR has a four-fold phase
ambiguity as is the case of the conventional OQPSK modulation. Therefore, the CDR loop may
be locked in four possible phase points. Since only one phase has the proper phase relationship,
the phase ambiguity should be resolved for the proper data acquisition. As discussed before, a
differential coding with loss of 3dB power efficiency or other methods can fix this problem [10],
[46]. Intuitively, it might be also resolved with training bits at the initializing steps of the
communication. However, this fourfold phase ambiguity issue is for future work which is
discussed in Chapter 5.
119
4.4.3 Layout
The prototype receiver is designed and fabricated in UMC 0.18μm CMOS technology.
Figure 4-26 show the layout structure of the HSRC-OQPSK receiver.
Varactors
Quadrature VCO
gndvbrev outQ+ outQ-
Din-
Din+
outI- outI+vbivbcp
osc+
osc-
vbvco lpfout vcnt
gnd
gnd
gnd
gnd
gnd
vdd
vdd
vdd
vboc
vbo
Demodulation with CDR
vdd
Varactors
Quadrature VCO
gndvbrev outQ+ outQ-
Din-
Din+
outI- outI+vbivbcp
osc+
osc-
vbvco lpfout vcnt
gnd
gnd
gnd
gnd
gnd
vdd
vdd
vdd
vboc
vbo
Demodulation with CDR
vdd
Figure 4-26 HSRC-OQPSK receiver chip fabricated with UMC 0.18μm CMOS technology.
Four inductors for the quadrature VCO (QVCO) occupy the most part of chip, varactors
are place in the center and the demodulation logics with CDR are placed on right side of the
chip. The power and ground ring is placed around the chip, which are not shown in the die photo
because the power and ground ring is metal5 layers. Input signal pads are placed close to the
demodulation logic. The chip has 26 pads including 8 differential signal inputs and outputs
which are operated up to 10Gbps, 11 power and ground, 5 biases, and VCO control outputs for
the external loop filter with the total chip size of 1185μm X 1260μm. The bypass capacitor for
the power and ground has been placed at the unused chip area with the value of more than 60pF.
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4.5 Measurement (Rev.2)
The same test of the transmitter’s has been used for the receiver. Figure 4-27 shows the test
board which is the same board as that of the transmitter’s. Bypass capacitor of approximately
100μF are attached between the power and the ground. The I and Q channel outputs are to be
connected to the external 2:1 mux for the BER test. VCO outputs are for monitoring the locked-
state of the CDR loop and the recovered clock signal.
Figure 4-27 Receiver test board.
Figure 4-28(a), (b) show the simplified 2.5Gbps and 10Gbps receiver measurement setups,
respectively. The signals are depicted with a single signal line for the simplification while the
actual signals are differential. Since it is not easy to estimate the receiver’s performance with a
conventional signal generator because the proposed HSRC-OQPSK signal is different from the
conventional NRZ signal, the HSRC-QOPSK receiver incorporated with the proposed CDR
requires HSRC-QOPSK modulated signal to evaluate the receiver’s performance. Therefore, the
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HSRC-OQPSK transmitter output is connected to the receiver input via a channel as shown in
Figure 4-28.
A 2.5GHz VCO signal output of the transmitter is fed into the external clock input of the
Agilent 4093A BERT for the 2.5Gbps BER test. An external 2:1 mux (Inphi 20709SE) operating
up to 20Gbps is located at the receiver output for serializing the I and Q channel data. The
serialized data is fed back into the BERT for the BER performance test of the receiver.
CK
Data In
Transmitter
Signal Out
2.5GHz VCO Signal
Signal Generator
VCO OutExternalClock In
5GHz Clock
2.5Gbps
Data In
BERT
D
Receiver
Channel 50ohm IData
QData
2:1 MUX (external)
Phase Shifter
(a)
BERT
CK
Data In
Transmitter
Signal Out1/2 sub clock
10Gbps
Data In
D
Receiver
Channel 50ohm IData
QData
2:1 MUX (external)
Phase Shifter
Phase Shifter
(b)
Figure 4-28 Simplified receiver (transceiver) measurement setups (a) for 2.5Gbps input (equivalent data-rate of 5Gbps), (b) for 10Gbps data-rate.
Figure 4-29 shows the phase noise performance of the VCO. The red line in Figure 4-24
represents the phase noise of the receiver’s VCO signal in locked-state. The phase noise of the
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recovered clock is approximately -87dBc/Hz at 50KHz offset. The 2.43Gbps random data has
been fed into the transmitter to generate the HSRC-OQPSK signal which is the source signal of
the receiver. The measured tracking range of the CDR is approximately 30MHz.
10K 100K 1M-120
-110
-100
-90
-80
-70
-60
-50
-40
Offset Frequency (Hz)
Pha
se N
oise
(dB
c)free-runninglocking
Figure 4-29 Phase noise performance of the receiver’s VCO in free-running and locking states.
Figure 4-30 illustrates the measured jitter of the recovered clock in response to 2.43Gbps
PRBS sequence of 231-1. Since the modulated signal cannot be generated by BERT, the
transmitter outputs which generate the HSRC-OQPSK signal are connected to the receiver’s
inputs for the measurement. The measured rms jitter and the peak-to-peak jitter of the recovered
clock by the CDR loop are equivalent to 6.5ps and 39.9ps respectively.
Figure 4-31 shows the recovered I or Q channel data output when the 231-1 PRBS input has
been used. As shown in Figure 4-23, the BER test has been performed using 2.5Gbps and
10Gbps test setups, respectively with three different ( 5”, 10”, 20” ) FR-4 PCB channels and a
19” SATA cable. From the measurement results, BER of < 10-9 have been achieved up to 10”
PCB channel and a SATA cable where 2.43Gbps 231-1 PRBS is used while BER of 10-4 is
123
achieved where a 20” PCB channel is used. However, the BER of <10-9 has been achieved where
2.43Gbps 27-1 PRBS is used. The power consumption of the receiver core is approximately
130mW from a 1.8V supply excluding power consumptions of the output buffers for the I and Q
channel data, which is driving the input of the external 2:1 mux for serializing the data and
output buffer of the VCO for the purpose of monitoring.
50mV/div
10ps/div
p-p jitter
50mV/div
10ps/div
p-p jitter
Figure 4-30 Measured jitter of recovered clock in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1).
100mV/div
100ps/div
100mV/div
100ps/div
Figure 4-30 Recovered I (or Q) channel eye-diagrams in response to 4.86Gbps (both I and Q channel input with 2.43Gbps PRBS sequence of 231-1).
124
Unfortunately, it has been failed to evaluate the performance of the receiver at 9.72Gbps
because there are no reasonable BER performance and recovered eye-diagrams from the
measurement. One of the main reason of the failure in recovering the 9.72Gbps data is that the
transmitted signal generated from the transmitter does not have enough energy in a peak signal
which has the signal energy of Es,p analyzed in Chapter 2. Eye-opening mismatches in the
transmitted data-rate of 9.72Gbps eye-diagram shown in Figure 3-27(a) caused a slight
synchronization mismatch between the clock and the data and it might affect the performance of
the receiver. Another reason for failure in recovering data might be from the CDR performance
of the receiver. However, it is hard to evaluate the CDR performance itself without the HSRC-
QOPSK modulated signal because there is no equipment that generates the ideal 10Gbps HSRC-
QOPSK signal. Although it has failed to recover 9.72Gbps transmitted data at the receiver which
is originally designed for recovering up to 10Gbps transmitted data, we could get a much
improved system performance if the low-noise and the broadband circuit design are considered
to design the transceiver. And frequency compensation techniques, such as a pre-emphasis of the
signal at the transmitter or the equalizing signal at the receiver-end using filter will also greatly
help in increasing the performance of the transceiver. However, these are put to future work.
Table 4-1 summarizes the performance of the receiver.
Table 4-1 Transceiver (Rev.2) performance summary Data Rate 4.86Gbps (2.43Gb/s I/Q input)
@ sequence of 231-1 < 10-9 @ up to 10” PCB channel and 19” SATA cable < 10-4 @ 20” PCB channel
BER Performance @ 4.86Gb/s PRBS input (2.43Gb/s PRBS I/Q input) @27-1
< 10-9 @ 20” PCB channel Phase Noise (recovered clock) -87dBc @ 50KHz offset
125
Table 4-1 (continued)
Recovered clock jitter 6.5ps (rms), 39.9ps (p -p) @ 2.43Gbps PRBS of 231-1
CDR tracking range 30MHz (Loop Bandwidth ≈ 200KHz)
Power consumption Tx + Rx : 200mW @ 1.8V
Die Size Tx: 1130 x 1240μm2 Rx: 1185 x 1260μm2
Technology UMC 0.18μm CMOS
4.6 Summary
This chapter proposed a HSRC-OQPSK receiver incorporated with a new CDR loop, and
demonstrated its viability of increasing the data-rate in high-speed serial link system by using the
HSRC-OQPSK modulation. The proposed receiver has been designed with UMC 0.18μm CMOS
technology and the analysis has been compared with the simulation results. From the simulation
results, the time domain signals and the spectrum of the HSRC-OQPSK modulation fit well with
theoretical analyses.
This paper also proposed a CDR based on the Costas loop for the HSRC-OQPSK
modulation. The proposed CDR is comparable to a quarter-rate CDR of NRZ modulation
because it uses quarter data-rate frequency clock. Therefore, the proposed CDR can improve the
timing constraints of the receiver’s clock and data recovery. The CDR incorporated with the
receiver is simulated and compared to the analytical results. Moreover, the CDR uses a QVCO
instead of multi-phase VCO which is applied to a conventional quarter-rate CDR hence it offers
a simple receiver structure. The circuit simulation results of the phase error and the locking
behavior relatively fit well with the behavioral model simulation. In addition, the proposed CDR,
characterized as a linear PD, can lower the jitter noise [44-45].
The HSRC-OQPSK transceiver can easily be implemented with a low-voltage technology
due to the reason that it uses two level data decision while a multi-PAM (e.g., 4-PAM) system [3]
126
needs reference voltages and the level spacing which is difficult to maintain linear levels in a
low-voltage system for data decisions. Moreover, this allows a simple transceiver architecture.
The measurement results show the feasibility of using the HSRC-OQPSK as a modulation
technique offering a simple transceiver architecture for the high-speed wire-line
communications, such as a serial link. Moreover, the HSRC-OQPSK modulation and the
receiver can enable a serial link system to achieve higher data-rate without aiding a reference
clock in low-voltage wire-line communication systems.
127
CHAPTER 5 SUMMARY AND SUGGESTIONS FOR FUTURE WORK
5.1 Summary
The HSRC-PSK modulations are proposed to optimize spectral efficiency for high data-
rate transmission over band-limited channels. The analysis and simulation results show that the
proposed modulations can be used in high-speed data communications, such as a backplane
serial link.
In the past, a multi-PAM signal (e.g., 4-PAM) has been demonstrated to increase the data-
rate in band-limited channels [3]. However in 4-PAM modulation, it is difficult to maintain the
linear spacing between levels in low-voltage and low-power application and as a result the
system’s performances are degraded. The level spacing also causes complexity in the transceiver
design not only because the received signal needs to be linearly amplified but also because 4-
PAM signaling requires accurate reference voltages.
The proposed HSRC modulations not only reduced the bandwidth requirement but also can
be easily implemented in deep submicron integrated circuit technologies with low supply
voltages. Three HSRC-PSK modulations named HSRC-QPSK, HSRC-OQPSK, and HSRC-
MSK are introduced and analyzed in terms of their spectrums and BER performances.
The HSRC-QPSK modulation can reduce the required bandwidth without any BER
performance degradation compared to the NRZ modulation. However, it is hard to implement a
HSRC-QPSK demodulator with a conventional circuit technique due to the difficulty in realizing
a matched filter in GHz range. The demodulation method for HSRC-QPSK is still under
investigation.
The HSRC-MSK modulation can minimize crosstalk noise compared to the conventional
ones, since the high frequency components are maximally suppressed [14] among the introduced
128
three quadrature HSRC-PSK modulations. However, it does not help to reduce the required
bandwidth of the transmitted signal because the first null bandwidth is the same as that of the
NRZ modulation.
The HSRC-OQPSK modulation has been chosen as a feasible modulation technique which
can be used in high-speed wire-line data communications. A prototype HSRC-OQPSK
transmitter has been designed with discrete components to verify the theory. Measurement
results confirmed that the proposed modulations can be effectively used in band-limited wire-line
applications requiring spectral efficiency, such as the backplane serial link. Moreover, because it
requires only a two-level decision, the HSRC-OQPSK transmitter can be implemented in a
simpler architecture than 4-PAM and is suitable for low-voltage systems. The HSRC-OQPSK
spectrum, which is the same as the MSK spectrum, contains 99% of the total signal power within
the bandwidth of B ≈ (1.2/Tb). In comparison, 4-PAM which has the same signal spectrum as
that of QPSK has a much larger 99% bandwidth of B ≈ (8/Tb) [13]. Therefore, it is expected that
the proposed HSRC-OQPSK modulation should have an efficient signal spectrum in band-
limited channels and also this spectrum efficiency will reduce the high frequency crosstalk noise
between the signal lines which may improve the performance of the multi-port serial
communication links.
Moreover, a fully reference-less serial link transceiver using the HSRC-OQPSK
modulation has been proposed and demonstrated its viability of increasing data-rate in high-
speed serial link system. The proposed transceiver has been designed with UMC 0.18μm CMOS
technology and the analysis has been compared with the simulation results. From the simulation
results, the time domain signals and the spectrum of the HSRC-OQPSK modulation fit well with
the theoretical analyses.
129
A QPSK carrier recovery loop can be used for the propoed HSRC modulations which
enables flexible design of the receiver. A new CDR loop for the HSRC-OQPSK based on the
polarity-type Costas loop has been proposed and implemented by the UMC 0.18μm CMOS
technology. This paper also proposed a CDR based on the Costas loop for the HSRC-OQPSK
modulation. The proposed CDR is comparable to a 1quarter-rate CDR of the NRZ modulation
because it uses a quarter data-rate frequency clock. Therefore, the proposed CDR can improve
timing constraints of the receiver’s clock and data recovery. Moreover, the HSRC-OQPSK
allows a simple transceiver architecture which can easily be implemented with a low-voltage
technology due to the reason that it uses two-level data decision while a multi-PAM (e.g., PAM-
4) system [3] needs reference voltages and the level spacing which is difficult to maintain linear
levels in a low-voltage system for data decisions. Table 5-1 summarizes and compares the
characteristics of the conventional modulations and the proposed HSRC-OQPSK modulation.
Table 5-1 Performance comparison of the different modulations.
PAM-2 (NRZ) PAM-4 Duobinary HSRC-
OQPSK
Main lobe bandwidth (first null) 1/Tb 1/2Tb 1/2Tb 3/4Tb Transmitted
Signal Spectrum Difference between
main and second lobe 13dB 13dB 13dB 23dB
1CDR Clock Frequency Full Rate Half Rate Full Rate Quarter Rate
# of Level 2 4 3 2
Decision Threshold 1 3 2 1 Data Decision
Decision Interval Tb 2Tb Tb 2Tb
1 Half and quarter data rate CDR has been developed for the PAM signaling [32], [51].
130
The results show that the HSRC-OQPSK modulation and the transceiver can enable a
serial link system to achieve a higher data-rate without aiding a reference clock in low-voltage
wire-line communication systems.
5.2 Four-fold Ambiguity Issue
As mentioned in Chapter 4, the proposed CDR based on the Costas loop has a fourfold
ambiguity problem. Only one out of the four stable locking points has proper phase information.
The differentially encoded data can resolve this four-fold ambiguity problem with 3dB signal to
noise ratio (SNR) degradation [10]. A transmitter with differentially encoded data input can be
implemented using a XOR gate and a F/F, as shown in Figure 5-1. It is essential for the
architecture of Figure 5-1(a) to have a parallel-to-serial logic which is implemented with a 2:1
multiplexer in the receiver. The alternative architecture decoding the data in the receiver without
using a 2:1 multiplexer is shown in Figure 5-1(b). The I and Q channels of the receiver generate
the demodulated data which are offset with one bit-time, Tb, offset, hence, the architecture shown
in Figure 5-1(b) can also be used to decode the modulated data.
HSRC-OQPSK TransmitterD Q
CK
HSRC-OQPSK Receiver
(include 2:1 multiplxer with I/Q inputs)
Data In
Data Out
CK
Q D
Transceiver 1
Channel
Transceiver 2
(a)
Figure 5-1 A differentially coded HSRC-OQPSK transceiver architecture to resolve the fourfold ambiguity issue (a) the receiver includes a 2:1 multiplexer for serializing I/Q channel data (b) alternative architecture without using a multiplexer.
131
HSRC-OQPSK TransmitterD Q
CK
HSRC-OQPSK Receiver
Data In
Data OutCK
Q D
Transceiver 1
Channel
Transceiver 2
I
Q
(b)
Figure 5-1 (continued).
Another approach to resolve the fourfold ambiguity issue is synchronization at the protocol
layer. Every serial data link communications – almost all data communications – needs
synchronization, that is initialization of the data communications. Bits are sent out to the channel
from the least-significant bit (LSB) to the most-significant bit (MSB). All packets start with a
synchronization (SYNC) field, which is coded for the maximum edge transition rate. It is used
by CDR to recover the clock and data synchronization. A SYNC filed is defined to be eight bits
in length for full/low speed and 32 bits for high speed in the USB specification 2.0 [52] as an
example. Packet identifier (PID) follows the SYNC field. The USB specification 2.0 protocol
detail is presented in [52].
The protocol detail is not discussed in this chapter; however, a conceptual resolution of
the fourfold ambiguity by using a SYNC field. As described before, the SYNC field is coded to
make maximum edge transition in order to give more gain to the circuitry which aligns the
incoming data. However, the HSRC-OQPSK should have different SYNC to maximize edge
transition because it uses a carrier for the modulation. The carrier signal transforms the original
132
transmitted data sequences. To make it simple, assume the SYNC field is eight bit as is the case
for full/low speed of USB specification 2.0 and the SYNC field of the initial transmitter of
‘10010110’ has the maximum edge transition.
The data is split into I and Q channel ‘1001’ and ‘0110’ for the transmitter. After
demodulated at the receiver, four possible data sequences exist on the I and Q channel. When the
CDR locks the loop with a proper locking phase, the data sequences are the same as the
transmitted ones which are ‘1001’ and ‘0110’ for the I and Q channels of the receiver,
respectively. If the loop is locked with ±90° phase offset, one of the I/Q channels would recover
the transmitted data reversely from the original data which are ‘0110’, ‘0110’ or ‘1001’, ‘1001’.
Both the I/Q data are inverted –‘0110’ and ‘1001’– on condition that the CDR loop is locked
with the 180° phase offset. With these four possible SYNC fields at the receiver, we can estimate
at which phase the CDR loop is locked. Figure 5-2 shows the conceptual four-fold ambiguity
resolution method using a SYNC field.
D Q
CKB
HSRC-OQPSK Receiver
I
Q
D Q
CK
D Q
D Q
D Q
D Q
D Q
D Q
4
4
I Data Out
Q Data Out
Logical Operation(Control signals generate
logical 1 if the SYNC of I/Q is inverted from expected value, otherwise logical 0)
I Control
Q Control
Figure 5-2 An example of a conceptual architecture for resolving four-fold ambiguity issue using eight bits SYNC field.
133
LIST OF REFERENCES
[1] A. B. Carson, P. B. Crilly, and Janet C. Rutledge, Communication Systems, New York: McGraw-Hill, 2001, ch.11.
[2] G. Lawday, “On the buses” IEE Review, pp. 44-47, Jan. 2004.
[3] R. Farjad-Rad, C.-K. Ken Yang, M. A. Horowitz, and T. H. Lee, “A 0.3-µm CMOS 8-Gb/s 4-PAM serial link transceiver,” IEEE Journal of Solid-State Circuits, vol. 35, no.5 pp. 757-764, May 2000.
[4] J. T. Stonick, G.-Y. Wei Yang, J. L. Sonntag, and D. K. Weinlader, “An adaptive PAM-4 5Gb/s backplane transceiver in 0.25μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 38, no.3 pp. 436-443, Mar. 2003.
[5] R. Farjad-Rad, “A CMOS 4-PAM Multi-Gbps Serial Link Transceiver,” Ph.D. dissertation, Dept. Elct. Eng., Stanford Univ., Stanford, CA, 2000.
[6] B. Razavi, Design of Integrated Circuits for Optical Communications, McGraw-Hill, 2003.
[7] P. Kabal, S. Pasupathy “Partial-response signaling,” IEEE Transactions on Communications, vol. 23, no. 9, pp. 921-934, Sep. 1975.
[8] M. Horowitz, C.-K. K. Yang, and S. Sidiropoulos, “High-speed electrical signaling: overview and limitations,” IEEE Micro, pp. 12-24, Jan. 1998.
[9] J. H. Sinsky, M. Duelk, and A. Adamiecki, “High-speed electrical backplane transmission using duobinary signaling,” IEEE Transaction on Microwave Theory and Techniques, vol. 53, no.1, pp. 152-160, Jan. 2005.
[10] J. G. Proakis, Digital Communications, New York: McGraw-Hill, 1995.
[11] D. R. Smith, Digital Transmission Systems, New York: Van Nostrand Reinhold, 1985, ch. 6.
[12] T. S. Rappaport, Wireless Communications, NJ: Upper Saddle River, Prentice Hall, 1996, ch. 5.
[13] S. Pasupathy, “Minimum shift keying: a spectrally efficient modulation,” IEEE Communications Magazine, pp. 14-22, July 1979.
[14] R. Bashirullah, W. Liu, and R. Cavin, “Cross-talk reduction for interconnect-limited bus based on raised cosine signaling,” Proceeding of 2002 CICC, pp. 513-516
[15] S. A. Gronemeyer, and A. L. McBride, “MSK and offset QPSK modulation,” IEEE Transactions on Communications, vol. 24, no. 8, pp. 809-820, Jul. 1976.
134
[16] T. J. Gabara and W. C. Fischer, “Capacitive coupling and quantized feedback applied to conventional CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 419-427, Mar. 1997.
[17] L. Luo, J. M. Wilson, S. E. Mick, J. Xu, L. Zhang, and P. D. Franzon, “3Gb/s AC coupled chip-to-chip communication using a low swing pulse receiver,” IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 287-296, Jan. 2006.
[18] Part3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specification, IEEE Standards 802.3-2002.
[19] J. Yoon, and W. Eisenstadt, “Lumped passive circuit for 5GHz embedded test of RF SoCs,” IEEE ISCAS, pp. 1241-1244, May 2004.
[20] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd, MA: Cambridge University Press, 1998, ch. 18.
[21] B. Razavi, RF Microelctronics, NJ: Upper Saddle River, Prentice Hall PTR, 1997, ch. 5.
[22] P. Heydari, “Design and analysis low-voltage current-mode logic buffers,” Proceedings of 4th ISQED03, pp. 293-298, 2003.
[23] B. Razavi, Design of Analog CMOS Integrated Circuits, New York: McGraw-Hill, 2003.
[24] P. Heydari, and R. Mohanavelu, “Design of ultrahigh-speed low-voltage CMOS CML buffres and latches,” IEEE Transactions on VLSI Systems, vol. 12, No.10, pp. 1081-1093, Oct. 2004.
[25] M. G. Johnson, and E. L. Hudson, “A variable delay line PLL for CPU-coprocessor synchronization,” IEEE Journal of Solid-State Circuits, vol. 23, no.5 pp. 1218-1223, Mar. 1988.
[26] A. Mazzanti, P. Uggetti, and F. Svelto, “Analysis and design of LC dividers for quadrature generation,” IEEE Journal of Solid-State Circuits. vol.39, no.9, pp.1425-1433, Sep. 2004
[27] H. Johnson, and M. Graham, High-Speed Digital Design, 1st, Prentice Hall PTR, 1993.
[28] S. Galal, and B. Razavi, “10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 38, no.12, pp. 2138-2146, Dec. 2003.
[29] Affirma Spectre Circuit Simulator User Guide, Cadence Design Systems Inc., San Jose, CA, 2000.
[30] A. Adamiecki, M. Duelk, and J. H. Sinsky, “25Gbit/s electrical duobinary transmission over FR-4 backplanes,” IEE Electronics Letters, vol. 41, no.14, pp. 826-827, Jul. 2005.
135
[31] K. Yamaguchi, K. Sunaga, S. Kaerlyama, T. Nedachi, M. Takamiya, K. Nose, Y. Nakagawa, M. Sugawara, and M. Fukaishi, “12Gb/s Duobinary signaling with x2 oversampled edge equalization,” ISSCC 2005 IEEE International, pp. 584-585
[32] J. Lee and B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18um CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 38, no.12, pp. 2181~2190, Dec. 2003
[33] H. C. Osborne, “A generalized “polity-type” Costas loop for tracking MPSK signals,” IEEE Transactions on Communications, vol. 30, no. 10, pp. 2289-2296, Oct. 1982.
[34] M. K. Simon, “Tracking performance of Costas loop with hard-limited in-phase channel,” IEEE Transactions on Communications, vol. 26, no.4, pp. 420-432, Apr. 1978.
[35] J. P. Costas, “Synchronous communications,” Proceedings of the IRE, vol. 44, no.12, pp. 1713-1718, Dec. 1956.
[36] W. C. Lindsey and M. K. Simon, “Carrier synchronization and detection of polyphase signals,” IEEE Transactions on Communications, vol. 20, no.3, pp. 441-454, Jun. 1972.
[37] A. Leclert, and P. Vandamme, “Universal carrier recovery loop for QASK and PSK signal sets,” IEEE Transactions on Communications, vol. 31, no.1, pp. 130-136, Jan. 1983.
[38] M. K. Simon and J. G. Smith, “Carrier synchronization and detection of QASK signal sets,” IEEE Transactions on Communications, vol. 20, no.2, pp. 98-106, Feb. 1974.
[39] M. K. Simon, “On the optimality of the MAP estimation loop for carrier phase tracking BPSK and QPSK signals,” IEEE Transactions on Communications, vol. 27, no. 1, pp. 158-165, Jan. 1979.
[40] C. L. Weber, and W. K. Alem, “Demod-remod coherent tracking receiver for QPSK and SQPSK,” IEEE Transactions on Communications, vol. 28, no. 12, pp. 1945-1954, Dec. 1980.
[41] C. L. Weber, and W. K. Alem, “Performance analysis of demod-remod coherent receiver for QPSK and SQPSK input,” IEEE Transactions on Communications, vol. 28, no. 12, pp. 1954-1968, Dec. 1980.
[42] R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, New York: McGraw-Hill, 2003, ch. 9.
[43] H. Yeo, Y. Lee, J. Chen, and J. Lin, “Half-symbol-rate-carrier offset QPSK transmitter for bandwidth-efficient high-speed data communications,” IEEE Microwave and Wireless Components Letters, vol. 17, no. 6, pp. 466-468, June 2007.
[44] S. B. Anand, and B. Razavi, “A CMOS clock recovery circuit for 2.5Gb/s NRZ data,” IEEE Journal of Solid-State Circuits, vol. 36, no.3, pp. 432-439, Mar. 2001.
136
[45] C. R. Hoggie, “A self correcting clock recovery circuit,” IEEE Journal of Lightwave Technology, vol. 3, no. 6, pp. 1312-1314, Dec. 1985
[46] E. R. Cacciamani. and C. J. Wolejsza, Jr. “Phase ambiguity resolution in a four-phase PSK communications system,” IEEE Transactions on Communication Technology, vol. 19, no.6, pp. 1200-1210, Dec. 1971.
[47] B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, NJ: Piscataway, IEEE Press, 1996.
[48] F. M. Gardner, “Charge-pump phase locked loops,” IEEE Transactions on Communications, vol. 28, no.11, pp. 1849-1858, Nov. 1980.
[49] C.-K. Ken Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick, “A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no.11, pp. 1684-1691, Dec. 2001.
[50] M. H. Shakiba, D. A. Johns, and K. W. Martin, “BiCMOS circuits for analog Viterbi decoders,” IEEE Transactions on Circuits and Systems, vol. 45, no.12, pp. 1527-1537, Dec. 1998.
[51] J. Savoj, and B. Razavi, “10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector,” IEEE Journal of Solid-State Circuits, vol. 38, no.1, pp. 13-21, Jan. 2003.
[52] Universal Serial Bus Specifications, revision 2.0, Apr.. 2000.
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BIOGRAPHICAL SKETCH
Hyeopgoo Yeo was born in Seoul, Korea, in 1968. He received his B.S. and M.S. degrees
in electronic engineering from Yonsei University, Seoul, Korea, in 1991 and 1993, respectively.
He also received his M.S. degree in electrical and computer engineering from the University of
Florida, Gainesville, USA, in 2003.
From 1993 to 1999, he worked as a design engineer at Samsung Electronic Co. Ltd.,
Kihung, Kyounggi-do, Korea, where he performed CMOS ASIC cell library design and
development.
He is currently pursuing his Ph.D. degree as a graduate research assistant at the University
of Florida. His research interests involve RF/analog circuit design, high-speed digital systems.
He is particularly interested in high-speed serial links.
