Design of Integrated-Circuit Interconnects with AccurateModeling of Chemical-Mechanical Planarization

Lei He, Andrew B. Kahng*, Kingho Tam, Jinjun Xiong

EE Department, University of California, Los Angeles

*ECE Department, University of California, San Diego

SPIE-2005, San Jose, March 3, 2004

CMP and Fill

Dishing and erosion require dummy fill insertion for metal density and CMP uniformity

Fill Design Rules

Lower and upper bounds on fill dimensions Minimum fill spacing rules

– Between fills– Between fill and functional feature

Crude “coverage” bounds (e.g., between 30-70% density)– Saddle point of weak filling rules and weak filling tools

W

WS l u

l

W w W

S s

Fill Pattern

Fill pattern inserted between “active” interconnects– Blue: active interconnect– Gray: dummy fill

Subset of potential fill patterns:– Rectangular shapes– Isothetic (aligned with axes)

Characterized by:– Number of rows (M=5)– Number of columns (N=3)– Series of widths (W)– Series of lengths (L)– Series of horizontal spacings (Sx)– Series of vertical spacings (Sy)

W1

L1

W2 W3

L2

L3

L4

L5

Sx,1 Sx,2

Sy,1

Sy,2

Sy,3

Sy,4

XY B

M=5, N=3

Fixed-Dissection Fill Synthesis

Fixed set of w w windows, each partitioned into r2 tiles

– n n layout has nr/w nr/w overlapping fixed dissections

Find the amount of fill within each tile such as to:

– Minimize window density variation [Kahng et. al., TCAD’02]

– Minimize total amount of added fill [Wong et. al., DAC’00]

w/r

Overlapping windows

w

n

tile

How Are They Related?

Local Metal Density– Proportion of area occupied by fill between active

interconnects Effective Metal Density

– Proportion of area occupied by metal features (interconnect + fill) within planarization window (tile)

Linkage– Fixed dissection fill synthesis -> – Amount of metal within each tile ->– Amount of fills between active interconnects within the tile

Cu

f

Performance-Driven Fill (DAC-2003)

Dummy fill increases capacitance, delay, crosstalk Insert fill where layout and timing can best tolerate it

Full solution: Timing path driven, multi-layer aware

This work addresses: How much can the fill pattern matter?

Driving Questions

How much does fill affect coupling and total capacitance? How much do dishing and erosion affect interconnect

performance? What QOR loss is incurred by CMP-oblivious interconnect

design?

Where this is leading:– CMP-aware fill pattern synthesis

– CMP-aware fill and interconnect synthesis

– CMP-and fill-aware routing CMP modeling drives performance analysis, layout signoff

Outline

Introduction and study goals Impact of fill insertion and fill patterns Impact of dishing/erosion on RC parasitics Impact on interconnect design Conclusions Note: This talk = outline of methodology and

analysis framework to drive full-chip place/route

Fill Pattern Concerns

How much can fill patterns affect interconnect cap? What is the range of capacitance impact across

“equivalent” fill patterns?– “Equivalence” is with respect to multi-layer CMP

modeling, per-feature defocus budgeting, etc.

A B A B A B BA

M=5, N=3 M=4, N=3 M=6, N=3 M=5, N=5

Distribution Characteristic Function

Given a total budget (e.g., width, length, spacing), distribute the budget to a given series (e.g., widths) via a Distribution Characteristic Function– Uniform– Linear increasing– Linear decreasing– Convex triangular

Z

f(z)

Z Z

f(z) f(z)

(1) (2) (4)

Z

f(z)

(3)

DCF for Fill Pattern Exploration

Different DCF combinations for width, length, and spacing series result in different fill patterns

Facilitates systematic exploration of wide range of fill patterns– Enumeration is infeasible– Runtime and flexibility of capacitance extraction are

another limit

A B A B A B BA

M=5, N=3 M=4, N=3 M=6, N=3 M=5, N=5

Simulation Experiments: Setup

Interconnect models: Stripline (G-M-G) Global interconnects at 65nm

– Local metal density: 0.1~0.7 – Spacing (s) = (3-10) x minimum spacing (0.24um) – Width (w) = minimum width (0.24um)– Length (l) = 1000um– Metal thickness (0.50um)– ILD thickness (0.45um)

Three types of DCF for fill pattern exploration– Uniform– Linear increasing – Linear decreasing

All fills are floating QuickCap employed for capacitance extraction

Distribution of Coupling Capacitance

Local metal density = 0.3 Blue: nominal Cc without fill insertion Red: Cc with different fill patterns (min – mean – max)

Distribution of Coupling Capacitance

For each interconnect configuration– Different fill patterns-> different Cc– Fill always increases Cc:

• 25%-300%

– Metal spacing increases ->the relative change of Cc increases

• Under same local metal density

– Local metal density increases-> more significant increasing of Cc

Distribution of Total Capacitance

Similar observations hold for Cs Relative change of Cs is less

dramatic than that of Cc Still, more than 10% relative

change compared to the nominal case

Coupling Cap V.S. Total Cap

Local metal densities: 0.1 ~ 0.7 Minimum (blue) or maximum (red) Cc over Cs among all fill

patterns studied. Nominal Cc/Cs is shown in the title

Coupling Cap V.S. Total Cap

Fill always increases Cc/Cs – The gap (maximum –

minimum) = potential variation due to fill insertion

Metal spacing increases -> Cc/Cs is also increasing

Local metal density increases -> Cc/Cs is also increasing

However: Cc/Cs < 20% in our studies

Mini-Conclusion on Fill Insertion and Fill Pattern

Fill insertion can dramatically increase Cc and Cs over their respective nominal values

– Cc 25%~300%, Cs ~10%

Cc and Cs varies significantly across different fill patterns– Relative change is more prominent for Cc than for Cs

Therefore, to obtain robust designs that will meet requirements (e.g., delay and parametric yield) after fill insertion, the variation (increase) of both Cc and Cs must be considered by the design flow.

Outline

Introduction and study goals Impact of fill insertion and fill patterns Impact of dishing/erosion on RC parasitics Impact on interconnect design Conclusions

Multi-step CMP Process Modeling

Three steps = three pads CMP process– Step 1: eliminates all local step heights, and irrelevant to the

modeling of dishing and erosion.– Step 2: removes copper above trench, no dishing and erosion

at the moment when pad reaches the barrier– Step 3: simultaneous oxide/copper polishing– Details see [Gbondo-Tugbawa Ph.D. Thesis 2002]

Step 2: After Pad Reaches Barrier

Dishing (d) and Erosion (E)– Process-dependent constants are taken from [Gbondo-Tugbawa

Ph.D. Thesis 2002]

Step 3: Simultaneous Oxide/Copper Polishing

Much Complicated– Details see the paper– Or [Gbondo-Tugbawa Ph.D. Thesis 2002]

Impact on Global Interconnect Resistance

Rf due to dishing/erosion is large: 28.7%~31.7%–Reduced cross-section

As width (w) grows, variation also increases Spacing has little impact, as effective metal density is

enforced

Width w

(μm)

Spacing

(μm)

Nominal Ro

(kΩ)

Real Rf

(kΩ)

0.24 0.95 18.6 23.9 (+28.7%)

2.61 0.95 16.9 22.1 (+30.6%)

4.75 0.95 9.29 12.3 (+31.4%)

0.24 0.95 18.6 23.9 (+28.8%)

2.61 0.95 16.9 22.1 (+30.9%)

4.75 0.95 9.29 12.2 (+31.7%)

Impact on Global Interconnect Capacitance

Three scenarios:– S1: Interconnect with nominal value– S2: Interconnect affected by dishing/erosion, WITHOUT fill insertion– S3: Interconnect affected by dishing/erosion, WITH fill insertion

Dishing and erosion have comparatively smaller impact on capacitance

The fact of fill insertion itself has much larger impact on capacitance

W S

S1: NO CMP

S2: Dishing/ErosionS3:

Fill+Dishing/Erosion

Cc Cs Cc Cs Cc Cs

0.24 0.95 6.99 79.466.80

(-2.63%)

79.20

(-0.33%)

9.30

(33.06%)

79.38

(-0.11%)

2.61 0.95 7.24 268.566.96

(-3.78%)

268.05

(-0.19%)

9.14

(26.33%)

264.92

(-1.35%)

4.75 0.95 7.01 433.297.22

(2.97%)

436.25

(0.68%)

8.87

(26.51%)

432.29

(-0.23%)

Mini-Conclusion on Dishing/Erosion Impact

Dishing and erosion significantly increase interconnect resistance

Dishing and erosion impact on capacitance is ignorable– Is this really the case? – Any such assessment is design- and methodology-

dependent

Fill insertion has much larger impact than dishing/erosion on capacitance

Outline

Introduction and study goals Impact of fill insertion and fill patterns Impact of dishing/erosion on RC parasitics Impact on interconnect design Conclusions

CMP-aware RC Model

Tabulate the extracted capacitance – (active interconnect width, spacing, local metal density)

Capacitance table only saves the capacitance under the best (worst) fill pattern– Best = minimum Cc

– Worst = maximum Cc Resistance calculated from multi-step CMP model CMP-aware RC Model

– Fill insertion + Dishing & Erosion CMP-oblivious RC Model

– Nominal geometry only

Interconnect Design Concerns

How do CMP effects change conventional CMP-oblivious interconnect design ?

How do we take CMP effects into account for a better CMP-aware design flow?

Experiment Setup

Interconnect design for WIDE parallel bus– Four parallel, capacitively-coupled wires– Minimum # of elements, yet captures the “worst" case coupling effects

Goal: minimize “unit length delay” (DL)– Vary buffer size (S) and interconnect length (L) between buffers

Experiment Results Under Best-Fill

CMP-oblivious design– Post “best-fill” insertion– Best “possible” practice for FAIR comparison

CMP-aware designs always result in smaller unit length delay – Relative improvement up to 3.3%– Improvement decreases as effective metal density increases

• Diminishing amount of erosion -> Reduced resistance Buffer area measured by S/L

– CMP-aware design increases S/L by 14.8%

LocalDen.

Eff. Den

CMP-oblivious CMP-aware

L S D L S S/L% D D%

0.5 0.3 2137 310 21.6 1862 310 +14.8 20.8 -3.3

0.5 0.5 2137 310 20.7 1962 310 +8.9 20.2 -2.4

0.5 0.7 2137 310 20.2 1962 310 +8.9 19.8 -2.2

Experiment Results Under Worst-Fill

Post worst-fill insertion: CMP-aware designs still result in smaller unit length delay – Relative improvement up to 3.5%

Post best-fill insertion: CMP-aware design not necessary better Therefore, no single design that is CMP-variation optimal

– Design for specific fill pattern in order to attain optimality

LocalDen.

Eff. Den

CMP-oblivious CMP-aware

L S D L S S/L% D D%

Verified under post worst-fill insertion

0.5 0.3 2637 350 21.0 2162 330 +15.0 20.4 -2.7

0.5 0.5 2637 350 20.5 1962 340 +30.6 19.8 -3.5

0.5 0.7 2637 350 20.0 2262 340 +13.2 19.4 -2.7

Verified under post best-fill insertion

0.5 0.3 2637 350 19.3 2162 330 +15.0 19.0 -1.5

0.5 0.5 2637 350 18.4 1962 340 +30.6 18.6 +0.8

0.5 0.7 2637 350 18.0 2262 340 +13.2 18.0 -0.3

Outline

Introduction and study goals Impact of fill insertion and fill patterns Impact of dishing/erosion on RC parasitics Impact on interconnect design Conclusions

Conclusions

Dummy fill can cause very large coupling capacitance variation w.r.t. nominal

Dishing and erosion cause substantial resistance increase, but have limited impact on coupling

CMP-aware design can improve design quality– Improve unit length delay by 3.3% under best-fill

Ongoing directions– Integration of multi-layer CMP modeling into flow– CMP-aware fill pattern synthesis, then single-

interconnect wire and buffer sizing, then full routing– Study the impact from more sources of variations on

interconnect performance and design