Copyright 2011 KIEEME. All rights reserved. http://www.transeem.org261

† Author to whom all correspondence should be addressed:E-mail: mailto:torikul@siswa.ukm.edu.my

Copyright ©2016 KIEEME. All rights reserved.This is an open-access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted noncommercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

pISSN: 1229-7607 eISSN: 2092-7592 DOI: http://dx.doi.org/10.4313/TEEM.2016.17.5.261

OAK Central: http://central.oak.go.kr

TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS

Vol. 17, No. 5, pp. 261-269, October 25, 2016

Design of an Active Inductor-Based T/R Switch in 0.13 μm CMOS Technology for 2.4 GHz RF Transceivers

Mohammad Arif Sobhan Bhuiyan, Mamun Bin Ibne Reaz, Md. Torikul Islam Badal, Md. Abdul Mukit, and Noorfazila Kamal†

Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi 43600, Malaysia

Received December 15, 2015; Revised June 13, 2016; Accepted June 20, 2016

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25 to 125 are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm2 that is the lowest-ever reported chip area for this frequency band was achieved.

Keywords: CMOS, ISM band, SPDT, T/R switch, Transceiver

Regular Paper

1. INTRODUCTION

An efficient transmit/receive (T/R) switch that is for the shar-ing of a single antenna between its transmitter and its receiver, whereby the size and system cost are reduced, is essential for modern wireless transceivers; furthermore, it improves the por-tability. The switches for RF devices can be implemented elec-tronically with the use of either on-chip complementary metal-oxide-semiconductor (CMOS) transistors that are integrated, or board-level components like GaAs MESFETs, PIN diodes, or even MEMS [1]. The T/R switch, which deals with both high-power transmitters and low-power receiver circuits, is one of the most-crucial parts of the transceiver (Fig. 1). During the transmission phase, the switch connects the antenna to the power amplifier of the transmitter so that the large signal is radiated to the sur-

roundings, and the low-power receiver circuit is simultaneously protected from being damaged [2]; alternatively, during the reception phase, it ensures that the low-noise amplifier receives the intended signal with a minimum loss. The key requisites for a

Fig. 1. SPDT T/R switch and matching network at the transceiver front end.

Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.262

T/R switch are an enhanced isolation, the minimal insertion loss, the maximum power-handling capacity, a high linearity, and an acceptable reliability for a large range of signal amplitudes [2,3].

To meet the performance requirements of T/R switches in terms of the standard CMOS technology, extensive research is being conducted throughout the world [3]. Yamamoto et al. (2001) illustrated the basic concerns for the improved perfor-mance of a classic series-shunt-type T/R switch whereby only the optimization of the MOS-gate width has occurred [4]. Although the design exhibited a low isolation and a low power-handling capacity, the area of the total chip is large due to the use of large CMOSs. For a further improvement of the performance, Huang (2001) introduced a dc biasing of the transistors along with their proper optimization in the gate, and the result comprises a low insertion loss, along with a moderate isolation and power-han-dling capacity [5]; however, relatively higher control voltages (6.0 V/2.0 V) were used, and even though the layout area was reduced by half, the final size is still large compared to the concurrent CMOS-switch circuits.

Huang (2004) and Hove et al. (2004) did, however, improve the isolation and the insertion loss of the switch by utilizing impedance transformation and a parasitic MOSFET model, re-spectively [6,7]. But the power-handling capacity of both these circuits is inadequate, while the layout areas of the switches were not reduced. In the same year, Talwalkar et al. (2004) adopted an increased-substrate-impedance technique to offer a narrowband resonance, whereby the additional on-chip inductors resulted in an increased chip area [8]. Bhatti et al. (2005) introduced a transformer-based T/R switch with numerous complex matching requirements that is only for low-power applications [9]. Yeh et al. (2006) utilized a resistive body-floating technique to improve the overall performance of the switch, but the power-handling capacity and the isolation of the switch are inadequate for high-power transceivers; nevertheless, they reduced the size of the chip [10].

In this paper, a proper transistor optimization, resistive body floating, and parallel-resonance techniques are used simultane-ously to obtain a high-performance series-shunt T/R switch at the 2.4 GHz ISM band in 0.13 μm CMOS technology; here, the avoidance of in-circuit bulky inductors and capacitors means that a very small chip size was also achieved. The proposed switch will be useful for 2.4 GHz ISM-band RF transceivers with respect to a variety of applications.

2. METHODOLOGY

A basic series-shunt T/R-switch topology is illustrated in Fig. 2. The addition of two shunt arms to the series-type T/R switch leads to the formation of the shunt/series-type T/R switch. The two complement-control signals Vc and Vc' are applied to the gate of the transistors M1 and M2 to alternate the ON/OFF states in a manner that is the same as that for the series-type switch. The series transistors, M1 and M2, execute the main switching task while the shunt transistors M3 and M4 provide low-imped-ance paths for the unwanted signals to reach the RF ground; therefore, the two shunt arms allow the T/R switch to exhibit a relatively enhanced isolation between the transmitter and the receiver port when compared to the situation where only the series-type switch is used. Although the isolation is improved in the series-shunt switch, the insertion loss of the switch is dete-riorated at higher frequencies.

2.1 Transistor W/L optimization

To improve the performance of the switch, the following tech-

niques are adopted for the basic circuit. Figure 3 shows the simplified models of an NMOS transistor

where the body is floated [11]. During the reception of the signal, the circuit that is shown in Fig. 2 is abridged to the equivalent cir-cuit that is shown in Fig. 4, whereby these models are used while the coupling effect to the transmitter is overlooked. To facilitate the realization of the consequences of the junction capacitances, the substrate resistances, and the on-state resistance on the cir-cuit, the insertion loss of the T/R switch in the receive mode has been analyzed for simplicity. For this analysis, the transistor M2 is biased in the linear region, while the transistor M4 remains in the cut-off mode. The signal is made to pass from the antenna port to the Rx port.

Fig. 2. Series-shunt topology of typical SPDT T/R switch.

Fig. 3. Models of NMOS transistor in (a) cut-off mode and (b) triode mode.

Fig. 4. Simplified receive-mode circuit for determination of S21.

263Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.

The signal loss that is included in a transceiver due to the use of a T/R switch is the insertion loss. The insertion loss is inversely proportional to the S21 parameter of the switch core, as follows:

(1)

According to Fig. 4, the value of S21 is derived by the following equation:

(2)

where Z0 is the characteristic impedance of the system, and Z1 is the total impedance at port 1; therefore, the following equa-tions have been achieved:

(3)

where

(4)

Here, Ron, M2 is the on-state resistance of the transistor M2. By substituting Eq. (3) into Eq. (1), the following equation is de-rived:

(5)

Then, by neglecting the values of Con, M2, Coff, and M4, Eq. (5) simplifies to Eq. (6), as follows:

(6)

According to Eq. (6), the insertion loss of a transistor is primar-ily dependent on its on-state resistance (Ron), and this is given by Eq. (7), as follows:

(7)

where μn is the mobility of the electrons, and Cox represents the capacitance-per-unit area of the gate.

Equation (7) implies that the Ron can be lowered with the use of transistors with a high mobility, a large W/L ratio, and a high gate-to-source/channel voltage (VGS); therefore, NMOS transis-tors are used for the realization of the proposed switch because of their relatively high mobility when compared with PMOS tran-

sistors. Besides, the NMOSs in the ON state are biased by a 1.8 V gate-to-channel voltage, which prevents both avalanches and gate-oxide breakdowns; in addition, the W/L ratio of the MOSs is the prevailing factor that influences the ON resistance of the M2 transistor, as well as the insertion loss. From Eq. (6), it is also apparent that the insertion loss of the switch decreases with the increasing of the W/L ratio of the transistor. But a limitation af-fects the enlargement of the transistor width because the source/drain to the body-parasitic capacitance becomes prominent, and this in turn degrades the isolation; that is, an inevitable trade-off between the Ron and the parasitic capacitances, which results in an optimum NMOS-width value at a given frequency band, must be considered. As shown in Fig. 5, the optimal width for the 2.4 GHz ISM band is 100 μm. In this study, a MOS with a width of more than 100 μm could not be used due to the scale limit of the foundry-provided RF CMOS transistors [12].

2.2 Resistive body floating

For an improved power-handling capacity, the body-floating technique is usually employed to reduce the signal loss that oc-curs through the body junctions of the transistors [13]. When the body of a transistor is connected to its source, an increased input power causes its drain-to-source voltage to become negative, and this in turn activates the diode between the drain and the body; consequently, the input impedance of the transistor be-comes lower, as shown in Fig. 6(a). But if the body-floating tech-

Fig. 5. NMOS width versus insertion loss of the switch.

221

1 | |

ILS

∝

2 2 0 221

1 1 0 1 1 0

2 ( )

V I Z VSV I Z I Z Z−

= =+ +

0, 4

21

0 0, 4

12 / /

1/ /

off M

off M

Zj C

SZ Zeq Z

j C

ω

ω

=

+ +

, 2, 2

11eq

on Mon M

Zj C

Rω

=+

2

0 0, 4

0, 4

1/ /

12 / /

off M

off M

Z Zeq Zj C

ILZ

j C

ω

ω

+ + ∝

20 , 2

0

2

2on MZ R

ILZ+

∝

1

( )on

n ox GS TH

R WC V VL

µ=

−

Fig. 6. MOS transistor (a) without and (b) with body-floating tech-nique [11].

(a)

(b)

Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.264

nique is adopted, the transistor body is tied to the ground with a high resistance, as shown in Fig. 6(b); therefore, the high-input impedance of the transistor is retained to maintain the improved power performance.

2.3 Triple-Well NMOS

To handle high-voltage signals with the usual MOS devices, the device terminals are floated generally. In the CMOS process, substrate-floating may degrade the performance due to the low-resistivity substrate [3,14]; to solve this problem, triple-well NMOS devices that consist of a P-well that is embedded within a deep N-well to create an isolated body for the NMOSs from the P-substrate, as shown in Fig. 7, are used for this design [15]. This architecture detaches the body from the substrate and offers a separate biasing of the body of the transistor and the deep N-well; as a result, the design robustness is improved.

2.4. Active inductor and parallel resonance

To improve the isolation property of the proposed T/R switch, a parallel-resonance technique has been proposed in this study. For this, the High Q active inductor circuit that was proposed by [16], and is shown in Fig. 8(a), is used. The active inductor circuit includes a common-source transistor (M4), a common-drain transistor (M3), a feedback resistor (Rf ), and the two current sources (I1) and (I2). A gain network consisting of the Rf and the M4 transistor develops a gain factor that is used to lower the loss from the parallel conductance (G); therefore, the Q of the induc-tor is increased and the total internal loss is decreased. The Rf also contributes to the retention of the inductance (L) value of the circuit.

The values of the parallel conductance (G), the inductance (L), the Q value, and the resonant frequency (ωo) of the equivalent circuit that are all shown in Fig. 8(b) can be obtained by using the following equations:

(8)

(9)

(10)

(11)

where gm4, gds4, and Cgs4 represent the transconductance, the output conductance, and the gate-source capacitance of the corresponding transistor, respectively.

According to the model that is illustrated in Fig. 3, the OFF-state capacitance (Coff ) can be derived by the following equa-tion:

(12)

The capacitance of the OFF transistor here allows for an un-wanted coupling of the signal between the TX and RX terminals. The inductors that are in shunt with the core switching transis-tors M1 and M2 (Fig. 2) help with the improvement of the isola-tion through a reduction of the coupling through the OFF-state capacitances, whereby a parallel resonance is created at a par-ticular frequency.

Figure 9 shows the equivalent circuit of the switch core during the transmission period. The total impedance of the circuit is therefore given by the following equation:

(13)

The inductor (L) and the equivalent capacitance (Cx) create a tank circuit that resonates at the frequency that is given by Eq. (14). At the resonant frequency, a high impedance that resists the passing of the signal through the unintended terminal is conse-quently created.

(14)

where

(15)

The complete series-shunt T/R switch circuit is illustrated in Fig. 10. The gate resistances are then used to provide a dc-bias isolation at the gates, and they are also used to mitigate the voltage fluctua-

Fig. 7. The triple-well-NMOS transistor structure.Fig. 8. High Q active inductor: (a) Schematic circuit and (b) its equiv-alent circuit.

(a) (b)

43

41m

P dsf ds

gG R gR g

= ≈ ++

( )3 4

4 3

1gs f ds

m m

C R gL

g g+

≈

( )3 4

4 3

1gs f ds

m m

C R gL

g g+

≈

( )4 3

4 3 41m m

ogs gs f ds

g gC C R g

ω ≈+

gs gd sb dboff ds

gs gd sb db

C C C CC CC C C C

= + ++ +

( ) 2 2 21

2 2 2

1 ( )1 P off s

eq P s

R j C C R LZ R R L

ω ω

ω

+ + + +=

+

12r

x

fLCπ

=

1x offC C C= +

265Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.

tions around the gate terminal that can affect the channel resistance and cause breakdowns at the gate terminal [12]; moreover, to main-tain the switching speed of the transistor, a suitable gate-bias resistor is very important. For the body floating (RB1-RB6), 5 KΩ resistors were used, and 5 Ω resistors were used for the gate biasing (RG1-RG6).

Table 1 provides the specifications of the components that were used.

3. RESULTS AND DISCUSSION

The proposed T/R switch that is for 2.4 GHz-band RF applica-

tions was designed and simulated in a 0.13 μm CMOS process. The Design Architect (DA-IC) and IC station tools of Mentor Graphics were used to measure the performance of the switch. In this study, the following aspects of the switch are evaluated: insertion loss, isolation, linearity, power-handling capacity, sta-bility, and temperature dependence. Statistical analyses were also performed to verify the reliability of the switch.

Figure 11 and Fig. 12 show the insertion loss and the isolation of the switch as a function of the input signal in both the Tx and Rx operational modes. For the Tx mode, the insertion loss of the switch is measured from the Tx port to the Antenna port, while the Antenna port to the Rx port is measured for the RX mode. For the Tx mode, the isolation is measured from the Tx port to the Rx port, while for the Rx mode, the isolation is measured from the Antenna port to the Tx port. In both modes, the insertion loss of the switch increased with an increasing of the input-signal strength, as an NMOS behaves like a resistor that is connected between the drain and source terminals; moreover, the rate of the change of the insertion loss is higher in the receive mode due to the increased leakage through the three-shunt path at the Rx port, whereas the isolation is observed to decrease in both modes due to the increased shunt leakage. It is evident from Fig. 13 that the isolation and the insertion loss at a 30 dBm power remain constant in this band for both the transmit and receive operational modes; here, the values are 28.67 dB and 1 dB, re-spectively, during the transmission, and 19.4 dB and 1.16 dB, re-spectively, during the reception. These results imply that the per-formance of the switch will not be affected by accidental changes of the frequencies, and its performance is therefore stable.

The linearity of a switch influences the maximum amount of power that it can handle. A power-compression point of 1 dB (P1dB) is a basic measurement of the linearity and the power-handling capacity.

Fig 9. The equivalent circuit of the switch core during the transmis-sion period.

Table 1. Specifications of the T/R-switch components.

Elements ValueM1–M8 100/0.13 (μm/μm)

M9–M16 0.35/0.13 (μm/μm)RG1–RG6 5 ΩRB1–RB6 5 KΩ

Fig. 10. The schematic circuit of the active-inductor-based series-shunt T/R switch. M1-M8 100/0.13 (μm/μm), M9-M16 0.35/0.13 (μm/μm), RG1-RG6 5 Ω, RB1-RB6 5KΩ, Rf 5 KΩ, VDD 1.8 V, Vc 1.8 V, Vbias 1.8 V.

Fig. 11. Insertion loss of the switch in Tx and Rx modes.

Fig. 12. Isolation of the switch in Tx and Rx modes.

Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.266

Figure 14 shows the large signal linearity of the switch, and the values of the P1dB in the Tx and Rx modes are 35.8 dBm and 20.4 dBm, respectively. The P1dB values for different frequencies of the 2.4 GHz band are shown in Fig. 15, and these provide infor-mation regarding the potential design flexibility in terms of the power handling and the reliability of the proposed switch.

The temperature sensitivity of an IC is one of the major con-siderations here. For a sound design, the performance-parameter change of an IC should be as small as possible. For the proposed T/R switch, the insertion loss and the isolation vary by 0.019 dB and 0.095 dB, respectively, for a temperature change from - 25 to 100, as shown in Fig. 16; here, it is implied that the sensitiv-ity of the performance of the switch to temperature variations is only slight.

The completion of a statistical analysis is very important to ensure the reliability of the CMOS circuit in the absence of ex-periment results.

Figure 17 and Fig. 18 show the corner analysis regarding the proposed switch for the insertion loss and the isolation, respec-tively, in both the transmit and receive operational modes. From Fig. 17, it is clear that the insertion loss in the transmit mode does not vary much for the ss, ff, and tt modes; besides, the high-est value of the insertion loss in the receive mode is observed in the ff mode, and the lowest value is detected in the ss mode for the same input power. Alternatively, the isolation values are more or less the same in both modes, as shown in Fig. 18.

The Monte Carlo analysis of the switch in the Tx mode is given in Fig. 19 and Fig. 20 for the insertion loss and the isolation, re-spectively. For both 100 runs and 200 runs, most of the values of the insertion loss are within 0.99 dB and 1.01 dB, while most of

Fig. 14. Power-handling capacity of the switch in 2.4 GHz band.

Fig. 15. Linearity of the switch in 2.4 GHz band.

Fig. 16. Temperature sensitivity of the switch in 2.4 GHz band.

Fig. 17. Corner analysis for insertion loss of the switch.

Fig. 18. Corner analysis for isolation of the switch.

Fig. 13. Stability of the isolation and insertion loss of the switch in 2.4 GHz band.

267Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.

the isolation values are within 28.4 dB and 28.8 dB. The Monte Carlo analysis for the Rx mode that is shown in Fig. 21 and Fig. 22 clearly shows that, for both 100 runs and 200 runs, most of the values of the insertion loss are within 1.080 dB and 1.115 dB, while the isolation values are within 19.1 dB and 19.8 dB. The Monte Carlo results do not differ significantly, and the perfor-mance is therefore quite stable.

The proposed switch can handle large amounts of power dur-ing the transmission mode, while a very small insertion loss is incurred and an improved isolation is obtained regarding the re-ceiver circuit. This characteristic is essential because the higher the isolation, the greater the reduction of the transmitter-to-receiver power loss, and this is directly related to the transmit-ter efficiency. Besides, the receiver circuit handles very small amounts of power, so an improved isolation is required to pro-tect the receiver from high transmitted powers. The low insertion loss makes the switch suitable for high-performance transceiver front-ends, whereby an enhanced transmitter efficiency is ex-ploited; furthermore, the high-power handling capacity of the switch makes it reliable for larger signal transmissions with ad-equate linearities. Alternatively, a low insertion loss and a high isolation are vital for the reception mode because the receiver re-ceives very weak signals, and the leakage toward the transmitter will further weaken the signal. A high insertion loss degrades the receiver output, while a low isolation demeans the noise figure of the receiver; moreover, the low switching time is a crucial issue for both the transmission and reception stages, and especially for high-frequency applications.

The following characteristics make the switch appropriate for 2.4 GHz ISM-band RF applications: A 1 dB insertion loss, a 28.67 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode, and a 1.16 dB insertion loss and a 19.4 dB isola-tion in the receive mode with an extremely-low power dissipa-tion and a lesser sensitivity to temperature variations. Further, these values remain constant for the entire 2.4 GHz band, and this means that the switch is reliable.

Figure 23 shows the complete layout of the T/R-switch circuit. The area of the switch is only 0.0207 mm2, and to the authors’ best knowledge, it is the lowest-ever reported chip area for this frequency band.

A comparison of this work with the recently reported per-formances of 2.4 GHz CMOS switches is given in Table 2; from this comparison, it is evident that the isolation of the proposed switch is competitive against the results of the other research-ers that are presented in Table 2. Although the switch-isolation values that are reported in [7,8,21], and [22] are better, the cor-responding power-handling capacities and insertion-loss values are not satisfactory; furthermore, the insertion-loss values that are presented in [13] and [17] are sound, but again, the other pa-rameters are not satisfactory. The P1db values that are presented in [10,19], and [23] are relatively small when compared with those of this study, but the insertion-loss and isolation values are competitive. Importantly, though, the core layout area of the proposed chip is the smallest of all.

4. LIMITATIONS OF THE STUDY AND FUTURE WORK

In this study, an SPDT T/R switch for the CEDEC 0.13 μm CMOS process technology has been designed and simulated with the use of the Mentor Graphics environment for 2.4 GHz ISM-band RF applications. The main limitation of this study is the lack of a realization in a real-life environment; however, the fabrication of the circuit and the experimental measurement greatly increase the confidence regarding the proposed solution.

Fig. 19. Monte Carlo analysis for insertion loss of the switch in Tx mode.

Fig. 20. Monte Carlo analysis for isolation of the switch in Tx mode.

Fig. 21. Monte Carlo analysis for insertion loss of the switch in Rx mode.

Fig. 22. Monte Carlo analysis for isolation of the switch in Rx mode.

Fig. 23. Complete switch layout with dimensions = 0.18 mm2 × 0.115 mm2.

Trans. Electr. Electron. Mater. 17(5) 261 (2016): M.A.S. Bhuiyan et al.268

All of the proposed designs were fabricated in Silterra, a Malay-sian fabrication house, and the Malaysian Government is its ma-jor shareholder. Other fabrication industries such as TSMC and UMC exist, but higher costs are required. As part of a subsidized project for academics, the proposed design has already been sent to Silterra for fabrication. For academics of Malaysian uni-versities, Silterra will follow its own timeline for the subsidized IC fabrication, which is scheduled to occur after seven or eight months; therefore, the fabrication and the measurement results of the fabricated chip can be achieved after approximately nine or ten months.

The results that were achieved in this article are, however, the post-layout simulation results. The Electronic Design Automa-tion (EDA) tools of Mentor Graphics, which are also widely used in the industry along with Cadence and Synopsys, have been used for this study. It is most likely that the post-fabrication measurement will follow the post-layout simulation result. The experiment results will surely be verified with the simulated results once they are received. In the absence of the experiment results, the statistical analyses of the proposed circuit have been included to verify the reliability of the circuit.

CEDEC 0.13 μm CMOS process technology has been used for the design and simulation of this paper. But other process technologies such as SOI, BICMOS, and Twin-tub can be utilized for the design and simulation of the proposed circuit, and the performance, size, and cost can all be compared. Besides, other advanced transistors such as asymmetric transistors and carbon-nanotube transistors can be utilized instead of the traditional MOSFET structure for improved performances. In this study, CMOSs with a width of more than 100 μm could not be used due to the scale limit of the RF CMOS transistors that were provided by the foundry [12]; moreover, while it has been shown that this circuit can handle transmission powers that are as high as 35 dBm, this study could not verify whether the CMOSs that are used in this design can withstand such high powers.

In this study, an active inductor-based parallel-resonance technique is utilized to improve the isolation of the switch. But it is obvious that it is the combination of the CMOSs and the other components in the active inductor circuit that determine the resonant-frequency value of the equivalent tank circuit; therefore, the proposed design will work well for the 2.4 GHz ISM band only, and the configurations need to be changed for other frequency bands. Besides, it is clear that some deviations of the parameter values occur with the variation of the temperature; therefore, the performance parameters that have been stated are

for 25 only.Of further note, the comparison table (Table 2) shows that the

overall performance of the proposed circuit is better than those of the others; however, for this comparison, only the series-shunt topology of the switches at the 2.4 GHz band that is reported in the literature is considered. Further, if it is necessary to empha-size only one parameter such as a very high isolation or a very low insertion loss, the circuit is needed for a reorganization, and the other performance-parameter values need to be compro-mised.

5. CONCLUSIONS

A high-performance and fully integrated SPDT T/R switch is a pressing need regarding every modern RF device. In this study, a high-performance fully-on-chip 2.4 GHz T/R switch that is designed in 0.13 μm CMOS technology has been reported. The results exhibit a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode, while a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited in the receive mode with an extremely-low power dissipation of 377.14 μW for the 1.8 V/0 V control voltages. The body-floating technique, the proper transistor optimization, a triple-well-structured transistor, and a parallel resonance with the active in-ductor helped the proposed switch with the simultaneous attain-ment of a low insertion loss, a high isolation, a faster switching speed, a sound power performance, and a high linearity. Besides, the chip area of the switch has been reduced drastically through an avoidance of bulky inductors and capacitors; that is, it oc-cupies only 0.0207 mm2, and to the authors’ best knowledge, this area is the lowest that has ever been reported for this frequency band. The stability and reliability of the switch mean that it is also highly suitable for 2.4 GHz wireless terminals.

REFERENCES

[1] M.A.S. Bhuiyan, M.B.I. Reaz, J. Jalil, L. F. Rahman, and T. G. Chang, Journal of Central South University, 22, 546-551 (2015). [DOI: http://dx.doi.org/10.1007/s11771-015-2554-2]

[2] M.A.S. Bhuiyan, Y. Zijie, J. S. Yu, M.B.I. Reaz, N. Kamal, and T. G. Chang, Anais da Academia Brasileira de Ciências, 88, 1089-1098 (2016). [DOI: http://dx.doi.org/10.1590/0001-3765201620150123]

Table 2. Performance-comparison table of the T/R switch.

Ref. Year CMOS Process Vc/Vc' (volts) Isolation (dB) P1dB (dBm) IL (dB) Area (mm2) Comments[4] 2001 (μm) 1.8/0 24 11 1.5 45* Optimizing gate width

[17] 2001 0.18 6.0/2.0 24.4 17 0.8 0.28 Optimizing transistor widths and dc biasing[18] 2002 0.18 20.6 23 1.1 0.28 Impedance transformation[7] 2004 0.35 3.6/0 42 16 1.3 0.026 Parasitic MOSFET model

[8] 2004 0.35 32 28.5 1.5 0.56Increasing the substrate impedance with properly tuned

LC circuit[6] 2004 0.18 6.0/2.0 20.6 20.6 1.1 0.28 Impedance transformation

[10] 2006 0.18 1.8/0 35 21.3 0.7 0.03 Body floating[19] 2007 0.13 3.3/0 31 28 0.8 0.09 Transistor stacking[20] 2008 0.5 1.2/0 - 25.33 1.085 - DC biasing

[14] 2008 0.065 - 28 29 0.8 0.2 Optimizing the matching network

[21] 2009 0.18 - 40 - 1.0 - Floated-body and Connected-body MOSFETs[22] 2011 0.18 - 43 21.5 1.1 0.672 Transistor stacking[23] 2012 0.032 1.8/0 32 34 1.3 - Optimizing gate width[24] 2014 0.18 1.8/0 24.5 22.4 0.72 0.037 Diode-connected transistor pair This

work2015 0.13 1.8/0

28.6 (Tx)

19.4 (Rx)35.8

1.0 (Tx)

1.1 (Rx)0.0207

Optimizing gate width, body floating, triple-well structure,

and parallel resonance

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