Design of 2 Stage BJT CE Amplifier
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Transcript of Design of 2 Stage BJT CE Amplifier
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8/2/2019 Design of 2 Stage BJT CE Amplifier
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Design of 2 stage BJT CE amplifier(SEM 4)
Circuit diagram:
Selection of voltage gains
If ratio of output impedences is given thenAv1/Av2 = Rc1/Rc2
[If ratio of output impedences is not given then assume Rc1/Rc2 = 2]Overall voltage gain, Av = Av1 * Av2
[Substitute Av2 in terms of Av1 or vice versa & find Av1 & Av2]
[If you have to select a transistor, select BC 147B for its higher inputimpedence & hfe]
Part 2: Design of second stage
Step 1: Calculation of RL
RL = (Vo peak)/(Io peak)
[Not necessary if RL is not given or Vo peak, Io peak is not given]
Step 2: Selection of Rc2
mod(Av2) = (hfe * RL2')/hie
[RL' = (Rc2) parallel (RL) or RL' = Rc2 if RL is not given]
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[if min voltage gain is specified, use hfe min. If some specific voltagegain is specified, use hfe
typ]
[Calculate RL' & Rc2]
Step 3: Selection of Vceq
Case 1:Vcc is given
Vceq 2 = 1.5 * (Vo peak + Vce saturation)
If Vo is not given thenVceq = Vcc/2
Vre2 = 10% to 20 % of Vcc
Vrc2 = Vcc - Vceq2 - Vre2
Icq2 = Vrc2/Rc2
Re2 = Vre2/Icq2
[Select lowerstandard value so that drop across Re is less which increases gain of the output]
Case 2: Vcc is not given
Vceq 2 = 1.5 * (Vo peak + Vce saturation)
Ic2 peak = Vo peak/ RL2
Assume Vre2 = 2 V
Vcc = Vceq + Icq(Rc2 + Re2)[Select on higher side]
Step 4: Selection of R3 & R4
If stability factor is not given ,assume S = 8
S = (hfe + 1)/(1 + (hfe * Re2)/(Rb2 + Re2))
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Find Rb[Do not standardise]
Vr4 = Vbe + Vre
Vr3 = Vcc - Vr2
Assume Vbe = 0.6V [for Si, 0.3 for Ge if not specified]
R3/R4 = Vr3/Vr4 .............(A)
[Get R3 in terms of R4 & substitute in Rb2]
Rb2 = R3 parallel R4 = (R3 * R4)/(R3 + R4)
Find R4[Select lower standard value to make circuit indepent of beta]
Substitute in (A) to find R3
Select higher standard value so that circuit draws minimum current from supply
Part 2: Design of first stage
[Find value of Av2 using designed value of Rc2]
Then Av1 = Av/Av2
Step 1: Selection of Rc1
mod(Av1) = (hfe * RL1')/hie
[RL' = (Rc1) parallel (Rb2) parallel (hie)]
[if min voltage gain is specified, use hfe min. If some specific voltagegain is specified, use hfetyp]
[Calculate RL' & Rc1]
Let Vceq1 = Vceq2Vrc1 = Vrc2Vre1 = Vre2
Icq1 = Vrc1/Rc1
Re1 = Vre1/Icq1
Step 3: Selection of R1 & R2
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s = (1 + hfe max)/(1 + ((hfe max * Re )/(Rb + Re))Find Rb[Do not standardise]
Vr2 = Vbe + Vre
Vr1 = Vcc - Vr2
Assume Vbe = 0.6V [for Si, 0.3 for Ge if not specified]
R1/R2 = Vr1/Vr2 .............(A)
[Get R1 in terms of R2 & substitute in Rb]
Rb = R1 parallel R2 = (R1 * R2)/(R1 + R2)
Find R2
[Select lower standard value to make circuit indepent of beta]
[Substitute in (A) to find R1]
Select higher standard value so that circuit draws minimum current from supply
Step 4: Selection of coupling capacitors
Select higher standard value for all capacitors
Selection of Ce1:
Xce1 = Re1/10Ce1 = 1/(2*pi * FL * Xce1) [FL = lower cutoff frequency. Assume FL = 20 Hz (For all
capacitors)if not specified]
Selection of Ce2:
Xce2 = Re2/10
Ce2 = 1/(2*pi * FL * Xce2) [FL = lower cutoff frequency.Assume FL = 20 Hz (For all
capacitors)if not specified]
Selection of Cb1:
[Rb = R1 parallel R2]
[If Rs[Source resistance] is not specified assume Rs = 0]
Xcb1 = ((Rb) parallel (hie))
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Cb1 = 1/(2 * pi * FL * Xcb)
Selection of Cb2:
[Rb2 = R3 parallel R4]
Xcb2 = Rc1 + ((Rb) parallel (hie))
Cb2 = 1/(2 * pi * FL * Xcb)
Selection of Co:
[Rb2 = R3 parallel R4]
Xcc = Rc + RL [If RL[load resistance] is not specified thenassume amplifier is connected to asimilar next stage. Hence RL = (Rb1)parallel (hie)]
Cc = 1/(2 * pi * FL * Xcc)
[Draw the figure with designed values. Do all this in about 36 - 40 minutes (1.8minper mark)]