EE1411

Microelettronica

Design Design MethodologiesMethodologies

EE1412

Microelettronica

Productivity TrendsProductivity Trends

1

10

100

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxxx

xx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Source: Sematech

Complexity outpaces design productivity

Com

plex

ity

2.5 μm

0.35 μm

0.1 μm

EE1413

Microelettronica

A Simple ProcessorA Simple Processor

MEMORY

DATAPATH

CONTROL

I N P U T - O U T P U T

INP

UT/

OU

TPU

T

EE1414

Microelettronica

A SystemA System--onon--aa--Chip: ExampleChip: Example

EE1415

Microelettronica

Impact of Implementation ChoicesImpact of Implementation Choices

Ene

rgy

Effi

cien

cy (i

n M

OP

S/m

W)

Flexibility(or application scope)

0.1-1

1-10

10-100

100-1000

None Fullyflexible

Somewhatflexible

Har

dwire

d cu

stom

Con

figur

able

/Par

amet

eriz

able

Dom

ain-

spec

ific

proc

esso

r(e

.g. D

SP

)

Em

bedd

ed m

icro

proc

esso

r

EE1416

Microelettronica

Implementation ChoicesImplementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

EE1417

Microelettronica

The Custom Approach The Custom Approach Intel 4004

EE1418

Microelettronica

Transition to Automation and Regular Transition to Automation and Regular StructuresStructures

Intel 4004 (Intel 4004 (‘‘71)71) Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486

EE1419

Microelettronica

CellCell--based Designbased Design

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier, …)

Routingchannel

Logic cellFeedthrough cellR

ows

of c

ells

Standard Cell Layout methodology

EE14110

Microelettronica

The Evolution of Standard Cell The Evolution of Standard Cell

[Brodersen92]

EE14111

Microelettronica

Standard Cell Standard Cell –– The New GenerationThe New Generation

Cell-structurehidden underinterconnect layers

EE14112

Microelettronica

Standard Cell Standard Cell -- ExampleExample

3-input NAND cell(from ST Microelectronics):

EE14113

Microelettronica

Automatic Cell GenerationAutomatic Cell Generation

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell

EE14114

Microelettronica

MacroModulesMacroModules

256×32 (or 8192 bit) SRAM Generated by hard-macro module generatorImplemented in 0.18 μm CMOS technology (0.094 mm2)

EE14115

Microelettronica

““SoftSoft”” MacroModulesMacroModules

Synopsys DesignCompiler

8 x 8 Multiplier

EE14116

Microelettronica

Semicustom Design FlowSemicustom Design Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Itera

tion

Des

ign

Itera

tion

EE14117

Microelettronica

The The ““Design ClosureDesign Closure”” ProblemProblem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

EE14118

Microelettronica

Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists

EE14119

Microelettronica

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

LateLate--Binding ImplementationBinding Implementation

EE14120

Microelettronica

Gate Array Gate Array —— SeaSea--ofof--gatesgates

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

EE14121

Microelettronica

Gate Array ArchitecturesGate Array Architectures

EE14122

Microelettronica

Examples of SeaExamples of Sea--ofof--gate Primitive Cellsgate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation

EE14123

Microelettronica

SeaSea--ofof--gatesgates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 μm CMOS)

EE14124

Microelettronica

XilinxXilinx FPGA FPGA ArchitectureArchitecture

EE14125

Microelettronica

AntifuseAntifuse--Based FPGABased FPGA

antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2 λ

Open by default, closed by applying current pulse

EE14126

Microelettronica

RAMRAM--based FPGA based FPGA

Xilinx XC4000ex

EE14127

Microelettronica

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1

TwoTwo--Level LogicLevel LogicEvery logic function can be expressed in sum-of-products format (AND-OR)

Inverting format (NOR-NOR) more effective

EE14128

Microelettronica

ArrayArray--Based Programmable Logic (1)Based Programmable Logic (1)

PROMIndicates programmable connection

Indicates fixed connection

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Fixed AND array

ProgrammableOR array

EE14129

Microelettronica

Programming a PROMProgramming a PROM

f0

1 X 2 X 1 X 0

f1NANA: programmed node

EE14130

Microelettronica

PLA

I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Programmable AND array

ProgrammableOR array

ArrayArray--BasedBased ProgrammableProgrammable LogicLogic (2)(2)

EE14131

Microelettronica

ArrayArray--BasedBased ProgrammableProgrammable LogicLogic (3)(3)

PAL

I 5 I 4

O 0

I 3 I 2 I 1 I 0

O 1O 2O 3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

EE14132

Microelettronica

More Complex PALMore Complex PAL

i inputs, j minterms/macrocell, k macrocells

programmable AND array (2 i 3 jk ) k macrocells

j -wide OR array

j

macrocell

productterms

D Q

A

1

j

BCLK

OUT

C i i inputs

i x

EE14133

Microelettronica

PLA Layout PLA Layout –– Exploiting RegularityExploiting Regularity

f0 f1x0 x0 x1 x1 x2 x2Pull-up devices Pull-up devices

VDD GNDφAnd-Plane Or-Plane

EE14134

Microelettronica

CellCell--Based Programmable LogicBased Programmable Logic

FA 0

B

S

1

ConfigurationA B S F=0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X + Y1 0 X1 0 Y1 1 1 1

XYXY

XY

F = A ·S + B ·S

22--input input muxmuxas programmableas programmablelogic blocklogic block

EE14135

Microelettronica

Logic Cell of Logic Cell of ActelActel FuseFuse--Based Based FPGAFPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1

EE14136

Microelettronica

LookLook--up Table Based Logic Cellup Table Based Logic Cell

Out

ln1 ln2

Mem

ory In Out

00 00

01 1

10 1

11 0

Out

ln1 ln2

Mem

ory In Out

00 00

01 1

10 1

11 0

Cell schematicXOR function

EE14137

Microelettronica

LUTLUT--Based Logic CellBased Logic Cell

Xilinx 4000 Series

EE14138

Microelettronica

ArrayArray--Based Programmable WiringBased Programmable Wiring

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontaltracks

Vertical tracks

Cell

M

EE14139

Microelettronica

MeshMesh--based Interconnect Networkbased Interconnect Network

Switch Box

Connect Box

InterconnectPoint

EE14140

Microelettronica

Transistor Implementation of MeshTransistor Implementation of Mesh

EE14141

Microelettronica

Hierarchical Mesh NetworkHierarchical Mesh Network

Use overlayed meshto support longer connections

Reduced fanout and reduced resistance

EE14142

Microelettronica

Prewired ArraysPrewired ArraysClassification of prewired arrays (or field-

programmable devices):Based on Programming Technique

Fuse-based (program-once)Non-volatile EPROM basedRAM based

Programmable Logic StyleArray-BasedLook-up Table

Programmable Interconnect StyleChannel-routingMesh networks

EE14143

Microelettronica

SystemSystem--onon--aa--ChipChip

RAM

500 k Gates FPGA+ 1 Gbit DRAMPreprocessing

Multi-SpectralImager

μCsystem+2 GbitDRAMRecog-nition

Ana

log

64 SIMD ProcessorArray + SRAM

Image Conditioning100 GOPS

Embedded applications where cost, performance, and energy are the real issues!DSP and control intensiveMixed-modeCombines programmable and application-specific modulesSoftware plays crucial role

EE14144

Microelettronica

Heterogeneous Programmable Heterogeneous Programmable PlatformsPlatforms

Xilinx Vertex-II Pro

High-speed I/O

Embedded PowerPcEmbedded memories

Hardwired multipliers

FPGA Fabric

EE14145

Microelettronica

Berkeley Pleiades ProcessorBerkeley Pleiades Processor

• 0.25um 6-level metal CMOS

• 5.2mm x 6.7mm

• 1.2 Million transistors

• 40 MHz at 1V

• 2 extra supplies: 0.4V, 1.5V

• 1.5~2 mW power dissipationInterface

Reconfigurable

Data-path

FPGA

ARM8 Core

EE14146

Microelettronica

SummarySummary

Digital CMOS Design is kicking and healthySome major challenges down the road caused by Deep Sub-micron

Super GHz designPower consumption!!!!Reliability – making it work

Some new circuit solutions are bound to emergeWho can afford design in the years to come? Some major design methodology change in the making!