Design Issues of Flash-based SSD& Hybrid Disks

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Design Issues of Flash-based SSD&

Hybrid Disks

Han-Lin Li

Dept. Computer Science and Information Engineering

National Taiwan University

Advisor: Prof. Chia-Lin Yang

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Trend of Flash Memory Application

Machine sizeCell Phone PDA Notebook Server

Solid State DriveSingle Chip Hybrid Disk

Low Power

Small Size

Reliability

Low Power

Performance

Reliability

Low Power

Performance

Reliability

Small Size

Requirement

Sensor Node

Low Power

Small Size

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Outline Background

NAND vs. NOR Organization and characteristics of NAND flash memory Trend of NAND flash memory technology

Design Issues of Flash-Based SSD FTL design Efficient garbage collection Wear-leveling techniques Multi-Chip (bank) flash memory Flash memory as a swap device of virtual memory

Design Issues of Hybrid Disk Our current work

NAND vs. NOR NOR

Design for storing program code Needs random-access for reading Rarely needs to be updated

Cells are connected in parallel to the bit lines Allowing cells to be read and programmed individually

NAND Goal of NAND flash was to replace hard disks

Reduce chip area required to implement a given capacity Reduce cost per bit Increase maximum chip capacity

Cells are connected in series Cells connected in series must be read in series Occupy only a small fraction of the area of equivalent NOR cells

NAND vs. NOR

NOR[19] NAND[20]

Read/Write Unit Word(2B) 2KB

Block size 16K/64K 128K

Read latency 110ns 25µs

Write latency 100µs 200µs

Erase time 0.6s 2ms

Cost Expensive Cheap

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Organization of a Typical NAND Flash Memory

NAND Flash Cell Single-level Cell (SLC)

1 bit/Cell Level 0 = Erased “1” Level 1 = Programmed to “0”

Multi-level Cell (MLC) 2 bits/Cell Level 0 = Erased “11” Level 1 = Programmed to “10” Level 2 = Programmed to “01” Level 3 = Programmed to “00”

Voltage

11 10 01 00

Dis

trib

utio

n Voltage

1 0

Dis

trib

utio

n

SLC

MLC

Control Gate

Floating Gate

SubstrateDrain Source

Tunnel Oxide

Storedelectrons

Erased = “1” Programmed = “0”

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NAND Flash Cell Potential problem

Endurance Flash has limited write/erase times

Data retention Stored electrons lost due to leakage

Control Gate

Floating Gate


Tunnel Oxide

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……

Block 0Block 0Block 1Block 1Block 2Block 2Block 3Block 3

Erase Erase one one

blockblock……

Read/Read/Write Write

one pageone page

1 Page


Samsung K9F1208R0B 1 Block = 32 pages 1 Page = 512B

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Flash Memory Characteristics Write once

Written page can not be overwritten

Flash Memory

Flash block

A free pageA free page

10


Written page can not be overwritten

A

Flash Memory

A live pageA live pageA free pageA free page

Live page Flash block

11


Written page can not be overwritten Out-place update

A’

Flash Memory

A live pageA live pageA dead pageA dead page


Dead page

New data

Flash block

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Flash Memory Characteristics (cont’d) Garbage collection

When # of free pages < GCt ( Garbage Collection Threshold ) Erase a block to reclaim dead pages

Flash Memory

Flash block



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Flash Memory Characteristics (cont’d)

Flash Memory

Flash block



Garbage collection When # of free pages < GCt ( Garbage Collection

Threshold ) Erase a block to reclaim dead pages

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Flash Memory Characteristics (cont’d) Garbage collection

When # of free pages < GCt ( Garbage Collection Threshold ) Erase a block to reclaim dead pages

Overheads Live data copying Block erase

Flash Memory

Flash block



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Flash Storage System Architecture

Physicaldevice

File Translation Layer(FTL)

Command translationMTD layer

Logic Block Address

Physical address

Flash MemoryFlash Memory

(0, 0, 3)1 (0, 1, 2)2 (1, 2, 1)

LBA Physical address(bank, block, page)

……

address translation table

0GarbageCollection

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Trend of Flash Memory Technology As VLSI technology continues to scale,

Advantage Capacity ↑

Disadvantage Data retention ↓

The floating gate is smaller # of electrons in floating gate ↓

The tunnel oxide is thinner Leakage current ↑

Endurance ↓ The tunnel oxide is thinner

Write/Erase operations damage oxide more easily

Control Gate

Floating Gate


Tunnel Oxide

2007 2009 2011 2013 2015

NAND Flash-

SLC(μm2/bit)

0.0130 0.0081 0.0052 0.0031 0.0021

NAND Flash-

MLC(μm2/bit)

0.0065 0.0041 0.0013 0.0008 0.0005

ITRS 2007 roadmap for memory technology.

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Trend of Flash Memory Technology Multi-Level Cell (MLC) flash

Advantage Capacity ↑

Disadvantage Data retention ↓

Voltage gap between each state is smaller

Voltage

Dis

trib

utio

n

TimeVoltage

Dis

trib

utio

nVoltage

Dis

trib

utio

n

TimeVoltage

Dis

trib

utio

n

SLC

MLC

Control Gate

Floating Gate


Tunnel Oxide

11 10 01 00

1 0

11 10 01 00

1 0

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Trend of Flash Memory Technology Page/Block size increasing [3]

Latency ─ Throughput ↑ Operation 512B-page 2KB-page

Read (page) 15 us 25usWrite (page) 200 us 200 usErase (block) 2 ms 2 ms

Latency of operation in different flash page size [4,5]

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Design Issues of Flash-Based SSD FTL design

Reduce FTL’s memory requirement Efficient garbage collection

Reduce garbage collection overhead Wear-leveling techniques

Prevent blocks from being unevenly worn so as to lengthen the overall lifespan

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FTL (File Translation Layer) Map logical address to physical address to simulate

traditional disk FTL granularity

How many LBAs associated with an entry of FTL FTL granularity ↑

Smaller FTL table size Larger update overhead

A BC D

Block X

A’

Block Y

FTL granularity = 1 page

Update page A

A B

FTL

A BC D

Block X

A’

Block Y

FTL granularity = 2 page

Update page A

BA B

FTL

FTL (File Translation Layer) (cont.) Dynamic switch between fine-granularity and coarse-granularity

in the FTL [7] Exploit the advantages of fine-grained FTL and coarse-grained

FTL Switch to fine-grained FTL when out-place update triggered

Reduce update overhead Switch to coarse-grained FTL when # of entries in fine-grained FTL

exceeds limit Limit FTL table size LRU replacement policy

A BC D

Block X

A’

Block Y

Update page A

A B

FTL Address Translation Table

A Fine-GrainHash Table

A Coarse-GrainHash Table

FTL (File Translation Layer) (cont’d) Multi-level FTL [6]

Some LBAs are never used Don’t create FTL entries for unused LBAs in Multi-level

FTL Save memory spaces

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Efficient Garbage Collection Objective

Reduce garbage collection overhead (# of live page copies) Cost-benefit policy [16]

Choose the block of the largest score calculated by age: the time past since last modification of the block u: the live pages in the block

Hot-cold separation [10] High # of write operation => hot data Low # of write operation => cold data Put hot data in the same block can reduce garbage collection

overhead

HH

HH

H H

Block X

H HC CC C

C CC C

Block X

After hot data are rewritten

Block X

C CC C

C CC C

Block X

H

C

Hot data

Cold data

Dead page

Wear-Leveling Techniques Principle #1

Allocate hot data to blocks with fewer erasure cycles Principle #2

At garbage collection, choose a block with fewer erasure cycles as the victim block

Wear-Leveling Techniques Hot-Cold Swapping [8]

Periodically check If the difference between the erasure cycles of the oldest

block and the youngest block > threshold Data stored in the oldest block and in the youngest block

are swapped.

Static-Dynamic [17] Static:

Hot-cold swapping Dynamic:

Blocks are allocated for new writes from a round-robin queue that sorts blocks in terms of their physical block addresses

Wear-Leveling Techniques CAT [14]

When garbage collection, always erase the block of the minimal score calculated by formula

μi: The space utilization of block i

εi: The erasure cycle of block i.

ai: age of block i.

iii

i

a

1

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References1. Energy-Aware Flash Memory Management in Virtual Memory System,L.-H. Lin, C.-L. Yang, H.-W. Tseng, to appear in IEEE

Transactions on Very Large Scale Integration (VLSI) Systems 2. Improving NAND Flash Based Disk Caches, T. Kgil, D. Roberts and T. Mudge, ISCA’ 083. Future Outlook of NAND Flash Technology for 40nm Node and Beyond, K. Kim and J. Choi, NVSMW’ 064. Samsung Electronics CO.,LTD. Datasheet of Samsung K9F1208R0B NAND flash, 2004.5. Samsung Electronics CO.,LTD. Datasheet of Samsung K9K2G08X0A NAND flash, 2006.6. A superblock-based flash translation layer for NAND flash memory, Kang, J., Jo, H., Kim, J., and Lee, J, EMSOFT '067. An adaptive two-level management for the flash translation layer in embedded systems, C.-H. Wu, T.-W. Kuo, ICCAD’068. Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design, Chang, Y., Hsieh, J., and

Kuo, T., DAC’ 079. On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems, L.-P. Chang, SAC’0710. An adaptive striping architecture for flash memory storage systems of embedded systems, L.-P. Chang and T.-W. Kuo, RTAS’ 0211. Energy-aware demand paging on NAND flash-based embedded storages, C. Park, J.-U. Kang, S.-Y. Park, and J.-S. Kim., ISLPED’

0412. SWL: a search-while-load demand paging scheme with NAND flash memory, J. In, I. Shin, H. Kim, LCTES’ 0713. SmartSaver: turning flash drive into a disk energy saver for mobile computers, Chen, F., Jiang, S., and Zhang, X., ISLPED’ 0614. Using Data Clustering To Improve Cleaning Performance For Flash Memory, M. L. Chiang, Paul C. H. Lee, and R. C. Chang,

Software - Practice and Experience, 1999.15. An Effective Flash Memory Manager for Reliable Flash Memory Space Management, H. J. Kim and S. G. Lee, IEICE Transactions

on Information and System, 2002.16. A flash-memory based file system., A. Kawaguchi, S. Nishioka, and H. Motoda. , In Proceedings of the 1995 USENIX Technical

Conference, pages 155–164, January 1995.17. M-Systems, TrueFFS Wear-Leveling Mechanism“18. Wear Leveling in Single Level Cell NAND Flash Memories," STMicroelectronics Application Note (AN1822), 2006.19. Samsung K8C1215EBM20. Samsung K9F1G08R0A

Design Issues of Flash-based SSD& Hybrid Disks

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