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Design GoalDesign GoalDesign an Analog-to-Digital Conversion chip Design an Analog-to-Digital Conversion chip to meet demands of high quality voice to meet demands of high quality voice applications such as: Digital Telephony, applications such as: Digital Telephony, Digital Hearing Aids and VOIP.Digital Hearing Aids and VOIP.

TEAM W3:TEAM W3:Digital Voice Processor 525Digital Voice Processor 525

Jarrett Avery (W3-1)Jarrett Avery (W3-1)Sean Baker (W3-2)Sean Baker (W3-2) Huiyi Lim (W3-3)Huiyi Lim (W3-3)

Sherif Morcos (W3-4) Sherif Morcos (W3-4) Amar Sharma (W3-5)Amar Sharma (W3-5)

Date: 3/22/2006

Functional Blocks and Simulation

Design Manager: Abhishek Design Manager: Abhishek JajooJajoo

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StatusStatus Design ProposalDesign Proposal

Project chosen: 16 bit Delta-Sigma ADCProject chosen: 16 bit Delta-Sigma ADC Basic specs definedBasic specs defined

ArchitectureArchitecture Matlab SimulatedMatlab Simulated Behavioral Verilog - SimulatedBehavioral Verilog - Simulated Structural Verilog – SimulatedStructural Verilog – Simulated

SchematicSchematic Digital – All modules createdDigital – All modules created Analog - All modules createdAnalog - All modules created

FloorplanFloorplan Revised for signal routingRevised for signal routing

Layout Layout Op Amps – DRC, LVS, SimulatedOp Amps – DRC, LVS, Simulated Low Pass Filter – DRC, LVS, SimulatedLow Pass Filter – DRC, LVS, Simulated PII – DRC, LVS, SimulatedPII – DRC, LVS, Simulated Sinc Filter – DRC, Not LVS, Not SimulatedSinc Filter – DRC, Not LVS, Not Simulated

Simulation / VerificationSimulation / Verification All modules verified separately at transistor level All modules verified separately at transistor level

and some layoutsand some layouts

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Analog ProgressAnalog Progress

Everything is in Transistor Everything is in Transistor Level and VerifiedLevel and Verified

Layouts and Extracted Views of Layouts and Extracted Views of the Operational Amplifiers the Operational Amplifiers Integrator - Verified Integrator - Verified Comparator – VerifiedComparator – Verified

Reviewed Common Centroid Reviewed Common Centroid Style of LayoutStyle of Layout

More in-depth next week…More in-depth next week…

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Design DecisionsDesign Decisions

Metal DirectionalityMetal Directionality Buffering – Clock to Minimize Buffering – Clock to Minimize

GlitchingGlitching Overall Chip Routing and Signal Overall Chip Routing and Signal

DirectionalityDirectionality Compacted Mirror-adder and Compacted Mirror-adder and

DFF DFF Reviewed Common Centroid Reviewed Common Centroid

Layout – Next Week…Layout – Next Week…

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Clock BufferingClock Buffering

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DFF LayoutDFF Layout

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DFF SimulationsDFF Simulations

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Mirror Adder LayoutMirror Adder Layout

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Mirror Adder Mirror Adder SimulationsSimulations

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24-Bit Counter Layout24-Bit Counter Layout

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24-Bit Counter 24-Bit Counter SimulationsSimulations

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12-Bit Equality Function - 12-Bit Equality Function - LayoutLayout

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12-Bit Equality Function 12-Bit Equality Function SimulationsSimulations

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12-Bit Register - Layout12-Bit Register - Layout

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12-Bit Register 12-Bit Register SimulationsSimulations

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PII Function - LayoutPII Function - Layout

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Sinc Filter -LayoutSinc Filter -Layout

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Timing and PowerTiming and Power

Total = 6,432 transistors, 509.8 uW of power

Block Power Delay Transistors

16-Bit Adder 22.47uW at 5.12MHz 2.856ns 448

16-Bit Subtractor 28.54uW at 5.12MHz13.09uW at 20KHz

2.916ns 480

12-Bit Register 22.41uW at 20KHz 1.065ns 216

16-Bit Register 33.17uW at 5.12MHz29.88uW at 20KHz

1.065ns 228

12-Bit Equality Function 3.323uW at 20KHz 270.5ps 138

16-Bit Multiplexer 2.114uW at 20KHz 24.7ps 96

Clock Divider 4.812uW 241.5ps 334

2nd order Sinc Filter 227.1uW 8.748ns 3296

PII Function 115.9uW 2.950ns 2782

Decimator 347.8uW 8.748ns 6412

Analog Op-Amps 162uW Total (81 uW each)

N/A 11 for Integrator, 9 for Comparator

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FloorplanFloorplan

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Problems and QuestionsProblems and Questions

Layout is very time consumingLayout is very time consuming More metal layers or larger More metal layers or larger

layouts?layouts? Sand in my laptopSand in my laptop

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What's Next…What's Next…

LVS all blocksLVS all blocks Sinc Filter Sinc Filter Analog ComponentsAnalog Components

Global RoutingGlobal Routing Wire Decimation filter and ModulatorWire Decimation filter and Modulator Wire Overall ChipWire Overall Chip

Overall Chip SimulationOverall Chip Simulation Extract and simulate in a mixed Extract and simulate in a mixed

signal env.signal env. OptimizationOptimization