Design for Test - Analog Circuits

8/2/2019 Design for Test - Analog Circuits

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Design for Testability (DFT)


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2009/5/12

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin

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Design for Testability

To increase to controllability and/or observability

Methodology

Reconfiguration

Test point insertion

Checksum

Sub band Filtering

IEEE standard 1149.4


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Reconfiguration

Isolation (Bypassing)

Most used currently Switch (multiplexer) should be carefully designed

Normal

Test functional block 1 Test functional block 2

Analog

function

Analog

function

sel1 sel2


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Reconfiguration

Loop Around Loop around for back-to-back testing

Modulator

De-

modulator

Down-

converter

voice RF

RFvoice

sel1

sel2

Example

CODEC, RF/IF Test

Switch (multiplexer) should be carefully designed

Fault masking


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Reconfiguration

DfT for Switched Capacitor Filter [Soma, VTS94]

In test mode, bypass a filter stage by converting itto an all-pass gain stage

Open grounding switches and close signal path switches

Operated in continuous fashion, not in sampled-datamode (bandwidth extended)

1

42

12

||v

CC

Cv =


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Reconfiguration

SW-OPAMP Type A (1/2) [Huertas, VTS96]

SW-OPAMP

With additional inputs: Test, VT

= 0: regular opamp = 1: unit buffer VT is connected to the output of

previous stage

In test mode

= 0 for stage under test = 1 for others


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Reconfiguration

SW-OPAMP Type A (2/2)

Gain

Phase

Frequency responses oforiginal opamp and sw-opamp

Carefully design for embedded switches is needed to maintain theopamp performance (offset, frequency response, SR, CMRR, )


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Reconfiguration

SW-OPAMP Type B (1/2) [Renovell, EDTC98; J. W. Lin]

Test strategy

C=1: normal operation test

C=0: reconfiguration test

Example

C1 C2 C3 =111

C1 C2 C3 =000

C1 C2 C3 =100


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2009/5/12MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin

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Reconfiguration

SW-OPAMP Type B(2/2) [Crols, JSSC1994]

Switched-Opamp

Additional inputs: C

C= 1: regular opamp

C= 0: power-off opamp

Loading effect due to

large output drive stage

Add switch on output to isolate the large loading Switch in signal path should be carefully designed

VoM1

VDD

VSS

V+V-M2

M8M5

M6

M4M3

M7

5uA

Cc

M10

M9

C

C


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Reconfiguration

Oscillation Test Strategy (1/2) [Kaminska, VTS96]

In test model Partitioning CUT into functional building blocks

Converting each building block to an oscillator

Shift poles on the imaginary axis

Adding a feedback loop to the CUT

Combine various building blocks to form an oscillator

Defects cause deviations in oscillation frequency


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Reconfiguration

Oscillation Test Strategy (2/2)

Example

Continuous-time

state-variablefilter

Excellent for hard and large deviation faults

Adopted by Fluence

Challenges

No universal rules to transfer DUT into oscillator

No trivial relationship between the oscillation frequencyand the specification under test


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Test Point Insertion

Analog Scan -- Voltage-Based [C.L. Wey, TIM90]

Voltage-basedscan cell

Scan Path

-

+

-

+SI

SO

DI

-

+

-

+

- +

-

+

-

+

- +

-

+

-

+

- +

CUT POPI

SISO


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Analog Scan -- Current-Based [Soma, CICC95]

Current-basedscan cell

Gnd

VddI(in)

Shift In Shift Out

CUT POPI

SO

V-I

Converter

V-I

Converter

V-I

Converter

Gnd

Vdd

Gnd

Vdd

Gnd

Vdd

Scan Path


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IDDQ / IDDT Test

Insert current sensor between CUT and

Vdd (Vss) Use current signature to make pass/fail

decision

Compare to: DC threshold (IDDQ) [Stopjakova, 96]

Expected spectrum (IDDT) [Siskos, 97]

Challenges Resistance in Vdd Path

Aliasing


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Output Response Compaction [Bertrand, EDTC97]

Summing or weighted-summing the internal node voltage orbranch current

During Testing

C=0, output is initialized to 0

C=1, performs the integration function

The analog signature provided by the =RC of the integrator

Challenge -- Aliasing


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Checksum

Analog Checksum (1/3) [Chatterjee, D&T96]

For Linear circuit (system)

( ) ( ) )()(

)(

)(

)()(

2

1

2

1

2221

1211

2

1tu

b

b

tx

tx

aa

aa

ttx

ttxtutXttX

+

=

+

++=+ BA

( ) ( ) ( )( ) ( ) ( ) ( ) variablestate:output,:

vectorstate:input,:

txy(t)tutXty

X(t)u(t)tutXttX

DC

BA

+=

+=+

++

++=

+

+

)()()(

)()()(

)(

)(

2222121

1212111

2

1

tubtxatxa

tubtxatxa

ttx

ttx

( ) ( ) ( ) )()()(

)()()()()()()()(

212221212111

2122212121211121

tubbtxaatxaa

tubtubtxatxatxatxattxttx

+++++=

+++++=+++

[ ] [ ] [ ] )()(

)(

)(

0)( 21

3

2

1

221221113 tubb

tx

tx

tx

aaaattxLet ++

++=+

)()()( 213 ttxttxttx +++=+

-1-1

a11+a21

x1 x2

1/s

u y

a12+a22

b1+b2

x3


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Checksum

Analog Checksum (2/3)

Fourth order band passleapfrog filter

Checksum circuit


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Checksum

Analog Checksum (3/3)

Fault free response Faulty response


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Sub-Band Filtering

Sub-Band Filtering (1/3) [Abraham, ITC99]

Motivation

Reducing the aliasingprobability of the integratorscheme by analyzing thesignature for each frequencyband

Signature Analysis Scheme


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Sub-Band Filtering

Sub-Band Filtering (2/3)

Low-pass filtering and down-sampling

Filtering Example


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Sub-Band Filtering

Sub-Band Filtering (3/3)

Recursive Architecture of Filter Bank

Pros -- More immune from fault aliasing problems Cons -- Requires on-chip ADC

Sub-Band Filtering Wavelet


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IEEE Standard 1149.1

Digitalcircuit

TAPcontroller

TDO

TCK

TDI

TMS

Digitalboundary

cells

Digital

boundaryscan path

Digitalpins


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Test Board with Mixed-Signal Parts

The introduction of analog components to 1149.1 compliantchip, the ability to isolate faulty interconnects on the analogI/O pins does not exist!!

The introduction of analog components to 1149.1 compliantchip, the ability to isolate faulty interconnects on the analogI/O pins does not exist!!


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1149.4 -- Mission Statement

To define, document, and promote the use of a

standard mixed-signal test bus that can be used

at the device, sub-assembly, and system levels

to improve the controllability and observability of

mixed-signal designs and to support mixed-signal

built-in test structures in order to reduce

test development time and costs,

and improve test quality.


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Structure of a Basic 1149.4 Chip

TMS

TDI TDO

TCK

AT2

AT1

Digital I/O Pins

Analog I/O Pins

TBIC (Test BusInterface Circuit)

Analog Test Access Port(ATAP = AT1 + AT2)

VHVLVG

VH

VLVG

Internal Analog Bus

(AB1, AB2)

Core

Circuit

Analog Boundary Module(ABM)

Digital Boundary Module(DBM)

Test Control CircuitryTAP Controller

Instruction register and decoder

Digital Test Access Port(TAP ) as in IEEE1149.1

Digital Test Access Port(TAP) as in IEEE1149.1

Boundary Scan Path

Analog Test Stimulus Bus(AT1, AT2)


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Analog Boundary Module (ABM)

Input value can be sensed,digitized (against VTH),

and captured in theregister

Ability to disconnect thereceiving core from the

pin using CD and driveeither a 1 or a 0

ABMs can be

implemented with actualswitches or can beintegral in the analogcircuit

F/F

F/F

TDI

F/F

F/F

GND

Vdd

-

+

VTH

Analogcore

Mode controlfrom TAP

CD

TDO

AB2

AB1


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Test Bus Interface Circuit (TBIC)

VH and VL allowfixed 1 and 0

values (forEXTEST) using S1,S2, S3, S4

ATn disconnected

from ABn via S5, S8

Noise suppression

via S9, S10, Vclampwhen ABn not in

use

- +-+

S9 S10

S5 S8 S7 S6

Vclamp

AB1 AB2

VH

VL

VTH

S1

S4S3

S2

AT1

AT2

Provision forinterconnect test

Bus connectionand calibration


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DfT Strategies Have Potential to

Reduce redundancy

Reduce probabilities of undetectable faults at the

layout level

Improve test access (controllability andobservability)

Reduce demands on production test equipment

Increase resolution of parameter measurement

Provide support for on-line monitoring anddiagnostics


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DfT Principle 1: Precision

[S. Sunter, ITC tutorial #15, 1999]

Definition Measurement sample deviation relative to measurement mean, e.g.

standard deviation (MEAS) of a set of measurements

Sources of imprecision: various noise Signal: thermal or shot noise of source impedance

Other signal: capacitive coupling or via power rail

Test/DfT cct: power supply, coupling, buffers, algorithm Quantization: in converter under test, or ADC of tester

Misc: transmission line reflections at I/O pins

Basic technique to increase precision: integration

The more samples averaged, the better Example

Histogram


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DfT Principle 2: Accuracy

Definition Measurement mean relative to true mean

e.g. average measurement error 100% * (MEAS - 0) /0 Cause of inaccuracy: systematic errors

Wrong gain Offset voltage

Capacitive coupling To increase accuracy: substraction

e.g. measure with/without stimulus, inverted/non-inverted, double-correlated sampling

Example Differential signals, IEEE1149.4 metrology

[S. Sunter, ITC tutorial #15, 1999]

DfT P i i l 3


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DfT Principle 3:Conversion to Digital (without an ADC)

Definition Converting a continuous variable into a binary-coded digital value

Why not use an ADC

Area, design automation Technology and process-dependence, diagnosability How to test the ADC

Examplee.g. convert a delay into an oscillation whose frequency is counted

e.g. compare Vin to voltage from RC, and measure delay

Unknown Delay

Known Delay

Frequency

Counter

Vin

Fref


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General DfT Guidelines

Incorporate DfT features at a early design stage

Partition the circuit in simple and ease to treat macroblocks

Use digital test access port to select test mode

Separate analog and digital circuits Consider the limitation (speed, accuracy, memory, )

of ATE

If possible, incorporate digital circuit rather thananalog one when using DfT techniques


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Reference (1/2)

1. M. Soma & V. Kolarik A Design-for-Test Technique for Switched-Capacitors Filters,, IEEEEuropean Design & Test Conference, pp.42-47, Paris, March 1994

2. D. Vazquez, J. L. Huertas, A. Rueda, Reducing the impact of DFT on the performance ofanalog integrated circuits: improved sw-op amp design, VLSI Test Symposium, pp.42-47,

19963. M. Renovell, F. Azais, Y. Bertrand, Optimized implementations of the multi-configuration DFT

technique for analog circuits, Design, Automation and Test in Europe, pp.815-821, 1998

4. J. Crols, M. Steyaert, Switched-opamp: an approach to realize full CMOS switched-capacitorcircuits at very low power supply voltages, IEEE Journal of Solid-State Circuits, vol.29 Issue 8,

pp.936-942, Aug. 19945. K. Arabi, B. Kaminska, Oscillation-Test Strategy for Analog and Mixed-Signal Integrated

Circuits, VLSI Test Symposium, pp.476-482, 1996

6. K. Arabi, B. Kaminska, Testing Analog and Mixed-Signal Integrated Circuits UsingOscillation-Test Method, IEEE Transactions on Computer-Aided Design of Integrated Circuitsand Systems, vol.16, Issue 7, pp.745-753, July 1997

7. C. L. Wey, Built-in self-test (BIST) structure for analog circuit fault diagnosis, IEEETransactions on Instrumentation and Measurement, vol.39, Issue 3, pp.517-521, June 1990

8. M. Soma, Structure and concepts for current-based analog scan, IEEE Custom IntegratedCircuits Conference, pp.517-520, 1995


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Reference (2/2)

9. M. Sidiropulos, V. Stopjakova, H. Manhaeve, Implementation of a BIC monitor in a newanalog BIST structure, IEEE International Workshop on IDDQ Testing, pp.59-63, 1996

10. S. Siskos, A. A. Hatzopoulos, A simple built-in current sensor for current monitoring inmixed-signal circuits, IEEE Transactions on Instrumentation and Measurement, vol.46,

Issue 6, pp.1301-1304, Dec. 1997

11. M. Renovell, F. Azais, Y. Bertrand, On-chip analog output response compaction,European Design and Test Conference, pp.568-572, 1997

12. A. Chatterjee, B. C. Kim, N. Nagi, DC built-in self-test for linear analog circuits, IEEEDesign & Test of Computers, vol.13, Issue 2, pp.26-33, Summer 1996

13. J. Roh, J. A. Abraham, Subband filtering scheme for analog and mixed-signal circuittesting, International Test Conference, pp.221-229, 1999

14. http://grouper.ieee.org/groups/1149/4/index.html

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