Solid-State Electronics 48 (2004) 1169–1174

www.elsevier.com/locate/sse

Design considerations for novel device architecture:hetero-material double-gate (HEM-DG) MOSFET with

sub-100 nm gate length

Manoj Saxena a, Subhasis Haldar b, Mridula Gupta c, R.S. Gupta c,*

a Department of Physics and Electronics, Deen Dayal Upadhyaya College, University of Delhi, New Delhi 110 015, Indiab Department of Physics, Motilal Nehru College, University of Delhi, New Delhi 110 021, India

c Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, Benito Juarez Road,

New Delhi 110 021, India

Received 1 July 2003; received in revised form 1 October 2003; accepted 2 December 2003

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

The paper presents the results of a systematic analytical characterization, supplemented by 2D device simulation,

applied to novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with effective channel length

down to 30 nm. A new approach to explain the pertinent device physics is presented, which can facilitate device design

and technology selection for enhanced performance. Numerical device simulation data, obtained using 2D device

simulator: ATLAS, for threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing (S) werecompared to the model to validate the analytical formulation. The comparison of symmetric DG (SDG) MOSFET and

HEM-DG MOSFET configurations demonstrated superiority of HEM-DG MOSFET: ideal S and reduced DIBL.Comparison with simulated results reveals excellent quantitative agreement.

� 2004 Elsevier Ltd. All rights reserved.

Keywords: Characterization; Hetero-material gate; DG-MOSFET; DIBL

1. Introduction

As bulk MOSFETs are scaled to below 100 nm in

gate length, the channel doping concentration should be

increased to reduce the short-channel effects (SCEs) but

high doping levels degrades the device performance due

to decreased mobility and increased junction capaci-

tance. In order to control the SCEs, various traditional

methods like scaling the dielectric and reduced junction

depths have been employed but each one of them is now

approaching their fundamental physical limits. An

alternative device architecture, which can suppress SCEs

* Corresponding author. Tel.: +91-11-2410-5580; fax: +91-

011-2688-6606.

E-mail address: rsgu@bol.net.in (R.S. Gupta).

0038-1101/$ - see front matter � 2004 Elsevier Ltd. All rights reserv

doi:10.1016/j.sse.2003.12.009

and can be scaled, further, is needed for the sub-100 nm

device dimensions. One of the most promising solutions

is double-gate (DG) concept [1] in which, the silicon

channel is so thin that it is fully inverted when gate

voltage is applied and this reduces SCEs. In case of

undoped DG devices, control of SCEs is ideally achieved

without the use of channel dopants. As the depletion

charge is zero, the carriers in the inversion layer

encounter a smaller average vertical field in thin-body

device than in standard bulk MOSFET with heavy

channel doping. This reduction in the vertical field is

expected to improve carrier mobility. But continuing

scaling may require the adoption of novel device struc-

tures, which does not rely on the thickness of the silicon

channel or channel engineering for controlling the SCEs.

In order to increase the average electron velocity long

the channel, the average electric field along the channel

ed.

Fig. 1. Schematic diagram of HEM-DG MOSFET. All our

simulation use tox ¼ 2 nm, tsi ¼ 10 nm and 1020 cm�3 n type

source and drain doping and NA ¼ 1015 cm�3, q/M1 ¼ 4:77 eV,

q/M2 ¼ 4:10 eV.

1170 M. Saxena et al. / Solid-State Electronics 48 (2004) 1169–1174

has to increase. This can be achieved by threshold

voltage modulation i.e. making the threshold voltage

function of position or by making use of a new gate

structure-dual material gate (DMG). The dual material

gate (DMG)-FET overcomes problems like (a) SCE and

(b) gate transport inefficiency by modifying the surface

potential profile, which ensures reduction in the SCE and

screening of the channel region under M1 from drain

potential variation [2–4]. In this work, a new structure

hetero-material double-gate (HEM-DG) MOSFET,

which clubs the advantages of DG- and DMG-structure,

is proposed and its 2-D analytical model is presented. In

hetero-material (HEM) DG MOSFET, two adjacent

gates are used having different work function. The gate

closer to the source, M1 (M3), having length L1 is called‘‘control gate’’ has metal-work-function, /M1 and thegate closer to the drain M2 (M4), having length L2 iscalled the ‘‘screen gate’’ has metal-work-function, /M2.

The threshold voltage modulation is produced by

choosing /M1 > /M2 which results in VTH1 > VTH2. Whenthe device is ON then the ‘‘screen gate’’ shields the region

under the ‘‘control gate’’ from any drain voltage varia-

tions and in this way, screen gate absorbs any additional

drain-to-source voltage beyond saturation. This in turn

leads to reduction in DIBL. A well-developed model for

HEM-DG MOSFET should be able to handle (a) Sym-

metric DG (SDG) MOSFET [5], with both gates of same

workfunctions (b) Asymmetric DG (ADG) MOSFET

[6], which has different workfunctions for the gates apart

from HEM-DG MOSFET.

2. Model formulation

In the past scaling properties of DG-MOSFET have

been studied using simplified analytical models [7,8] that

assume parabolic potential profile in the transverse

direction along the channel thickness. In our analysis,

evanescent mode analysis has been employed to study the

SCEs, DIBL (drain induced barrier lowering) and the

subthreshold characteristics. Fig. 1 shows a typical cross-

section of an undoped HEM-DG MOSFET. In case of

undoped devices, the free electrons are evenly spread in

the whole silicon layer resulting in very small vertical

field and therefore, the quantum effects are negligible in

the subthreshold region. The model does not account the

quantum mechanical effects (QMEs) due to the field

confinement and the spatial confinement because in the

undoped devices free electrons are quite evenly spread in

the whole silicon layer resulting in a small vertical electric

field. Therefore, the field confinement in undoped HEM-

DGMOSFET is negligible in the subthreshold region for

gate lengths (L) > 30 nm. Spatial confinement becomessignificant when the channel thickness (tsi) drops muchbelow than 5 nm, where the carrier distribution can be

obtained from solving the Schr€odinger and Poisson’s

equation self-consistently. As, our model for HEM-DG

MOSFET is valid only for channel length (L) P 30 nm

and channel thickness ðtsiÞP 10 nm therefore, account-

ing QMEs is beyond the scope of this work. But, if the Land tsi drops below 20 and 10 nm respectively, then the

QMEs start dominating and cannot be neglected. If the

potential perturbation due to the carrier and doping

concentrations can be ignored then the 2-D potential

distribution Uðx; yÞ in the subthreshold region can bedescribed by 2-D Laplace’s equation

d2Uðx; yÞdx2

þ d2Uðx; yÞdy2

¼ 0 0 < x < a; 0 < y < b ð1Þ

where a ¼ L1 þ L2 and b ¼ tsi þ 2 esieox

� �tox

� �. The para-

meters L1 and L2 are the lengths of metal gate M1 (M3)and M2 (M4) respectively. tox is the oxide thickness, tsi isthe thickness of the silicon channel, esi and eox are thepermittivity of silicon and SiO2 respectively.

The boundary conditions used to evaluate Uðx; yÞ areUðx; 0Þ ¼ VGS � VFB1 0 < x < L1 ð2aÞ

Uðx; 0Þ ¼ VGS � VFB2 L1 < x < L1 þ L2 ð2bÞ

Uðx; bÞ ¼ VGS � VFB3 0 < x < L1 ð2cÞ

Uðx; bÞ ¼ VGS � VFB4 L1 < x < L1 þ L2 ð2dÞ

Uð0; yÞ ¼ Vbi 0 < y < b ð2eÞ

Uða; yÞ ¼ Vbi þ VDS 0 < y < b ð2fÞ

The parameter VGS is the gate-to-source voltage, VDS isthe drain-to-source voltage, VFBiði ¼ 1; 2; 3; 4Þ is the flatband voltage of different metal gates M1, M2, M3 and

M4. If the boundary conditions on all sides of the

rectangle are non-homogeneous then the solution can be

obtained as

Uðx; yÞ ¼ U1ðx; yÞ þ U2ðx; yÞ ð3Þ

M. Saxena et al. / Solid-State Electronics 48 (2004) 1169–1174 1171

Each of the functions U1ðx; yÞ and U2ðx; yÞ has homo-geneous conditions on the parallel boundaries. Using the

boundary conditions (2a)–(2f) U1ðx; yÞ and U2ðx; yÞ canbe expressed as

U1ðx; yÞ ¼X1n¼1

sinnpxa

� �

�cn sinh

npya

� �þ bn sinh

npðb� yÞa

� �

sinhnpba

� �0BB@

1CCAð4aÞ

U2ðx; yÞ ¼X1n¼1

sinnpyb

� �

�tn sinh

npxb

� �þ sn sinh

npða� xÞb

� �

sinhnpab

� �0BB@

1CCAð4bÞ

where

bn ¼2

npðVGSð1� ð�1ÞnÞ � VFB1 þ VFB2ð�1ÞnÞ

þ cos npL1a

� �ðVFB1 � VFB2Þ ð4cÞ

cn ¼2

npðVGSð1� ð�1ÞnÞ � VFB3 þ VFB4ð�1ÞnÞ

þ cos npL1a

� �ðVFB3 � VFB4Þ ð4dÞ

sn ¼2Vbinp

ð1� ð�1ÞnÞ ð4eÞ

tn ¼2ðVbi þ VDSÞ

npð1� ð�1ÞnÞ ð4fÞ

The electrostatic potential in the channel region for DG-

MOSFET is assumed to be parabolic [6–8] in the

transverse direction i.e. normal to the Si/SiO2 interface.

But this method of estimating the 2-D nature of the

channel potential proves to be inaccurate in the scaled

devices. Therefore, 2-D effects should be properly esti-

mated in order to find the minimum gate length for the

device. For undoped HEM-DG MOSFET, the Laplace

equation is solved and the 2-D potential is represented,

in terms of Fourier expansion of various modes, in Eqs.

(4a)–(4f). In this expression the potential decays expo-

nentially both along the lateral and the transverse

direction and not parabolically. In order to avoid cal-

culation of 2-D potential numerically, lowest order

mode (n ¼ 1) can be considered as the higher modes

decay very quickly. Thus, under such approximation the

calculation of various electrical parameters like thresh-

old voltage (VTH), DIBL and subthreshold swing (S) canbe calculated accurately quickly and in terms of various

device dimensions. Further, the 2-D effects become

stronger as channel thickness (tsi) is reduced. Accordingto Eqs. (4a)–(4f), the parameter ‘‘b’’ gives the decaylength of the horizontal electric field and parameter ‘‘a’’gives the decay length of the transverse electric fielding

the channel. Ratio of a=b gives a fundamental measureof the quality of FET and its immunity towards the

threshold voltage roll-off.

Therefore, the expression of the 2-D electrostatic

channel potential is helpful in understanding the device

physics of (1) Symmetric DGMOSFET, (2) Asymmetric

DG MOSFET and, (3) HEM-DG MOSFET through

one model which may not be possible exactly through

numerical device simulations. The analytical expression

for the 2-D potential distribution Uðx; yÞ for HEM-DGMOSFET can also be used to study the various opera-

tion modes of DG-MOSFET i.e. symmetric DG (SDG)

MOSFET and asymmetric DG (ADG) MOSFET.

Case 1: Symmetric DG (SDG) MOSFET

In case of SDG-MOSFET the metal workfunction of

all the metal gates (M1, M2, M3 and M4) should be the

same i.e. VFB1 ¼ VFB2 ¼ VFB3 ¼ VFB4 ¼ VFB.

Case 2: Asymmetric DG (ADG) MOSFET

In case of ADG-MOSFET the metal workfunctions,

and corresponding flat band voltages, of M1 and M2

should be same (VFB1 ¼ VFB2 ¼ VFBU) and similarly forM3 and M4, VFB3 ¼ VFB4 ¼ VFBL but VFBU 6¼ VFBL.

Case 3: Hetero-material-DG (HEM-DG) MOSFET

In case of HEM-DG–MOSFET the metal work-

functions of metal gate M1 and M3 should be same

(VFB1 ¼ VFB3 ¼ VFBS) and similarly for metal gate M2

and M4 should be same (VFB2 ¼ VFB4 ¼ VFBD) but

VFBS > VFBD.The 2-D potential distribution, Uðx; yÞ, for SDG-,

ADG- and HEM-DG MOSFET in the subthreshold

region can be described by substituting the respective

conditions in (4a)–(4f). Fig. 2 shows a comparison of the

potential distribution along the channel for DG- and

HEM-DG MOSFET. It is evident from the figure that

positive offset of the potential for HEM-DG MOSFET

changes its position as the L1=L2 ratio changes.

2.1. Position of minimum electrostatic potential in HEM-

DG MOSFET

The position of minimum electrostatic potential is

very important to determine the threshold voltage (VTH),DIBL and S for the device. In case of undoped

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0 10 20 30 40 50 60 70 80 90Position along the gate length(nm)

Ele

ctro

stat

ic P

oten

tial (

V)

Simulated (DG) VDS = 0.1 VAnalytical (DG) VDS = 0.1VSimulated (DG ) VDS = 0.3 VAnalytical (DG ) VDS = 0.3 VSimulated (HEM-DG) VDS = 0.1 VAnalytical (HEM-DG) VDS = 0.1 VSimulated (HEM-DG) VDS = 0.3 VAnalytical (HEM-DG) VDS = 0.3 V

Fig. 2. Electrostatic potential along the channel length for

HEM-DG MOSFET and DG-MOSFET. VGS ¼ �0:4 V. ForDG-MOSFET L ¼ 90 nm, q/M ¼ 4:77 eV and for HEM-DG

MOSFET ðL ¼ L1 þ L2ÞL1 ¼ 45 nm, L2 ¼ 45 nm and q/M1 ¼4:77 eV, q/M2 ¼ 4:10 eV.

1172 M. Saxena et al. / Solid-State Electronics 48 (2004) 1169–1174

DG-MOSFET, only 2-D effects determine the channel

potential and the position of minimum channel potential

along the silicon channel thickness, yc, and can be ob-tained by solving

dUðx; yÞdy

¼ 0 at x ¼ L12

ð5aÞ

On substituting (4a)–(4f) in (5a), the value of yc can bedetermined accurately by solving

X1n¼1

npa

� �sin

npL12a

� �

�cn cosh

npyca

� �� bn cosh

npðb� ycÞa

� �

sinhnpba

� �0BB@

1CCA

þX1n¼1

npb

� �sin

npycb

� �

�tn sinh

npL12b

� �þ sn sinh

nða� L1Þ2b

� �

sinhnpab

� �0BB@

1CCA ¼ 0

ð5bÞ

For SDG-, ADG- and HEM-DG MOSFET, the posi-

tion of minimum channel potential along the channel

length, xmin, can be obtained as follows

dUðx; yÞdx

¼ 0 at y ¼ yc ð6aÞ

On substituting (4a)–(4f) in (6a), the value of xmin can beobtained numerically by solving

X1n¼1

npa

� �cos

npxmina

� �

�cn sinh

npyca

� �þ bn sinh

npðb� ycÞa

� �

sinhnpba

� �0BB@

1CCA

þX1n¼1

npb

� �sin

npycb

� �

�tn cosh

npxminb

� �� sn cosh

npða� xminÞb

� �

sinhnpab

� �0BB@

1CCA

¼ 0 ð6bÞ

The series in Eqs. (5b) and (6b) are quickly converging

and the first three or four terms are sufficient to obtain ycand xmin accurately. In HEM-DG MOSFET, the posi-

tion of xmin, lies under the metal gate M1 (M3) becauseVFBS > VFBD and therefore, the effective gate voltage

under the M1 region is less than that for region M2.

2.2. Threshold voltage model

In this section, we provide a general and compact

analytical formulation of threshold voltage (VTH) modelfor SDG-, ADG-, and HEM-DG MOSFET. Threshold

voltage is that gate voltage when the minimum 2D

electrostatic potential, Umin, meets the given condition

Umin ¼ Uðxmin; ycÞ ¼ 2/F, where /F is the Fermi poten-

tial and

Uðxmin; ycÞ

¼X1n¼1

sinnpxmin

a

� �

�c0n sinh

npyca

� �þ b0n sinh

npðb� ycÞa

� �

sinhnpba

� �0BB@

1CCA

þX1n¼1

sinnpycb

� �

�tn sinh

npxminb

� �þ sn sinh

npða� xminÞb

� �

sinhnpab

� �0BB@

1CCAð7aÞ

b0n ¼2

npðVTHð1� ð�1ÞnÞ � VFB1 þ VFB2ð�1ÞnÞ

þ cos npL1a

� �ðVFB1 � VFB2Þ ð7bÞ

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

25 35 45 55 65 75Channel Length (nm)

Thre

shol

d Vo

ltage

(V)

0

20

40

60

80

100

120

25 35 45 55 65 75Channel Length (nm)

DIB

L (m

V/V)

DG (Simulated)DG (Analytical)11 HEM-DG (Simulated)11 HEM-DG (Analytical)13 HEM-DG (Simulated)13 HEM-DG (Analytical)

Fig. 3. Threshold voltage versus channel length for HEM-DG

MOSFET and DG-MOSFET. These VTH are for VDS ¼ 0:1 V,

tox ¼ 2 nm, tsi ¼ 10 nm. For DG-MOSFET L ¼ 90 nm,

q/M ¼ 4:77 eV and for HEM-DG MOSFET (L ¼ L1 þ L2)L1 ¼ 45 nm, L2 ¼ 45 nm and q/M1 ¼ 4:77 eV, q/M2 ¼ 4:10 eV.

(Inset): DIBL variation for HEM-DG MOSFET and DG-

MOSFET for different gate lengths. For HEM-DG MOSFET

11 signifies L1 : L2 ¼ 1 : 1 and 13 signifies L1 : L2 ¼ 1 : 3.

M. Saxena et al. / Solid-State Electronics 48 (2004) 1169–1174 1173

c0n ¼2

npðVTHð1� ð�1ÞnÞ � VFB3 þ VFB4ð�1ÞnÞ

þ cos npL1a

� �ðVFB3 � VFB4Þ ð7cÞ

The magnitude of minimum surface potential is assumed

to be 2/F for undoped devices (dopant concentration

1015 cm�3) if both the induced and the depleted char-

ges are neglected in the derivation of the threshold

voltage model. The approximation holds quite well for

DG-MOSFET however, the deviation due to approxi-

mation is not negligible for extremely short-channel

devices (L < 30 nm) and thin-channel thickness (tsi < 10

nm) and may give inaccurate values of potential in the

channel region. Further more, if the dopant concentra-

tion drops at a level of 1014 cm�3 then the assumption

that threshold occurs when the inverted channel con-

centration is equal to the channel dopant concentration

fails to hold good. Therefore, the analytical results ob-

tained from our model will deviate in any one of the

following cases

i. Channel length (L) < 30 nm.ii. Channel thickness (tsi) < 10 nm.iii. Channel doping concentration (NA) is less than

1015 cm�3.

2.3. Subthreshold swing

The subthreshold current, is the leakage current that

affects dynamic circuits and determines the CMOS

standby power. For a device to have good turn-on

characteristics, S should be as small as possible [9]. ForSDG-, ADG-, and HEM-DG MOSFET negligible

interface density has been assumed. As the subthreshold

current is proportional to expðkT Uminq Þ, the subthreshold

swing (S) in terms of minimum electrostatic potential

Umin, is expressed as

S ¼ kTqlnð10Þ oVGS

oUmin

ð8Þ

where, k is the Boltzman constant and T is the temper-ature in Kelvin.

3. Results and discussion

According to Fig. 3, threshold voltage, VTH, of theHEM-DG MOSFET is lower than DG-MOSFET and

this gives more freedom for optimization of substrate

doping under M2. For smaller L1=L2 ratio, the electro-static potential change increases by scaling down L1, i.e.the length of the charge control region and the effective

length of the HEM-DG MOSFET also reduces thereby

decreasing the threshold voltage. The analytical results

are in close proximity with the results obtained by the

ATLAS device simulator [10]. DIBL is calculated as VTH(VDS ¼ 0:1 V))VTHðVDS ¼ 1:0 V). DIBL for HEM-DG

MOSFET is smaller than that of DG-MOSFET because

M2 region screens M1 region from any drain potential

variation and is shown in Fig. 3 (Inset). Therefore, the

minimum channel potential of the former undergoes

much less variation in comparison to SDG-MOSFET.

In hetero-material (HEM) DG MOSFET, when the

device is ON then the ‘‘screen gate’’ shields the region

under the ‘‘control gate’’ from any drain voltage varia-

tions and in this way, screen gate absorbs any additional

drain-to-source voltage beyond saturation. This in turn

leads to reduction in DIBL. But it is well known that in

subthreshold region of operation, the drain current is

dominated by the diffusion current and, subthreshold

slope (S) is inversely proportional to effective length

(Leff ). In case of conventional DG-MOSFET, the (LeffDG)changes with the drain voltage only but, in case of

HEM-DG MOSFET LeffHEM-DG is the length of the

‘‘control gate’’. Therefore, as the L1 : L2 ratio decreases,keeping total channel length (L ¼ L1 þ L2) constant, Sincreases which results in higher value of S for HEM-DG MOSFET in comparison to DG-MOSFET.

Fig. 4 shows the variation of S, the parameter thatevaluates the sensitivity of the surface potential to the

variation in the gate voltage, with the gate length.

Degradation in S is slightly smaller in case of DG

55

65

75

85

95

25 35 45 55 65 75

Channel length (nm)

S (m

V/de

c)

DG (Simulated)DG (Analytical)11 HEM-DG (Simulatedl)11 HEM-DG (Analytical)13 HEM-DG (Simulated)13 HEM-DG (Analytical)

Fig. 4. Comparison of subthreshold swing between 2D device

simulation results and model for various ratio of L1=L2 forHEM-DG MOSFET for VDS ¼ 0:1 V, tox ¼ 2 nm, tsi ¼ 10 nm,

q/M1 ¼ 4:77 eV, q/M2 ¼ 4:10 eV. For HEM-DG MOSFET 11

signifies L1 : L2 ¼ 1 : 1 and 13 signifies L1 : L2 ¼ 1 : 3.

1174 M. Saxena et al. / Solid-State Electronics 48 (2004) 1169–1174

structure than for the HEM-DG MOSFET. In this

work, we will adopt the criterion for acceptable short-

channel behavior, and S, as established in [11]. Thiscriterion is DIBL¼ 150 mV and S ¼ 100 mV/decade.

The threshold voltage (VTH) roll-off increases with

reduction in the channel length (L). The threshold volt-age of undoped HEM-DG MOSFET is independent of

the dopant concentration in the channel but depends

upon the metal work functions and lengths of ‘‘control

gate’’ and ‘‘screen gate’’. As the L1 : L2 ratio decreasesthe change in the magnitude of the minimum channel

potential is more, causing increase in VTH roll-off, in

comparison to the larger values of L1 : L2 ratio. There-fore, the effect is more pronounced in HEM-DG

MOSFET having smaller L1 : L2 ratio, in comparison tothe DG-MOSFET. Therefore HEM-DG MOSFET

gives an advantage of reducing DIBL in comparison to

DG-MOSFET but at the same time S increases. Basedon Figs. 3 and 4, HEM-DG MOSFET can suppress

SCEs effectively and thus could be a promising candi-

date for future nanometer devices.

4. Conclusion

A simple and accurate analytical model derived from

fundamental device physics for HEM-DG MOSFET is

presented for the first time. Within an acceptable SCEs

and S, the optimum design space of the HEM-DG

MOSFET is examined in comparison to the DG-

MOSFET. The efficiency of the new structure depends

on the metal workfunction and ratio of L1=L2. For in-stance, for smaller ratio of L1=L2, the value of S increaseswhereas the DIBL reduces in very short-channel range.

Because of its functional form and computational effi-

ciency, this model is suitable for the guidelines of tech-

nology design and can be used in circuit simulation for

enhanced performance.

Acknowledgements

The authors are grateful to the Defense Research

and Development Organization, Ministry of Defense,

Government of India, for necessary financial assistance

to carry out this research work. The authors are grateful

to Dr. Ciby Thuruthiyil, Technology Development

group, Advanced Micro Devices Corporation, Sunny-

vale, CA 94088, USA for his help during the progress of

the work.

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