Design and Practical Implementation of Digital Auto-Tuning ... · In switched-mode power supplies...

Design and Practical Implementation of Digital

Auto-Tuning and Fast-Response Controllers

for Low-Power Switch-Mode Power Supplies

by

Zhenyu Zhao

A thesis submitted in conformity with the requirements

for the degree of Doctor of PhilosophyGraduate Department of Electrical and Computer Engineering

University of Toronto

Copyright c© 2008 by Zhenyu Zhao

Abstract

Design and Practical Implementation of Digital

Auto-Tuning and Fast-Response Controllers

for Low-Power Switch-Mode Power Supplies

Zhenyu Zhao

Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering

University of Toronto

2008

In switched-mode power supplies (SMPS), a controller is required for output voltage

or current regulation. In low-power SMPS, processing power from a fraction of watt to

several hundred watts, digital implementations of the controller, i.e. digital controllers

have recently emerged as alternatives to the predominately used analog systems. This

is mostly due to the better design portability, power management capability, and the

potential for implementing advanced control techniques, which are not easy to realize

with analog hardware.

However, the existing digital implementations are barely functional replicas of

analog designs, having comparable dynamic performance if not poorer. Due to strin-

gent constraints on hardware requirements, the digital systems have not been able

to demonstrate some of their most attractive features, such as parameter estimation,

controller auto-tuning, and nonlinear time-optimal control for improved transient re-

sponse.

This thesis presents two novel digital controllers and systems. The first is an

auto-tuning controller that can be implemented with simple hardware and is suitable

for IC integration.

ii

The controller estimates power stage parameters, such as output capacitance,

load resistance, corner frequency and damping factor by examining the amplitude

and frequency of intentionally introduced limit cycle oscillations. Accordingly, a

digital PID compensator is automatically redesigned and the power stage is adapted

to provide good dynamic response and high power processing efficiency. Compared to

state of the art analog solutions, the controller has similar bandwidth and improves

overall efficiency.

To break the control bandwidth limitation associated with the sampling effects

of PWM controllers, the second part of the thesis develops a nonlinear dual-mode

controller. In steady state, the controller behaves as a conventional PWM controller,

and during transients it utilizes a continuous-time digital signal processor (CT-DSP)

to achieve time-optimal response. The processor performs a capacitor charge balance

based algorithm to achieve voltage recovery through a single on-off sequence of the

power switches. Load transient response with minimal achievable voltage deviation

and a recovery time approaching physical limitations of a given power stage is obtained

experimentally.

iii

Dedication

To the memories of my mother and my grandmother.

iv

Acknowledgements

I would like to express my special thanks to my supervisor, Professor Aleksandar

Prodic, for his invaluable advice, his guidance, and his financial support all through-

out my Ph.D. study. Also, financial supports from Ontario Graduate Scholarship pro-

gram and the Natural Science and Engineering Research Council of Canada through

the Post Graduate Scholarship are gratefully acknowledged.

I am also greatly indebted to my wife Ran for her patience and understanding in

the past few years.

My thanks also go to all the students of my group for their help and suggestions.

In particular, I would like to thank Zdravko Lukic who worked with me together on

several projects.

Finally, I will like to express my gratitude to the students and professors of this

department, especially those in the Energy Systems Group. It has been a wonderful

experience studying and working with all of you.

v

Table of Contents

1 Introduction 1

1.1 Low-Power SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Voltage-Mode Controllers for Low-Power SMPS . . . . . . . . . . . . 2

1.3 Auto-Tuning Controllers . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Dynamic Response of Digital Controllers for Low-Power SMPS . . . . 4

1.5 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.6 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Previous Art and Motivations 8

2.1 Analog Controllers for SMPS . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 PWM Voltage-Mode Controllers . . . . . . . . . . . . . . . . . 9

2.1.2 PWM Current-Mode Controllers . . . . . . . . . . . . . . . . 11

2.1.3 Hysteretic Controllers . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Digital Controllers for Low-Power SMPS . . . . . . . . . . . . . . . . 14

2.2.1 Digital PWM Voltage-Mode Controllers . . . . . . . . . . . . 14

2.2.2 Digital Compensator Design Methods . . . . . . . . . . . . . . 15

2.3 Auto-Tuning Controllers for Low-Power SMPS . . . . . . . . . . . . . 17

2.3.1 Auto-Tuning Controller Based on PRBS Frequency-Domain Iden-

tification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

vi

2.3.2 Linear Predictor based Auto-Tuning . . . . . . . . . . . . . . 20

2.3.3 Relay-Feedback based Auto-Tuning . . . . . . . . . . . . . . . 20

3 Limit-Cycle Oscillation based Auto-Tuning System 22

3.1 System Architecture and Operation . . . . . . . . . . . . . . . . . . . 24

3.2 Parameter Estimation from Limit-Cycle Oscillations . . . . . . . . . . 26

3.2.1 LCO Based System Identification . . . . . . . . . . . . . . . . 28

3.2.2 Measurements of LCO Features . . . . . . . . . . . . . . . . . 32

3.2.3 Relations between LCO Features and Power Stage Parameters 34

3.3 Programmable PID Compensator and Load Estimator . . . . . . . . 42

3.3.1 Compensator Design and Tuning . . . . . . . . . . . . . . . . 42

3.3.2 Programmable PID Implementation via Look-Up Tables . . . 51

3.3.3 Load Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.4.1 Auto-Tuning Examples . . . . . . . . . . . . . . . . . . . . . . 55

3.4.2 Improved Transient Response with Proposed PID Design Method 59

3.5 System Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.5.1 Load Estimation . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.5.2 Compensator Design Considerations . . . . . . . . . . . . . . 64

3.6 General Limitations of PWM Voltage-Mode Controllers . . . . . . . . 68

4 Continuous-Time Digital Controller 70

4.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.2 Optimal Recovery Time Algorithm . . . . . . . . . . . . . . . . . . . 74

4.3 Practical Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.3.1 Application Specific CT-DSP . . . . . . . . . . . . . . . . . . 78

4.3.2 Optimal Sequence Generator . . . . . . . . . . . . . . . . . . . 84

vii

4.3.3 Influence of the Output Capacitor and LC Parameter Variations 85

4.4 Experimental Systems and Results . . . . . . . . . . . . . . . . . . . 88

4.4.1 Functional Verification . . . . . . . . . . . . . . . . . . . . . . 88

4.4.2 Performance Comparison . . . . . . . . . . . . . . . . . . . . . 90

4.4.3 System Behavior for Parameter Variations . . . . . . . . . . . 94

4.5 Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5 Conclusions and Future Work 98

5.1 Limit-Cycle Oscillation based Auto-Tuning

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.2 Continuous-Time Dual-Mode Controller . . . . . . . . . . . . . . . . 99

5.3 Limitations and Comparison of the Two Controllers . . . . . . . . . . 100

5.4 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Appendices

A Matlab Routines Used in Thesis 104

A.1 Matlab Routine for Compensator Design . . . . . . . . . . . . . . . . 104

A.2 Matlab Routine for RLS Identification . . . . . . . . . . . . . . . . . 108

B Two-Step Tuning Procedure 111

B.1 Two-Step Tuning Concept . . . . . . . . . . . . . . . . . . . . . . . . 111

B.2 System Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

C RLS based Parameter Estimation of SMPS 117

C.1 RLS Method for Parameter Estimation . . . . . . . . . . . . . . . . . 118

C.1.1 Model Selection and the RLS Algorithm . . . . . . . . . . . . 118

C.1.2 Design of Experiment . . . . . . . . . . . . . . . . . . . . . . . 121

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C.1.3 Parameter Estimation Conditions . . . . . . . . . . . . . . . . 121

C.1.4 System Validation . . . . . . . . . . . . . . . . . . . . . . . . . 122

C.2 Practical Issues and Design Considerations . . . . . . . . . . . . . . . 123

C.2.1 Other Alternative REM for Simplification . . . . . . . . . . . 123

Bibliography 125

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List of Tables

3.1 Implementation Comparison of Auto-Tuning SMPS Controllers . . . . 55

4.1 Controllers’ Load Transient Response Comparison . . . . . . . . . . . 94

C.1 Parameter Estimation Results . . . . . . . . . . . . . . . . . . . . . . 123

x

List of Figures

2.1 Block diagram of a voltage-mode controlled SMPS . . . . . . . . . . . 10

2.2 A typical analog voltage-mode PWM controller . . . . . . . . . . . . 10

2.3 Block diagram of a current-mode controlled SMPS . . . . . . . . . . . 11

2.4 A Hysteretic voltage mode controller for SMPS . . . . . . . . . . . . 13

2.5 A digitally controlled voltage-mode SMPS . . . . . . . . . . . . . . . 15

3.1 An SMPS with LCO-based auto-tuning system . . . . . . . . . . . . . 23

3.2 LCO-based auto-tuning controller regulating operation of a buck con-

verter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.3 A typical waveform of limit-cycle oscillations . . . . . . . . . . . . . . 28

3.4 A model of the LCO-based auto-tuning system during system identifi-

cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.5 Flowchart of the limit-cycle initiation and system identification process 32

3.6 Frequency extractor block diagram . . . . . . . . . . . . . . . . . . . 34

xi

3.7 Relations between LCO features, including frequency (top) and am-

plitude (bottom), and the power stage physical parameters, including

load resistance R and capacitance C. Power stage parameters are

L = 33 µH , RL = 0.1 Ω, Vg = 8 V , and Vout = 3.3 V : (a) calculated

frequency of LCO; (b) measured frequency of LCO; (c) calculated am-

plitude of LCO; (d) measured amplitude of LCO. . . . . . . . . . . . 40

3.8 Comparison of the experimentally obtained data for LCO features with

analytical results: (a) dependence of LCO peak-peak amplitude on

the output load resistance when output capacitance C = 38 µF ; (b)

dependence of LCO frequency on the output capacitance value when

output load resistance R = 5 Ω. . . . . . . . . . . . . . . . . . . . . . 41

3.9 Root locus of the total loop T (s) = C(s)Gvd(s): (a) ideal pole-zero

cancellation case; (b) unmatched pole-zero cancellation case. . . . . . 46

3.10 Root locus of the total loop T (s) = C(s)Gvd(s) with a PID compen-

sator designed to provide better damping to the system . . . . . . . . 47

3.11 Modified root locus with respect to varying power stage damping factor. 48

3.12 Approximated gain plots of the characteristic of Gvd(s), C(s) and T (s). 50

3.13 Block diagram of programmable PID compensator and load estimator 53

3.14 Auto-tuning process after a sudden output capacitance change Vg = 8

V, C = 38 µF, L = 33 µH, fsw = 400 kHz. The limit cycle oscillations

of four least significant bits of dc[n] (digital channels D0-D3) are used

for parameter estimation. . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.15 Zoomed-in view of the output voltage waveform and the four least

significant bits of the control signal dc[n] during LCO phase. . . . . . 56

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3.16 Experimental load transient response of conventional controller for the

output load changes between 1.3A and 3A; Vg = 8 V, C = 38 µF,

L = 33 µH, fsw = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . 58

3.17 Experimental load transient response of the auto-tuned controller for

the output load changes between 1.3 A and 3 A; Vg = 8 V, C = 38 µF,

L = 33 µH, fsw = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . 58

3.18 Experimental load transient response showing operation of the load

estimator and the process of efficiency optimization through a selection

of switching sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.19 Load transient responses obtained with two PID designs: (a) conven-

tional PID response with pole-zero cancellation; (b) proposed new PID

with improved system damping. Load changes from 4A to 0 A; Vg = 12

V, Vref = 1.8 V, C = 200 µF, L = 1.5 µH, fsw = 500 kHz. . . . . . . 60

3.20 Time-domain simulations of the system of Fig. 3.1 for the case when

the load is a current sink whose value changes from 0 A to 1 A. . . . 63

3.21 Magnitude and phase characteristics of the uncompensated and com-

pensated buck converter for the cases when the frequency of a zero

introduced by Resr is around the desired crossover frequency of the

system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.22 Time-domain simulations of the closed-loop operation of the system of

Fig. 3.2 when Resr is not negligible; Top: the output voltage vout(t)

during a light to heavy load transient (0.65 A to 1.3 A); Bottom: vout(t)

during a heavy to light load transient (1.3 A to 0.65 A). . . . . . . . 67

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3.23 Magnitude and phase characteristics of the uncompensated and com-

pensated buck converter for the cases when the frequency of a zero

introduced by equivalent series resistance is close to the corner fre-

quency of the power stage. . . . . . . . . . . . . . . . . . . . . . . . . 68

4.1 Continuous-time digital controller regulating operation of a buck con-

verter (top); a simplified structure of the continuous-time digital signal

processor (CT-DSP) used for fast voltage recovery (bottom). . . . . . 73

4.2 Optimal recovery after a disturbance causing the output voltage drop.

Top: the output capacitor voltage, v(t); middle: gate-drive control

signal c(t); bottom: inductor and load currents iL(t) and iload(t). . . 76

4.3 The architecture of the application-specific continuous-time digital sig-

nal processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.4 Main signals of the application-specific continuous-time digital signal

processor during a voltage dip. Top: output voltage; bottom five:

continuous-time digital outputs. . . . . . . . . . . . . . . . . . . . . . 80

4.5 Signals of the CT-DSP during a voltage dip. Top to bottom: output

voltage v(t) , inductor current iL(t), the output of the last triggered

comparator bi(t), corresponding continuous-time digital signal y∗i (t),

the optimal switching sequence u(t). . . . . . . . . . . . . . . . . . . 83

4.6 Optimal sequence generator. . . . . . . . . . . . . . . . . . . . . . . 85

4.7 Circuit model of the output filter of a buck converter that includes

capacitor ESR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

xiv

4.8 Signals of the CT-DSP during a 0.2 A to 1.2 A load transient. Ch.1:

Output voltage v(t), 200 mV/div; Ch 2: gate-drive signal u(t); Ch.3:

control signal for load transient circuit; D0-D3: binary-weighted continuous-

time digital error e∗(t) of the PID compensator; D6: mode control

signal m(t); D7: peak detection signal st(t). Time scale is 2 µs/div. 89

4.9 Voltage and current waveforms of the experimental system during a

0.2 A to 1.2 A load transient. Ch.1: Output voltage v(t), 150 mV/div

- ac; Ch.2: the control signal of a load change circuit; Ch.3: Gate

drive signal; Ch.4: Inductor current iL(t), 1 A/div - dc; Time scale is

5 µs/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.10 PID controller’s response to a 0.2 A to 1.2 A load step change. Ch.1:

output voltage v(t), 150 mV/div - ac; Ch.2: load change command;

Ch.3: gate drive signal, 2.5 V/div; Ch.4: inductor current iL(t), 1

A/div. Time scale is 20 µs/div. . . . . . . . . . . . . . . . . . . . . . 92

4.11 CT-DSP controller’s response to a 0.2A to 1.2A load step change. Ch.1:




4.12 PID controller’s response to a 1.2 A to 0.2 A load step change. Ch.1:




4.13 CT-DSP controller’s response to a 1.2 A to 0.2 A load step change.

Ch.1: output voltage v(t), 150 mV/div - ac; Ch.2: load change com-

mand; Ch.3: gate drive signal, 2.5 V/div; Ch.4: inductor current iL(t),

1 A/div. Time scale is 20 µs/div. . . . . . . . . . . . . . . . . . . . . 93

xv

4.14 CT-DSP controller’s response to a 0.2 A to 1.2 A load step change for

the case when the output capacitance is 20 % smaller than the rated

value. Ch.1: output voltage v(t), 150 mV/div - ac; Ch.2: load change

command; Ch.3: gate drive signal, 2.5 V/div; Ch.4: inductor current

iL(t), 1 A/div. Time scale is 20 µs/div. . . . . . . . . . . . . . . . . . 95

4.15 CT-DSP controller’s response to a 0.2 A to 1.2 A load step change for

the case when the capacitor ESR is 7 times larger (Resr ≈ 35 mΩ).

Ch.1: output voltage v(t), 150 mV/div - ac; Ch.2: load change com-

mand; Ch.3: gate drive signal, 2.5 V/div; Ch.4: inductor current iL(t),

1 A/div. Time scale is 20 µs/div. . . . . . . . . . . . . . . . . . . . . 96

B.1 Block diagram of the two-step tuning controller . . . . . . . . . . . . 111

B.2 Bode plots of systems during second step tuning . . . . . . . . . . . . 114

B.3 Input (bottom) and output (top) of the nonlinear element (DPWM

quantizer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

B.4 Transient response of the auto-tuned system to a load current change

from 0.4A to 1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

C.1 Estimates of the parameters of a buck converter model when the RLS

method is used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

xvi

List of Abbreviations

ADC: Analog-to-Digital Converter

CT-DSP: Continuous-Time Digital Signal Processor

DPFM: Digital Pulse-Frequency Modulator

DPWM: Digital Pulse-Width Modulator

ESR: Equivalent Series Resistance

LCO: Limit Cycle Oscillations

LS: Least Square

PE: Parameter Estimation

PES: Persistent Exciting Signal

PI: Proportional-Integral

PID: Proportional-Integral-Derivative

POL: Point of Load

PWM: Pulse Width Modulation

REM: Recursive Estimation Methods

RLS: Recursive Least Square

SI: System Identification

SMPS: Switch-Mode Power Supplies

VRM: Voltage Regulator Modules

xvii

List of Symbols

ALC amplitude of limit cycle oscillation

App peak-to-peak amplitude of limit cycle oscillation

d: duty ratio

dc: duty ratio command

e: error signal

fLC : limit cycle oscillation frequency

fsw: switching frequency

iL: inductor current

iload: load current

Resr: capacitor equivalent series resistance

s: Laplace transform variable

t: continuous time

TLC : period of limit cycle oscillation

vout: output voltage

vg: input voltage

vref : reference voltage

ωLC : radian frequency of limit cycle oscillation

ωo: center frequency

ωc: cut-off frequency

z: z transform variable

xviii

Chapter 1

Introduction

The subject of this thesis is the design and practical implementation of digital auto-

tuning and fast-response voltage-mode controllers for low-power dc-dc switched-mode

power supplies (SMPS). The auto-tuning of low-power SMPS improves their dynamic

characteristics as well as power processing efficiency and introduces features such as

“state-of-health monitoring” and “plug-and-play operation”, previously not used in

the targeted systems. Decreasing the response time of controllers allows power stage

minimization.

1.1 Low-Power SMPS

Low-power switched-mode power supplies (SMPS) discussed in this thesis provide well

regulated voltage and/or current for numerous electronic devices. The applications

include miniature battery-powered devices, computers, telecommunication systems,

consumer electronics, automotive and avionics electronics, lighting applications and

other equipment that consumes power ranging from a fraction of watt to several

hundreds of watts. Compared to the previously used linear supplies, SMPS have much

1

Chapter 1. Introduction 2

higher power processing efficiency, which often exceeds 90%, smaller dimensions, and

can be implemented at a lower cost [1].

A voltage controlled SMPS consists of two main parts: a power stage, i.e. switch-

ing converter, and a controller. The power stage has several semiconductor devices

operating as power switches and an LC filtering network [1].

1.2 Voltage-Mode Controllers for Low-Power SMPS

A controller is usually required to regulate the output of the power supply, which in

most cases is the output supply voltage.

In dc-dc SMPS, the controller usually needs to satisfy the following requirements:

• It has to provide tight output voltage regulation, that is, to minimize the steady-

state voltage deviation with regard to a constant reference over a large range of

load variations. The reference value is application dependent and, in the tar-

geted systems, can vary between sub 1 V values, used for modern microproces-

sors, to several hundred volts utilized in back-panel lights for LCD monitors.

• It needs to provide a quick recovery to steady-state after output voltage distur-

bances, most often caused by sudden changes of the output load. This feature

is usually known as a fast transient response. The fast transient response allows

power stage optimization through the utilization of small filtering components,

in particular the output capacitor.

• Its power consumption needs to be low, so that it does not affect the overall effi-

ciency of the SMPS. In very low power applications, such as the power supplies

used in cell phones, the total power budget of the controller is often measured

in microwatts.


• In the targeted cost-sensitive applications, the hardware required for the con-

troller implementation needs to be very simple.

Conventionally, these requirements are satisfied by employing an analog voltage

mode pulse-width modulation controller [1]. The controller, which usually consists

of a sensing circuit, a pulse-width modulator, and a compensator, is a fairly simple

circuit. It can be implemented with a few operational amplifiers, comparators and

several passive components. The whole design occupies a small silicon area and

exhibits low power consumption.

However, in modern low-power systems, the analog controller implementation

also causes several problems. Unlike digital designs, analog circuits have poor design

portability, meaning that their transfer from one implementation technology to an-

other usually requires a complete redesign of the whole circuit. In modern low-power

systems, where the implementation technology and requirements for power supplies

practically change on a daily basis, this is a significant concern.

Recent publications [2–5] show that the implementation of digital controllers for

low power SMPS is a feasible alternative to analog solutions. They demonstrate novel

low-power hardware-efficient architectures that can support operation at switching

frequencies exceeding tens of MHz [4]. Except from the fact that they offer design

portability and have lower sensitivity to component variations, in most cases, the pre-

sented controllers have a performance similar to those of analog solutions. They are

designed as functional replicas of analog solutions and, at best, have dynamic response

comparable to that of their counterparts. Due to stringent hardware requirements,

the superior flexibility and computational power of digital systems are rarely used.

The exceptions are low-power digital controllers with current estimation [6], load de-

pendent multi-mode operation [7,8], and dynamic non-overlapping time adjustments


for minimizing the switching losses [9]. Still, auto-tuning and auto-compensation,

arguably the most attractive features of digital control, have not been utilized.

1.3 Auto-Tuning Controllers

The auto-tuning controllers can monitor or estimate system parameters and accord-

ingly adjust their own mode of operation to improve dynamic performance, overall

system efficiency, as well as reliability.

For example, in “mission-critical” power systems such as those in aircrafts, satel-

lites, and medical applications, they can perform real-time “state-of-health monitor-

ing” where component degradation/aging and other possible sources of failures are

detected and a preventive action is taken in advance.

Furthermore, the auto-tuning system can be used for the development of universal

“plug and play” digital controllers.

The main challenge in implementing auto-tuning controllers for low-power SMPS

is hardware complexity. Existing auto-tuning systems used in large-scale systems

[10, 11] are not suitable for the targeted applications. Usually, they use hardware

whose complexity and power consumption exceed that of a complete low power dc-dc

converter. This is mostly due to the use of powerful microprocessors, required to

implement complex auto-tuning algorithms [10–13].

1.4 Dynamic Response of Digital Controllers for

Low-Power SMPS

In some applications, existing voltage-mode digital controllers also suffer from unsatis-

factory dynamic performance. This is a serious problem in point-of-load (PoL) power


supplies where a fast dynamic response to load changes is of utmost importance for

the proper operation of the sensitive loads [14]. For example, nowadays power supplies

for computer microprocessors, also known as voltage regulator modules (VRM), are

required to respond to load changes with a slew-rate of 80-120 A/µs [15] to maintain

proper processor operation. Such a fast response is difficult, or almost impossible,

to achieve with conventional voltage mode controllers combined with existing power

stages.

Most of the existing low-power digitally controlled SMPS have very limited control

bandwidth, typically about 1/15 of the switching frequency [16,17]. With maximum

switching frequency of power stages limited to several MHz, the speed of the dynamic

response is limited as well. Therefore, the low-power digitally controlled SMPS often

suffer from long-lasting transients and/or larger voltage deviations in response to load

changes, which prevent their use in PoL applications.

The bandwidth limitation is mainly due to the natural sampling effects of the

DPWM and inherent delays introduced by the digital control loop. These cannot be

compensated using the widely-adopted digital redesign approach [18]. In the digital

redesign, an analog proportional-integral-derivative (PID) compensator is initially

constructed and, through an s-to-z domain transformation [19], converted into its

digital equivalent. At best this design approach results in bandwidth that is com-

parable or a little slower than that of standard analog solutions. Furthermore, some

of the state-of the art analog current-mode controllers have even wider bandwidth,

approaching 1/6 of the switching frequency [20].


1.5 Thesis Objectives

The main objectives of this thesis are to analyze the aforementioned problems and

develop new practical solutions for the introduction of auto-tuning digital controllers

with a fast transient response in low-power SMPS. The specific goals are listed below:

1. Development of a simple-to-implement digital voltage-mode SMPS controller

capable of extracting the power stage parameters and performing online com-

pensator re-design and/or auto-tuning.

2. Development of a proportional-integral-derivative (PID) compensator auto-tuning

procedure enabling a transient response comparable to state-of-the-art analog

solutions.

3. Development of a simple-to-implement, ultra-fast digital controller which breaks

the bandwidth limitation, by employing a nonlinear control law that relies on

the capacitor charge-balance principle.

1.6 Thesis Outline

The organization of this thesis is as follows:

Chapter 2 reviews the existing solutions for the design and implementation of

SMPS controllers. Both analog and digital systems are discussed. In addition, ex-

isting auto-tuning strategies for digitally controlled SMPS are reviewed and their

limitations discussed.

As the first major component of the thesis contributions, Chapter 3 presents

a new SMPS controller featuring power stage parameter estimation and PID com-

pensator auto-tuning. A limit-cycle oscillation (LCO) based power stage parameter


estimation (PE) method is presented and supported with theoretical analysis. A PID

compensator is accordingly designed and tuned. The PID compensator design/tuning

procedure based on modified zero positioning and automatic gain calculation is pre-

sented. The PID achieves virtually constant control bandwidth and improves system

damping. Practical implementation and operation of the system are demonstrated on

an experimental prototype. The limitations of the proposed system are also discussed.

The second major part of the thesis, Chapter 4 focuses on the development of

a new dual-mode controller that breaks the bandwidth limitation of linear PWM

controllers. In steady state, the controller operates as a conventional voltage-mode

PWM system ensuring tight regulation. During transients, fast transient response is

achieved by utilizing a new continuous-time digital signal processing (CT-DSP) unit.

It achieves optimal recovery time and minimal voltage deviation without current sens-

ing. To achieve the fast response, a charge balance based algorithm is implemented

with the CT-DSP. It calculates the optimal on/off transistor switching sequence. A

practical implementation realized with simple hardware is shown and experimental

results validating the system operation are presented.

Chapter 5 concludes the thesis and suggests future research directions.

Chapter 2

Previous Art and Motivations

This chapter briefly reviews the most common low-power SMPS controller topologies

and architectures. It also explains basic principles of auto-tuning and auto calibra-

tion and gives a survey of recent research results related to the implementation of

auto tuning systems in low-power SMPS. Limitations of the existing digital control

architectures and auto-tuning techniques are also addressed. In particular, the prob-

lems of overly high complexity and/or limited performance of the existing auto tuning

systems and poor dynamic performance of conventional digital controllers, both of

which this thesis tackles, are described.

2.1 Analog Controllers for SMPS

In commercial low-power SMPS, on-chip integrated analog controllers are predomi-

nately used. Low cost, high efficiency, design simplicity, and a relatively good dynamic

response are the main reasons for their popularity. In this section, some of the most

common analog solutions are reviewed.

8

Chapter 2. Previous Art and Motivations 9

2.1.1 PWM Voltage-Mode Controllers

Figure 2.1 shows a block diagram of an analog pulse-width modulation (PWM)

voltage-mode controller that regulates the operation of a dc-dc buck power stage.

The output voltage is regulated, i.e. maintained around the reference value Vref ,

through a pulse-width modulated control signal, c(t). The signal is generated using

the voltage feedback information only. Because of their simplicity, the voltage-mode

controllers dominate low-power low-cost systems. The controllers are used in minia-

ture battery powered devices and are also widely employed in higher power systems

that are produced in large volumes.

A more detailed implementation of a typical PWM controller is shown in Fig. 2.2.

It consists of two main blocks: a pulse-width modulator and a combined compensator

subtraction network. The modulator is comprised of a comparator and a sawtooth

wave generator. To form a pulse-width modulated signal, the output of the compen-

sator vc(t) is compared to the sawtooth vsaw(t). In this way, the gating control signal

c(t), whose duty ratio is proportional to vc(t), is generated.

It can be seen that the whole controller structure is very simple and cost effective.

It can be implemented with just two operational amplifiers, two comparators (an

additional amplifier and a comparator are needed for the sawtooth generator), and

several RC components.

The compensator of Fig. 2.2 is a typical type-III/lead-lag compensation net-

work [1, 21]. It offers both tight voltage regulation in steady state and fast dynamic

response. However, in this analog implementation it is difficult to control the transfer

function of the compensator [21], i.e. the compensator control law. The law de-

pends on the values of a large number of resistors and capacitors that have certain

tolerances, change with temperature, and are influenced by aging. Because of these


Figure 2.1: Block diagram of a voltage-mode controlled SMPS

Figure 2.2: A typical analog voltage-mode PWM controller

considerations a slower compensator ensuring system stability for all operating con-

ditions is designed [22] and the control bandwidth is usually limited. Consequently,

the LC components of the power stage are over designed, to reduce the magnitudes

of the output voltage deviations.


2.1.2 PWM Current-Mode Controllers

A typical peak current-mode controller is shown in Fig. 2.3. In this case, the output

voltage is regulated indirectly, by controlling the instantaneous inductor current. The

advantages over the voltage mode operation are that this control provides inherent

current protection and, at the same time, reduces the compensator complexity.

Similar to that in a voltage-mode controller, a voltage compensator is used for

the output regulation. However, instead of a saw tooth waveform, the compensator

output is compared with the measured inductor current IL(t). In some cases, it is

compared to the high-side switch current. Therefore, the configuration in Fig. 2.3

can be seen as a cascade control configuration, i.e., a two-loop controlled system.

The output of the voltage compensator Iref(t) is actually a current reference for

the inductor current. The current regulation is usually performed with the comparator

Figure 2.3: Block diagram of a current-mode controlled SMPS


in one switching cycle. This part of the circuitry is considered as the current loop.

Since the current loop is much faster than the outer voltage loop, it is often reduced to

a constant gain in the time-averaged system model [1]. In other words, the inductor is

forced to behave as a constant current source and the converter controlled in this way

behaves as a first order system. This system can be regulated with a proportional-

integral (PI) compensator, which is much simpler than the previously mentioned

type-III structure of the PWM voltage-mode controller. Seemingly, there is no hard

limit on the bandwidth of this configuration [1]. However, it has been shown in

[20, 23] that inherent sample-and-hold effects limit the bandwidth of the current-

mode controllers, making them no faster than the voltage-mode PWM systems. In

low-power SMPS operating at high switching frequencies, an additional drawback

is the need for a high-bandwidth high-gain current sensing and amplifying circuit,

which puts additional penalties on cost and overall system efficiency [24]. Therefore,

in lower power applications, where these are among the most crucial requirements,

current-mode controllers are less popular than the voltage-mode systems.

2.1.3 Hysteretic Controllers

The controller architectures reviewed so far can be classified as constant-frequency

controllers. The PWM control schemes guarantee a constant switching frequency

throughout the converter operation.

In some applications, variable frequency control systems are used. The hysteretic

(or bang-bang) controller [25, 26] of Fig. 2.4 is a commonly used representative of

this class. The control signal c(t) is now generated by comparing the output voltage

with a desired reference value vref(t). The comparator has a small hysteresis, ǫ, that

defines the output voltage ripple, as well as the range of the switching frequencies,


Figure 2.4: A Hysteretic voltage mode controller for SMPS

and prevents high frequency chattering.

The control scheme is very simple, the high-side switch sw1 of Fig. 2.1 is turned

on when vout drops below vref − ǫ and is turned off when vout exceeds vref + ǫ. Due

to their nonlinear nature and the absence of sampling and delay effects, hysteretic

controllers provide faster dynamic response than PWM solutions [27]. However, con-

ventional hysteretic architectures [25,26] create noise and electromagnetic interference

(EMI), both of which are highly undesirable in sensitive low-power applications. The

long switching intervals at low frequencies also significantly increase current stress on

components. In addition, the on/off switching times are determined in a generic way

and in some situations create large output voltage undershoots/overshoots. These

large voltage deviations occur due to a large amount of inductor current accumulated

during large load transients. As a result, the power stage components also go through

an extra voltage stress and over-design of the system is often required.

Other nonlinear techniques, such as sliding-mode control, neural networks and

fuzzy logic control [28–32] have also been investigated. However, they have not been

widely adopted, due to at least one of the following reasons. Like the current mode

controllers they need costly current sensing. In addition to this, they operate at non-

constant switching frequency causing noise problems, and/or have limited control


bandwidth.

2.2 Digital Controllers for Low-Power SMPS

Digital controllers for low-power SMPS have emerged in recent years due to attractive

features they offer and potential advantages over analog realizations. These include

flexibility, programmability, implementation with a small number of passive compo-

nents, design portability, and simpler implementation of advanced power management

and control techniques.

Similar to their analog counterparts, the digital systems can be implemented as

voltage-mode or current-mode controllers. However, most of the existing digital con-

trollers are of the voltage-mode type. This is because the conventional current-mode

digital architectures [33] require not only costly current sensing circuitries but also

complex analog-to-digital converters (ADCs) with a sampling rate tens of times higher

than the switching frequency. This is due to the need for instantaneous transistor

current measurement having very high frequency components. To overcome these

problems several digital or mixed-signal architectures implementing current estima-

tion or a digital-to-analog converter plus a comparator have been proposed [34–36].

These systems have not been adopted yet, either because of a high complexity or

cost issues, related to integration of analog and digital components on a single silicon

die [37]. Therefore, most of the existing commercial low-power digital solutions use

voltage-mode PWM controllers [38, 39].

2.2.1 Digital PWM Voltage-Mode Controllers

For the reasons stated in the previous section, digital voltage-mode controllers are the

main interest of this thesis. In the following section, the architecture and operation


of the voltage-mode digital PWM controller are briefly described.

Figure 2.5 shows a typical architecture of a digital PWM controller for low-power

SMPS. It consists of three major blocks: an analog-digital converter (ADC), a dig-

ital compensator and a digital pulse-width modulator (DPWM). The ADC usually

acquires the analog output voltage vout(t) and the voltage reference Vref , and then

calculates their difference, i.e. error signal, and converts it into a digital equivalent

e[n].

The digital compensator is basically a high-order linear filter that calculates the

duty ratio command d[n] from e[n] and their past values. Finally, the pulse-width

modulated control signal c(t), with duty ratio proportional to d[n], is generated with

the DPWM.

2.2.2 Digital Compensator Design Methods

A commonly used structure of a digital compensator is a linear infinite-impulse-

response (IIR) filter. In low-power applications this filter usually forms a proportional-

integral-derivative (PID) compensator having similarities with the type III (Lead-lag)

Figure 2.5: A digitally controlled voltage-mode SMPS


compensation networks. Besides the pole at (1, 0) in the z-plane, corresponding to

that at the origin in the continuous domain, it usually has two zeros. The pole is

used to eliminate steady state error and the zeros to enhance the phase response at

high frequencies.

Digital PID Structure

The conventional structures of digital PID compensators can be found in the literature

[18, 19, 40]. Their general form is shown in the following equation:

d[n] = d[n − 1] + ae[n] + be[n − 1] + ce[n − 2]) (2.1)

where d[n] is the duty ratio control signal i.e. duty ratio command, e[n] the feedback

error signal and a, b, c the coefficients for shaping the frequency response of the

compensator.

The coefficients are usually obtained using one of the two most common design

approaches, through direct or indirect design. In the indirect design, a PID compen-

sator is first constructed in the continuous-time domain and then converted into its

discrete-time equivalent, using various transformation methods [16, 19].

In [19], a PID is first constructed in the continuous-time using a modification

of the pole-zero cancellation design technique [41], similar to the one employed in

type-III compensation network designs. The obtained analog compensator is then

transformed into the discrete-time using the pole-zero mapping method [18].

This approach has certain drawbacks:

• First, the controller performance is sensitive to the converter parameter varia-

tions. Changes in the filtering inductor and capacitor values, caused by tem-

perature, aging, or other external influences can result in unmatched poles and


zeros. Consequently, the system starts behaving as an under-damped second-

order circuit experiencing oscillatory behavior.

• Secondly, at higher frequencies, the digital equivalent obtained with the pole-

zero matching shows significant discrepancy from the original continuous time

compensator. Because of this, the frequency response of controllers designed

using pole-zero matching is usually limited to frequencies 30 times lower than

the sampling rate, i.e. converter switching frequency.

In the PID compensator presented in [42], a direct design approach is applied. The

entire design is done in the z-domain. It starts with the discrete-time modeling of the

power stage that is followed by the pole-zero cancellation based compensator design.

Since the converter model is more accurate and the errors due to the transformation

are avoided, at higher frequencies it performs more precise cancellation than the

conventional methods. However, this compensator is still very sensitive to power stage

parameter variations, and experiences the same stability problems as the previously

developed systems. In other words, the design is still not robust.

To eliminate this problem, in both cases the gain of the compensator is intention-

ally reduced, resulting in dynamic response slower than that of the analog systems.

2.3 Auto-Tuning Controllers for Low-Power SMPS

The previous discussion indicates that accurate knowledge of the power stage para-

meters can significantly improve digital compensator characteristics. The problem is

that the parameters, such as the output capacitance, the filter inductor value, and

output load are changing in time, due to aging and temperature variations, and also

depend on the operating point of the power stage.


Potentially, the influence of the parameter variations can be minimized by utilizing

the flexibility of digital control and employing controllers that perform dynamic auto-

tuning. However, from the practical point of view this is a challenging task, since the

complexity of existing auto-tuning systems significantly exceeds that of the complete

low-power SMPS.

In the literature, auto-tuning controllers are widely employed in large scale sys-

tems, such as power utilities or chemical plants. They compensate for various uncer-

tainties, including temperature and load variations, aging, changes in the number of

system elements, and partial failures [10, 11].

Those controllers usually perform a two-step procedure. During the first step,

the system identification (SI) phase, the controller actively monitors system behavior

and “learns” about its properties through parameters extraction from the feedback

loop. Then, accordingly, the controller adjusts its own operation, i.e. performs auto-

tuning, to accommodate for any system changes (uncertainties) and improve the

system’s characteristics.

These auto-tuning systems rely on very powerful microprocessors or even use

high-end multi-processor systems to implement complex algorithms for parameter

estimation and auto tuning. Examples include least-squares (LS) based methods,

neural-fuzzy networks and A-function, i.e., a method for analyzing nonlinear systems

[10–13,31, 32, 43]. Therefore, existing methods are not suitable for the targeted low-

power applications.


2.3.1 Auto-Tuning Controller Based on PRBS Frequency-

Domain Identification

Recent publications [16, 44–46] show simplified auto-tuning controllers for SMPS.

In [44, 45], a system utilizing pseudo-random binary sequence (PRBS) is presented.

This system actually behaves as a modified network analyzer. After injecting a multi-

period PRBS to the control input of a power converter, the system frequency response

is obtained by performing a fast Fourier transform (FFT) of the cross-correlation of

the input PRBS signal and the converter output. The actual converter model is then

constructed with a recursive parametrization process in the frequency domain and

the compensator re-design is carried out, using a pole-zero cancelation approach.

This method has several drawbacks. Since the system emulates the operation of

a network analyzer, it can be used in open-loop only. This means that during the

SI phase, the SMPS operates without output voltage regulation. In addition, the

computational, i.e. hardware, demands for this system are high.

Therefore, the approach is neither suitable for very low power applications nor

for many others where a tight voltage regulation is required at all times.

The complexity comes from the fact that the method requires a long data collec-

tion process of 12285 switching cycles and an additional 4100 cycles for processing of

the collected data [45]. The long collection processes also influences the speed of the

auto-tuning. For instance, for a converter operating at 100 kHz switching frequency,

the identification takes 123 ms [44,45]. This might be too long for many applications

such as those in audio and video systems where fast changes of converter parameters

occur. Furthermore, the accuracy of this method is also strongly affected by the

quantization noise. As a consequence, the SI cannot give reliable information about

the high frequency behavior of the power stage unless complex high-resolution digital


controller components are used [45, 47].

2.3.2 Linear Predictor based Auto-Tuning

A significantly simpler system, based on a first-order adaptive linear prediction error

filter (PEF), is proposed in [46]. This system utilizes a self-learning concept. When

disturbances occur, the voltage loop compensator gradually adjusts its coefficients

until the optimal control law is achieved. It is assumed that a repetitive disturbance

of the same type always occurs and that in each step the controller “learns” more

about it. The main drawback to this approach is that this assumption is not always

valid. In most of the cases, disturbances are non-repetitive and unpredictable system

instability can occur. Moreover, the proposed solution uses a PD compensator that

does not provide good steady-state regulation. These limitations severely limit the

range of applications where the system can be used.

2.3.3 Relay-Feedback based Auto-Tuning

An effective relay-feedback based auto-tuning system is presented in [16]. In this so-

lution, a relay element causing oscillations at specific frequencies is introduced during

the start-up. Then, the system parameters are estimated from the frequency of oscil-

lations. The relay is placed in between the ADC and the digital compensator. In the

next phase, through several iterative steps, the auto-tuning of a PID compensator is

performed. The performance of this auto-tuner has not been verified for the regular

system operation (upon the start-up). This is mostly due to potential voltage regu-

lation problems caused by limiting analog-to-digital converter output with the relay

element during the SI phase. To create the oscillations, the ADC is replaced with a

relay and no control over the output voltage amplitude is provided.


The complete tuning process takes 27 ms for a 200 kHz converter and requires

fairly complicated computation [47]. In addition, the resulting system has a control

bandwidth of approximately 1/20 of the converter switching frequency fsw [16], which

is much lower than the bandwidth of state-of-the-art analog solutions.

Chapter 3

Limit-Cycle Oscillation based

Auto-Tuning System

In this chapter, a new hardware-efficient auto-tuning system suitable for low-power

digitally controlled SMPS is introduced. The system, shown in Fig. 3.1 utilizes

information from intentionally introduced limit-cycle oscillations (LCO) in the digital

pulse-width modulator’s (DPWM) control variable dc[n], to achieve the following

features:

• Closed loop calibration during regular converter operation with significantly

improved voltage regulation compared to the previous solutions;

• Fast compensator adjustment through a single process containing both system

identification (SI) and auto-tuning;

• Estimation of the output load and capacitance values, allowing power supply

health monitoring and dynamic mode adjustments, to improve system reliability

and efficiency over the full range of operation.

22

Chapter 3. Limit-Cycle Oscillation based Auto-Tuning System 23

Figure 3.1: An SMPS with LCO-based auto-tuning system

This system can also be used to minimize stability problems in distributed power

architectures (DPA) [48–50] and parallel converters [51]. For example, in DPA, any

change in a downstream converter can be detected and potential stability problems

can be avoided. Similarly in parallelled systems the stability problems caused by

adding new stages and the consequent change in the of power plant characteristic can

be compensated. Furthermore, in future, it could serve as a basis for the development

of universal digital controllers. They will be able to operate with various power stages

without any need for a prior compensator design. Ideally, once connected to a power

stage, the universal controller will be able to extract system parameters and adjust

its mode of operation to result in a fast dynamic response and a high efficiency under

all operating conditions.

This chapter is organized as follows. In the following section, the system oper-

ation and architecture are described. Section 3.2 gives a mathematical analysis of

limit cycle oscillations, and explains the relation between limit-cycle oscillations and


power stage parameters for buck and boost converter topologies. It also discusses the

influence of losses and non-idealities on the estimation process. In Section 3.3, it is

shown how the estimated parameters can be used for designing an auto-tuning digital

PID compensator with improved transient response compared to that of conventional

systems. Experimental results are presented in Section 3.4. System limitations are

discussed in Section 3.5.

3.1 System Architecture and Operation

The operation of the LCO-based auto-tuning controller is demonstrated on the SMPS

of Fig. 3.2. This figure shows the controller regulating a synchronous buck converter

with segmented switches. In this implementation, the auto-tuning system improves

the dynamic response and increases the overall system efficiency through current

estimation. The improved efficiency is obtained by applying segmented switches in

the power stage. Both the main switch and synchronous rectifier are replaced with

two differently sized parallel transistors. Transistors Q1 L and Q2 L are suitable for

low current. They have larger turn-on resistances but smaller gate capacitances, i.e.

lower switching losses, compared to those of Q1 H and Q2 H , designed for high current.

The process starts when a disturbance causing potential instability occurs. Such

an event is identified by the instability detector [45] and the auto-tuning begins. The

auto-tuning can also be initiated with an external check signal, and performed on a

regular basis.

The auto-tuning controller operates on a similar principle as the relay system

presented in [16,17]. However, in this case, instead of a relay, the digital-pulse width

modulator (DPWM) is used. To intentionally introduce small limit cycle oscillations

(LCO) in dc[n], the controller temporary reduces the resolution of the DPWM. Dur-


ing this short-lasting phase , the power stage corner frequency, output capacitance

and load are estimated from the amplitude and frequency of the ac component of

the signal dc ac[n] as well as from its steady state value, Dc[n] and the known digital

voltage reference Vref [n]. The Dc[n] is obtained with the steady-state capture block.

It captures the control value during the regular converter operation immediately pre-

ceding the auto-tuning process. In this way the need for a low-pass filter is eliminated

and a fast extraction of the steady state with very simple hardware is obtained.

Based on the collected information, appropriate coefficients for the PID com-

pensator are selected from a set of pre-stored look-up table values. In addition, to

improve the overall efficiency, the output load is estimated and the transistors driving

sequence selected accordingly. The selection is performed by the signal s[n] control-

ling switch enable block. The larger transistors Q1 H and Q2 H are disabled when a

light loading condition is estimated, while for heavier loads all four transistors are

enabled. Once all adjustments are completed, the controller restores high DPWM

resolution re-establishing regular system operation.

As described in more detail in Section 3.2, the use of the DPWM instead of

a relay results in much better voltage regulation during the auto-tuning process,

and consequently allows closed-loop system calibration. This is because the system

identification is based on the observation of the changes in the duty ratio control

value dc[n], which do not cause significant output voltage variations. As a result

this system not only provides better voltage regulation but also eliminates possible

stability problems existing in systems having only initial auto-tuning. We will show

that the existence of a non-negligible inductor resistance could cause a significant

change of converter resonant frequency, i.e. power stage LC frequency, and negatively

affect operation of such systems.


Figure 3.2: LCO-based auto-tuning controller regulating operation of a buck converter

3.2 Parameter Estimation from Limit-Cycle Oscil-

lations

A specific property of digitally controlled SMPS, as the one of Fig. 3.1, is that small

self oscillations of the output voltage around the reference could occur in steady


state. These oscillations are caused by non-linear quantization effects in the analog-

to-digital converter (ADC) and the digital pulse-width modulator (DPWM). The

DPWM produces a discrete set of duty ratio values, meaning that only a finite number

of steady-state voltages can be obtained. When the resolution of the DPWM is

low compared to that of the ADC, the quantized DPWM outputs cannot result in

steady-state zero error, i.e. e[n] = 0 for some operating conditions. Then, the voltage

loop compensator containing an integrator changes the duty ratio control signal dc[n]

between two or more adjacent discrete duty ratio values and oscillations known as

limit cycling (LCO) occur. The problem of LCO in digitally controlled dc-dc SMPS

and the conditions for their elimination are extensively analyzed in [40, 52].

Although undesirable in steady state, limit cycle waveforms contain useful in-

formation about the controlled system. Figure 3.3 shows a typical LCO waveform.

It is a non-symmetric signal characterized by its maximum and minimum am-

plitudes (Amax, Amin) and period, TLC . In a digitally controlled SMPS these three

distinctive features depend on the values of the power stage inductance, output ca-

pacitance and load. They also depend on Vg, the input voltage of the power stage and

the compensator parameters. Since in digital controllers the compensator coefficients

are usually known, LCO features Amax, Amin and fLC = 1/TLC can be used for the

estimation of any other three system parameters. However, the extraction of para-

meters from non-symmetric LCO usually requires complex mathematical tools, such

as the A-function [12], which gives little insight into the system’s physical behavior.

For that reason, we create symmetric LCO and analyze the amplitude and frequency

only. To compensate for the lost data, we combine these two LCO features with other

readily available information from the digital control loop; namely, the steady-state

dc value of dc[n] and the output voltage reference Vref [n].


Figure 3.3: A typical waveform of limit-cycle oscillations

3.2.1 LCO Based System Identification

This section presents the LCO based system identification(SI) process.

The flowchart of Fig. 3.5 summarizes the complete SI and auto-tuning process.

After the SI is initiated the controller checks system stability. If an instability is

detected by the detector of Fig. 3.2 the controller moves to regain stability mode. In

that mode, the output voltage is regulated with a conventional PID compensator that

would be used for a system without auto tuning. After the steady state is regained

the auto-tuning system performs parameter extraction and controller adjustments in

accordance with the procedure to be described in the following sections.

Figure 3.4 shows a model of the auto-tuning controller during the SI phase. In

a general system like this, the SI can be performed by placing a relay in the loop


and measuring the frequency and amplitude of the oscillations at the input of the

relay [12]. In [16] the authors introduced a relay after the feedback subtractor and

the variations of the output voltage error signal e[n] are utilized for compensator auto-

tuning only. The main problem of this approach is that the relay placement limits the

possibility for system identification and causes voltage regulation problems. Hence,

the authors limited the application of the method to the start-up phase only. To

obtain valuable information about the LCO amplitude at the relay input, significant

variations of e[n] need to be produced. As a result, the output voltage regulation

can be impaired. For this solution, a minimization of the output voltage oscillations

could be achieved with an ADC that has very small quantization steps. However, this

would require an expensive high-resolution ADC, which is not a preferable solution

in the targeted cost-sensitive applications.

In the system that we present here, no additional relay is needed. To improve

voltage regulation and allow dynamic adjustments during converter regular operation,

the DPWM is used as a natural quantizer. As shown in Fig. 3.4, during the auto-

tuning phase, the resolution of the DPWM is reduced while it is still fed with a high

resolution control variable, so that multiple values of dc[n] correspond to a single

implemented duty ratio value d. In addition, the PID compensator used for regular

converter operation is replaced with an integral compensator, K zz−1

. This integrator

has a dual role. It amplifies the small LCO of the output voltage resulting in much

larger variations of the control variable dc[n], which can be easily measured without

significantly affecting voltage regulation. The other role of the compensator is the

simplification of the system identification procedure.

When LCO is steadily excited the total loop has a gain of 1 and a phase shift of

180 degrees, as in the case of an analog oscillator. The amplitude and frequency of

produced oscillations, ALC and fLC = ωLC/2π = 1/TLC , respectively can be found


Figure 3.4: A model of the LCO-based auto-tuning system during system identifica-tion

from the following condition for their existence [53–55]:

−1 = 1∠180 = NDPWM(ALC , ε)Gvd(jωLC)KADC(jωLC)K ′

jωLC

(3.1)

Where, NDPWM(ALC , ε) describes the gain of the DPWM, Gvd(jωLC) is the control-

to-output transfer function of the switching converter, and KADC(jωLC), is the input-

to-output transfer function of the analog-to-digital converter. The integrator is repre-

sented in its equivalent analog form K ′

s. In this case, to obtain the gain of the DPWM

we use describing functions [54,55]. Also, to simplify the analysis we assume that the


frequency of the LCO is much smaller than the switching frequency and that, at fLC ,

the delays of the ADC and DPWM have negligible effects on the results.

In [53] it was shown that the nonlinear gain of DPWM depends not only on

the input signal amplitude, but also on the signal’s offset. In the context of this

study, the gain depends on the offset to the midpoint of the output quantization bin

where duty ratio equals d in Fig. 3.4. Hence, the direct parameter extraction cannot

be performed unless the offset is taken into account or its influence eliminated. To

eliminate the offset, we introduce a zero-offset calibration block, shown in Fig. 3.4.

Before the resolution of the DPWM is reduced, the block calculates the offset of dc[n]

and accordingly changes the digital voltage reference Vref [n] to result in zero dc bias.

For example, if the resolution of the DPWM is to be reduced from 10 to 7 bits and

if the three least significant bits (3 LSBs) of the 10-bit dc[n] value are 001, the offset

calibration block changes the reference to have the 3 LSBs of dc[n] equal 100. It

is performed by adding 011 to Vref [n] (see Fig. 3.2). This value is the mid-point

between two successive 7-bit values and has zero offset. As a result symmetric LCO

are created and analyzed using describing functions (DF) with zero dc bias [54]. That

analysis shows that the gain of the DPWM is:

NDPWM(A) =4Dq

πALC

(3.2)

where, Dq is the quantization step of the DPWM when operating with a crude res-

olution (see Fig. 3.4). It should be noted that the offset calibration block always

insures the existence of limit-cycle oscillations during auto-tuning. For some operat-

ing points, even a very low-resolution DPWM can result in operation without LCO.

It happens when one of the coarse quantization steps causes the output voltage to fit

inside the zero-error bin. By introducing zero offset this situation is eliminated and


Figure 3.5: Flowchart of the limit-cycle initiation and system identification process

the average value of d[n] always lies between two discrete values. It is also worthy to

mention that this change of reference does not have a significant effect on the output

voltage regulation. For the example discussed above, a temporary output voltage

change of less than 2% can be expected.

3.2.2 Measurements of LCO Features

Here we give a more detailed description of the blocks for the LCO amplitude and

frequency measurements.


A. Peak-to-Peak Amplitude Measurements

To improve the accuracy by minimizing quantization effects, the peak-to-peak am-

plitude of the LCO, APP is measured. The peak evaluation is performed through a

simple detection of sign change in the difference of the control signal dc[n]:

∆dc[n] = dc[n] − dc[n − 1] (3.3)

This signal is sampled at the switching rate, which is much higher than the LCO

frequency. The value dc[n − 1] immediately preceding the sign change from positive

to negative is considered to be the maximum amplitude of the the LCO, that is

Amax, while the dc[n−1] preceding the opposite sign change is equal to the minimum

amplitude of the LCO, Amin. Peak-to-peak amplitude APP in one LCO period is

calculated by taking the difference between the Amax and Amin values.

B. LCO Frequency/Period Estimator

Fig. 3.6 shows a block diagram of the frequency extractor, which is a part of the LCO

measurement block depicted in Fig. 3.2. The measurements is based on the detection

of two zero crossings of the control signal ac value dc ac[n]. A change of dc ac[n] to

a positive value is detected and used to start the counter, and the following change

of dc ac[n] to a negative number stops it. The counter is clocked at the switching

frequency, which usually is 30 times higher than the corner frequency of the output

filter, i.e. the frequency of LCO. This allows accurate evaluation of a value which is

proportional to the LCO period to obtain an accuracy of 3% accuracy.


3.2.3 Relations between LCO Features and Power Stage Pa-

rameters

The exact relations between LCO features and power stage parameters can be found

using advanced control theory tools developed for large-scale relay feedback systems

[12,13]. Still, as mentioned before, these methods give little insight into the relations

between LCO features and system parameters.

As shown next, a simpler and more intuitive analysis gives fairly accurate results.

It combines describing functions with the available information about the steady state

duty ratio and output voltage reference values. In this way, power stage parameters

such as corner frequency, damping factor are accurately identified using LCO feature

information. Indirectly, under the assumption that the inductance does not change

significantly over time and is known, the output capacitance and load values can also

be obtained. In the following sections, equations for converter parameter estima-

tion are derived for both buck and boost converters. The influences of the inductor

equivalent series resistor on the identification are also investigated for the buck case.

Figure 3.6: Frequency extractor block diagram


A. Theoretical LCO Analysis for A Buck Converter Example

This analysis starts from an averaged small signal model of a buck converter described

with its second order control-to-output transfer function [1],

Gvd(s) =v(s)

d(s)= Gd0

1

1 + sQω0

+ s2

ω2

0

(3.4)

where

ω0 =1√LC

Q = R

√

C

L

Gd0 = Vg =V

D

The output capacitance, inductance and load resistance are denoted by C, L, and

R respectively. In this case, it is assumed that the output voltage V is known, and

that the steady state value of the duty ratio D is extracted from the dc value of the

control variable, as shown in Fig. 3.2.

When a buck converter is connected as shown in Fig. 3.4, limit cycle oscillations

occur. Ideally, the frequency of the LCO corresponds to the output filter corner

frequency ω0 at which the phase shift of the loop gain is 180. In practice, this

frequency is a little bit lower, due to additional phase shifts introduced by the delays

of the ADC and DPWM [16].

In the estimation of the R and Q-factor we assume that the value of the inductance

L is known with a certain degree of accuracy, and is relatively stable, compared to the

values of the output load resistance and capacitance. To further simplify the analysis

without loosing generality, we assume unity gain of the analog-to-digital converter


and PI compensator. This is because the gain does not affect the values of the LCO

features.

The solution of (3.1)(3.2) and (3.4), gives the following result for the peak-to-peak

amplitude of the LCO:

App =4

πDqGd0

R

ω0L(3.5)

By combining (3.4) and (3.5) and we obtain expressions for the output resistance

and Q-factor:

R =Appω0πL

4DqGd0

(3.6)

Q = Rω0

L=

Appπ

4DqGd0

(3.7)

These equations show that by knowing the steady state duty ratio value and analyzing

LCO all parameters needed for a compensator design and load estimation can be

obtained during a single SI and auto-tuning phase.

It should be noted that at very light loads a high value of Q factor could result in

excessive limit cycle oscillations affecting voltage regulation. However, in the targeted

application this is of no concern. In such conditions most of the modern low-power

SMPS are likely to be regulated using pulse-frequency modulation (PFM) [2, 56]. In

those systems the light load operation (for example, stand-by mode of an electronic

load) is usually indicated with an external signal produced by the load or can be sensed

using the current estimator presented in [6]. Alternatively, the excessive oscillations

in dc[n] can be detected with a simple limiter and consequently the resolution of the

DPWM increased, i.e. Dq reduced, to minimize the amplitude of the LCO (3.5).


B. Boost Converter Example

The proposed parameter estimation approach can be applied to other converter

topologies as well, including boost, whose control-to-output transfer function is:

Gvd(s) = Gd0

1 − sωz

1 + sQω0

+ s2

ω2

0

(3.8)

where

ω0 =D′

√LC

Q = D′R

√

C

L

ωz = ω0Q

According to (3.1), in this case, the LCO frequency will not be the same as the

converter corner frequency but at the point where the boost converter introduces

−90 phase shift. Thus, the relation describing the LCO condition becomes:

Gvd (jω) =πApp

4Dq

∠ − 90 = Gd0

1 − j ωLC

ωz(

1 −(

ωLC

ω0

)2)

+ jωLC

Qω0

(3.9)

By solving (3.9), again assuming that D, V, and L are known, and D′ = 1 − D,

we can obtain the main parameters of the transfer function (3.8). Besides solving for

ω0, Q, and ωz, from (3.9) we can also extract R and C. These relations are given as

follows:

R =ωLCLB

D′2(3.10)

C =D′2 (B2 − 1)

Lω2LCB2

(3.11)


where, ωLC is the radial frequency of LCO, and B = Appπ

4DqGd0

a new constant introduced

for simplicity.

C. Influence of Inductor Series Resistance

In the proposed auto-tuning method, a nonnegligible inductor resistance RL can cause

significant quantitative changes in the frequency and amplitude of the LCO. The

following analysis, including a more accurate buck converter model, shows this effect.

Now, the coefficients of (3.4) change and the converter resonant frequency and Q-

factor become:

ω20 =

RL + R

RCL(3.12)

Q =

√

(RL + R)RCL

CRRL + L(3.13)

For this case, the relations between the amplitude and frequency of the LCO and

power stage parameters in (3.1) are given by the following equations and illustrated

in Fig. 3.7,

ω2LC =

RL + R

RCL(3.14)

App =4

πDqGd0

R

CRRL + L

1

ωLC

(3.15)

C =RL + LBωLC

BωLC(R2L + ω2

LCL2)(3.16)

R =L + RL

Lω2

LC

Vg

BωLC− RL

Lω2

LC

(3.17)

These results show that in a realistic converter both amplitude and frequency of

the LCO depend not only on the output capacitance but also on the load value. It

can be seen in (3.14) that at heavy loads the resonant frequency of the converter, i.e.


LCO frequency ωLC , can be significantly higher than the LC frequency of an ideal

converter, causing stability problems if the compensator adjustment is not performed

regularly.

To assess the accuracy of the previously described analysis we use the system of

Fig. 3.2 and compare its results (3.14)-(3.17) with experimental measurements for

various values of R and C. As it can be seen from Figs. 3.7 and 3.8, the describing

functions give a fairly accurate estimation of the system parameters.


Figure 3.7: Relations between LCO features, including frequency (top) and amplitude(bottom), and the power stage physical parameters, including load resistance R andcapacitance C. Power stage parameters are L = 33 µH , RL = 0.1 Ω, Vg = 8 V , andVout = 3.3 V : (a) calculated frequency of LCO; (b) measured frequency of LCO; (c)calculated amplitude of LCO; (d) measured amplitude of LCO.


Figure 3.8: Comparison of the experimentally obtained data for LCO features withanalytical results: (a) dependence of LCO peak-peak amplitude on the output loadresistance when output capacitance C = 38 µF ; (b) dependence of LCO frequencyon the output capacitance value when output load resistance R = 5 Ω.


3.3 Programmable PID Compensator and Load Es-

timator

The previous analysis shows that most of the power stage parameters can be extracted

by analyzing limit cycle oscillations and utilizing readily available information from

dc[n]. Consequently, we use the extracted data for a digital compensator design,

following the procedure presented in this section. The procedure gives the relations

between the parameters of a buck converter and PID compensator coefficients. The

practical implementation of the programmable PID and load estimator are also shown.

3.3.1 Compensator Design and Tuning

The determination of PID compensator coefficients is performed in two steps. First,

a modified pole-zero cancellation technique [41] is used to find compensator zeroes.

Then, a gain calculation technique using geometric relations in the frequency domain

is applied to achieve a predefined control bandwidth.

As described later, the modified pole-zero cancellation is used to avoid the oscil-

latory transient response due to mismatch of the PID zeros and power stage poles.

The influences of PID designs on closed-loop system damping are illustrated with the

root locus analysis [41].

A. PID design based on pole-zero cancellation

A PID design example for a buck converter based on conventional pole-zero cancel-

lation is shown below. The design starts from determination of the plant poles from


the converter transfer function,

Gvd(s) =v(s)

d(s)= Gd0

1

1 + sQω0

+ s2

ω2

0

(3.18)

where ω0, Q and Gd0 are power stage corner frequency, Q factor and dc gain respec-

tively.

In the conventional pole-zero cancellation design, the goal is to design a PID

compensator, C(s), such that the PID zeroes are at the exact locations of the power

stage complex conjugate double-pole, so that the total loop gain T (s) = C(s)Gvd(s)

is reduced to an integrator. The compensator and loop gain transfer functions for

that case are shown below:

C(s) = Kc

1 + sQω0

+ s2

ω2

0

s(3.19)

T (s) = C(s)Gvd(s) =KcGd0

s(3.20)

It can be seen, that in this idealized case the design of the integrator to meet

stability and bandwidth requirements becomes simple. As shown in (3.18) - (3.20)

the parameters used in the design are power stage corner frequency ω0, Q factor and

dc gain Gd0, all of which can be extracted from the LCO based identifications process

as described by equations (3.4)-(3.7). The ω0 is the same as the LCO frequency, Q is

proportional to the LCO amplitude and the converter dc gain can be found from the

steady state duty ratio value.


B. A Modified PID Zero Placement Strategy for Improving System Damp-

ing

The main problem of the conventional pole-zero cancellation compensator design is

oscillatory transients or even instability occurring when the poles and zeroes are not

perfectly matched. Since in practical applications the load is changing frequently and

the proposed estimation method has high but still limited accuracy the mismatching

is a serious concern.

As a solution, a modified version of the PID design method is proposed here.

Instead of placing the PID zeroes at the exact locations of power stage poles, they

are set in regions that provide better system damping. The new compensator design

results in more robust system operation, improving system damping for a large range

of load conditions. An additional advantage is that it also requires less accurate

information about the power stage damping factor than the conventional approach

so that the implementation can be further simplified.

B.1 Oscillatory Transient Response due to Pole-zero Mismatch

To demonstrate the problem of mismatching the root locus analysis of an arbitrary

buck converter of (3.18) regulated by a PID compensator is performed as follows. In

this case the PID compensator C1(s),

C1(s) = Kc

1 + sQzωz

+ s2

ω2z

s(3.21)


has the same form as (3.19) but its damping factor Qz is not necessarily equal to the

Q factor of the power stage. Then the loop gain T (s) becomes:

T (s) = C(s)Gvd(s) = KcGd0

1 + sQzωz

+ s2

ω2z

s(1 + sQω0

+ s2

ω2

0

)(3.22)

Figures 3.9. shows the root locus of the total loop transfer function for two cases.

The first case (Fig. 3.9.a) shows the root locus when the pair of complex conjugate

poles of the converter is perfectly matched with the zeros, i.e. Q = Qz. The second

case, shown in Fig. 3.9.b, is the situation when a mismatch exists.

It can be seen that for the second case, as the open-loop gain increases from zero

to infinity, the closed-loop poles travel from the open-loop ones to the open-loop zeros,

i.e. from points A and B to the points C and D [41]. As a result, the roots follow low

damping factor paths s1 and s2, meaning that the system is likely to oscillate.

B.2 Modified PID design for improving system damping

To compensate for the oscillatory response, we place the PID zeros, i.e. open-loop

zeros of T (s), in the geometrical regions that provide better damping. As in the

previous example, the resonant frequency of the PID zeros i.e. ωz in (4.11) is still

designed to be at the power stage corner frequency ω0 to avoid conditional instability.

However, the damping ratio ξz = 12Qz

, now becomes a design parameter. Its value is

set to be between 0.6 − 1, which, as shown in [41], results in a good damping. The

pre-set value of the damping factor eliminates the need for the measurement of the

actual damping factor simplifying the compensator design procedure.

Figure 3.10 shows the root locus for the system T (s) = C(s)Gvd(s) when ξz = 0.7.

The paths s1, s2 now move through more favorable regions as the loop gain increases.

Note that the scales of coordinates here is different from those in Fig. 3.9.


Figure 3.9: Root locus of the total loop T (s) = C(s)Gvd(s): (a) ideal pole-zerocancellation case; (b) unmatched pole-zero cancellation case.


Figure 3.10: Root locus of the total loop T (s) = C(s)Gvd(s) with a PID compensatordesigned to provide better damping to the system

It can be seen in Fig. 3.10 that a damping factor of 0.802 is obtained in the closed

loop when the desired loop bandwidth is reached i.e. feedback gain=1.

To verify the robustness of the proposed PID design technique, the compensator

design for the previous case is tested while the resistive load value is varied, i.e. Q

factor of the converter is changed from a value much smaller than 1 to ∞. The root

locus for this case is shown in Fig 3.11. It can be seen that over the full range of

variations a strong damping factor is obtained.

In order to implement the compensator with digital hardware, the continuous time

equation is transformed into a discrete-time equivalent using the zero-pole matching

approximation [18]. This results in the following PID compensator discrete-time


Figure 3.11: Modified root locus with respect to varying power stage damping factor.

control law:

dc[n] = dc[n − 1] + Kd

(

e[n] − 2r cos

(

2πfz

fs

)

e[n − 1] + r2e [n − 2]

)

(3.23)

r = e(−πfzQfs

) (3.24)

where fs is the system sampling frequency and fz the center frequency of a pair of

compensator zeros, which are selected to be equal to or slightly lower than the LCO

frequency to ensure positive phase margin.


The gain Kd is a design parameter transformed from the continuous gain Kc:

Kd =Kc

fs(1 + cos(2πfz

fs) + r2)

. (3.25)

As it will be shown in the next subsection, Kc is selected to meet pre-defined dynamic

response, i.e. bandwidth, requirements [21].

C. PID gain selection for a predefined control bandwidth

In this subsection, we show the digital compensator design with a virtually constant

bandwidth of 1/10 of the converter switching frequency, which is comparable to state

of the art analog solutions and is much faster than conventional digital controllers.

The selection of the compensator zeros and the damping factor described in the

previous subsection results in the loop gain characteristics whose ideal form is shown

in Fig. 3.12. The bode plots show that the system behaves as an ideal integrator,

whose crossover frequency can be controlled with the gain of C(s) only.

Based on the geometric relationship of the triangle ABC shown in Fig. 3.12, the

gain of compensator C(s) can be derived for a given bandwidth from the following

equations:

|T (jω)| |ω0= Slope(|T (jω)|) · −−→BC =

−→AB

⇒ Slope(|T (jω)|) · −−→BC = 20 log10(|Gvd(jω)| |ω0· |C(jω)| |ω0

)

⇒ Slope(|T (jω)|) · log10(ωBW

ω0

) = 20 log10(|Gvd(jω)| |0 · |Kc

jω| |ω0

)

⇒ 20 log10(ωBW

ω0

) = 20 log10(|Gvd(jω)| |0 · |Kc

jω| |ω0

) − 0

⇒ ωBW

ω0

= |Gvd(jω)| |0 · |Kc

jω| |ω0

⇒ ωBW

ω0

= Gd0Kc

ω0

⇒ Kc = ωBW

Gd0

(3.26)


Figure 3.12: Approximated gain plots of the characteristic of Gvd(s), C(s) and T (s).

Therefore, to obtain a specific control bandwidth ωBW , the compensator gain is

calculated as:

Kc =ωBW

Gd0(3.27)

Where Gd0 is estimated from the steady state duty ratio D and reference/output

voltage Vout as Gd0 = Vg = Vout

D. It is worth mentioning that inherently existing

information about the values of D and the voltage reference Vref in a digital control

loop simplifies estimation of the input voltage. The estimated value then can be used

for the implementation of a feed-forward strategy that eliminates the influence of

input voltage variations [57].


3.3.2 Programmable PID Implementation via Look-Up Ta-

bles

To create an auto tuner we could build dedicated digital hardware that performs

sophisticated calculations for the PID compensator parameters. However, as it will

be shown in (3.23),(3.24), from the practical realization point of view, such a solution

involving heavy computation would be quite complex. Instead, as shown in Fig. 3.13,

we use a set of look-up tables (LUTs) for the transformation of LCO features into

PID coefficients. The tables containing pre-stored values of controller coefficients are

addressed by the measured LCO features (APP , fLC) as well as by the steady state

value Dc[n].

This architecture involves a tradeoff between the size of the LUT and the number

of possible discrete control laws. However, for most of the applications, the construc-

tion of a large LUT covering all possible inputs is not necessary. We have found,

through extensive simulations and experimental verifications, that the knowledge of

(APP , fLC) and Dc for a relatively small number of operating points gives sufficient

information for the design of a compensator covering a wide operating range. In

practice, it is found that with the use of thirty discrete-time control laws, fairly good

dynamic characteristics can be obtained. A compensator which can be used to prove

the presented concepts is incorporated into our prototype. The address generator

selects an appropriate control law, based on (APP , fLC) and Dc values and their pre-

calculated relations with the compensator coefficients. Since, in most of the cases,

exact matching between the LCO parameters and addresses stored in look up tables

cannot be found, the generator selects the control law that corresponds to the closest

smaller value of the measured LCO frequency. In practice, it means that the fre-

quency of the PID’s complex zeroes, as described in [19], is always a little less than


the corner frequency of the power stage ensuring system stability. The rounding down

is performed in very simple manner, by observing only the 4 most significant bits of

fLC [n]. This results in fifteen possible values of PID zeroes (0 frequency is excluded).

Two possible compensators, with different damping factors, are assigned to each of

these frequencies. The selection of the damping factor is performed from D and APP .

The damping factor can also be made a design parameter to improve system damping

especially for under-damped power stages as shown in Section 3.3.1. As a result, the

system complexity and LUT sizes can be further reduced.

This structure having thirty possible control laws obviously cannot cover all pos-

sible converter configurations and all possible output filter values. To make a truly

universal controller, a massive memory, having a very large number of control laws

could be potentially used. Taking into account recent advances in the reduction of

size, power consumption, and cost of large capacity storage elements, this becomes

a conceivable solution. Alternatively, a two-step self-tuning system presented in Ap-

pendix. B, which calculates online parameters in (3.23) can be implemented.

3.3.3 Load Estimator

Figure 3.3 also shows a load estimator and switch selector block used for efficiency op-

timization and current protection. It combines the current extraction method based

on (3.6), with the switch selection logic introduced in [8]. Based on fLC and the

product DcAPP , an appropriate 2-bit switching sequence s[n] is selected with a com-

pensator having two programmable thresholds. The thresholds of the comparator

depend on the amplitude of the LCO and pre-stored current limit values. As shown

in Section 3.2.3, the largest DcAPP product corresponds to the lowest current and

only the small transistors Q1 L and Q2 L are enabled (see Fig 3.2). Larger output cur-


Figure 3.13: Block diagram of programmable PID compensator and load estimator

rents result in lower comparator inputs and the activation of parallel switches. When

the product drops below the lowest threshold corresponding to a current greater than

the rated maximum current, current protection is activated and all of the transistors

are turned off.

To eliminate possible current stress, the solution presented in [8] is applied. Dur-


ing each light to heavy load transition, all four transistors are enabled. Only after

the current estimation is completed, an appropriate driving sequence s[n] is set.

3.4 Experimental Results

Based on diagrams shown in Figs. 3.1, 3.2 and 3.3 an experimental prototype was

built. The power stage of the system is a 400 kHz synchronous buck with segmented

switches. The smaller transistors (Q1 L and Q2 L from Fig 3.2) are IRF-IRML2402,

rated for 1.2 A; the larger ones are IRF-IRMLS1902 with 3.2 A current rating. The

input voltage Vg is 5-9 V and the output is regulated at Vout = 3.3 V.

All functional blocks of the auto-tuning controller including the implementation

of a high-frequency programmable-resolution DPWM are realized on a Altera-DE2

FPGA board using the Verilog hardware description language (DHL). The only ex-

ternal component needed is an off-shelf ADC, AD9281. In steady state the DPWM’s

resolution is 10 bits, while during the identification process it is decreased to 7 bits.

The quantization step of the ADC around reference is set to be 20 mV. Pre-calculated

PID coefficients are placed in three 30-word 10-bit look-up tables. It should be noted

that the synthesizable Verilog HDL design on a FPGA and a custom designed ADC

can be easily migrated to a single application specific IC. The on-chip implementation

of the proposed auto-tuning system without using memory elements is estimated to

have about 5000 logic gates. This number is much smaller than those required by

other auto-tuning systems shown in Table 3.1.

Figures 3.14 to 3.18 show results obtained with the experimental prototype.


Table 3.1: Implementation Comparison of Auto-Tuning SMPS ControllersPRBS Relay Feedback PEF LCO

[45] [47] [16] [47] [46]Implementation Platform FPGA FPGA DSP FPGA

Parameter Estimation Yes No No YesTuning Time (cycles) 16385 5400 N/A 500

Gate Counts 26k ≥26k N/A 5kMemory Counts 10k RAM,3k ROM No N/A No

Transient Performance good good poor good

3.4.1 Auto-Tuning Examples

Figure 3.14 demonstrates a disturbance caused by a sudden change of the output

capacitance and a consequent auto-tuning process. After the disturbance is detected

by the Instability Detector of Fig. 3.2 the auto-tuning is performed in accordance

with the algorithm shown in Fig. 3.5. During the phase where stability is regained a

conservative PID compensator frequently changes the dc[n] control value to establish

a steady state. To provide stable system operation for all operating conditions, this

PID compensator is constructed in accordance with the worst-case design procedure

described in [19] and would be used in a conventional controller without auto-tuning.

As depicted in Figs. 3.7 and 3.8, variations of C and R from 10 µF to 55 µF and

from 1 Ω to 10 Ω, respectively are considered. The worst case conditions are assumed

to be R=10 Ω and C=55 µF.

In the following phase, LCO are introduced and a slower integral compensator reg-

ulates the output voltage. Since the bandwidth of the integrator is low, it eliminates

high-frequency variations of dc[n] allowing accurate measurement of the LCO. During

the last phase, the PID compensator coefficients are updated and a new auto-tuned

compensator is utilized.

A zoomed-in view of the previous waveforms during the LCO phase is shown

in Fig. 3.15. These waveforms verify that the new auto-tuning system has a small


Figure 3.14: Auto-tuning process after a sudden output capacitance change Vg = 8V, C = 38 µF, L = 33 µH, fsw = 400 kHz. The limit cycle oscillations of four leastsignificant bits of dc[n] (digital channels D0-D3) are used for parameter estimation.

Figure 3.15: Zoomed-in view of the output voltage waveform and the four leastsignificant bits of the control signal dc[n] during LCO phase.


influence on the output voltage regulation. It can be seen that even though the

converter operates with a relatively light load (5 Ω) and high input voltage, only

small output voltage variations of less than 40 mV at the output exist. Still, these

variations cause significant changes in the four least significant bits of dc[n] that can

be easily detected and used for parameter extraction. For even lighter loads, the

resolution of the DPWM can be increased to 8 bits. As a result, similar values of

LCO amplitude can be obtained for twice of the output resistance value as shown in

(3.6).

The waveforms of Figs. 3.16 and 3.17 show a comparison of load transient re-

sponses of the auto tuned compensator and the one used during the regain stability

phase.

It can be seen that auto-tuning improves the dynamic characteristics of the con-

troller resulting in a significantly faster response with much smaller output voltage

drops and overshoots.

Figure 3.18 shows the operation of the load estimator and the process of efficiency

optimization through a selection of switching sequence. As described in Section 3.3.3,

at light loads only transistors Q1 L and Q2 L are active while at heavier loads all four

transistors are enabled. It can be seen that during the transients, all four transistors

operate simultaneously. Changes of switching sequence are performed after the load

estimation phases (labeled as LCO1 and LCO2) are completed. This diagram also

shows the effect of the offset calibration circuit, described in Section 3.2.1. It slightly

changes the reference to generate symmetric LCO. The efficiency of this system is

compared to the one having larger transistors (Q1 H and Q2 H) only. An improve-

ment at light and medium loads of up to 7% was achieved. If a more sophisticated

segmented power stage is used, similar to the one demonstrated in [8], even better

improvement can be expected.


Figure 3.16: Experimental load transient response of conventional controller for theoutput load changes between 1.3A and 3A; Vg = 8 V, C = 38 µF, L = 33 µH,fsw = 400 kHz.

Figure 3.17: Experimental load transient response of the auto-tuned controller forthe output load changes between 1.3 A and 3 A; Vg = 8 V, C = 38 µF, L = 33 µH,fsw = 400 kHz.


Figure 3.18: Experimental load transient response showing operation of the loadestimator and the process of efficiency optimization through a selection of switchingsequence.

3.4.2 Improved Transient Response with Proposed PID De-

sign Method

The final set of experimental results demonstrates an improvement in the transient

response obtained with the PID compensator design method described in 3.3.1. The

modified pole-zero cancellation method is compared with the traditional one. From

Fig. 3.19, it can be seen that the oscillatory behavior of the conventional controller

is eliminated and a much shorter settling time is obtained.


Figure 3.19: Load transient responses obtained with two PID designs: (a) conven-tional PID response with pole-zero cancellation; (b) proposed new PID with improvedsystem damping. Load changes from 4A to 0 A; Vg = 12 V, Vref = 1.8 V, C = 200 µF,L = 1.5 µH, fsw = 500 kHz.


3.5 System Limitations

The losses of the switches and the resistances of the output filter components as well

as non-overlapping conduction times alter the transfer function of a converter, and

consequently change the amplitude and frequency of the LCO. As a result, in some

situations, the performance of the auto-tuning system can be affected. The operation

of the system is also influenced in situations when the output load is not a pure

resistor but a current sink or combinations of both. In this section we address these

problems, focus on the most dominant ones, and suggest solutions for them. The

problems are divided into two groups. The first group of problems have a negative

effect on load estimation and the second group influence the compensator design.

It should be noted that, in most of the cases these problems are not related since

the compensator design predominantly relies on the knowledge of actual resonant

frequency, which usually coincides with the frequency of the LCO.

3.5.1 Load Estimation

The presented load estimation method relying on the derivation of the output load

from the Q-factor has limited accuracy and is more suitable for coarse current esti-

mation and segmented switching than for the applications where an accurate knowl-

edge about the output current is required. The examples where coarse knowledge

of the current estimation is sufficient, include consumer electronics and communica-

tion devices. In those applications several clearly distinguishable task-dependent load

conditions can be easily recognized.

The accuracy of current estimation is affected by several factors, which we have

grouped into three categories.

First, is that the inductance value, which is used for calculation of the load, has


a tolerance that limits the accuracy of current measurement.

The second factor is related to the variation of the damping factor Q. It is

largely influenced by parasitic components and nonlinearities in the circuit. Namely,

as described earlier, the series resistances of the inductor and the capacitor’s Resr,

can change Q or cause the LCO to occur at a slightly different frequency. In addition,

in converters with synchronous rectification, non-overlapping dead-time [58] can also

alter the value of the damping factor. In digital controllers the value of the dead-time

is often known and can be accurately controlled [9, 58]. Hence, it can be taken into

account, to modify the converter model, and a consequent on-line compensation can

be performed.

From a system operation point of view, the most critical situation is when the

output load is a digital signal processor or a downstream converter, which dynamically

do not behave as a resistor but as a current sink or a power sink, respectively. In these

cases, the amplitude of the LCO is not proportional to the load resistance any more,

but is still limited due to the fact that the filter inductor and switching transistors

introduce losses.

The losses can be modeled as resistors [1] and lumped in a single equivalent value

Rtotal. Now, the amplitude can be derived from (3.15), by replacing RL with Rtotal

and letting R → ∞:

App =4

πDqGd0

1

CRtotal

√LC =

4

πDqGd0

1

Rtotal

√

L

C(3.28)

If the amplitude is too high, as suggested in Section 3.2.3, a protective limiter

can be introduced.

It should be noted that, even though the load estimation cannot be directly per-

formed, the LCO still occurs at the resonant frequency allowing proper compensator


operation and fast dynamic response. This is demonstrated with the simulation re-

sults of Fig. 3.20, showing the system identification phase and transient response of

the converter when the load is a current sink.

Figure 3.20: Time-domain simulations of the system of Fig. 3.1 for the case whenthe load is a current sink whose value changes from 0 A to 1 A.

To perform load estimation in these cases, other method can be used. For ex-

ample, as described in [6, 8] a simple low-bandwidth ADC at the input of the power

stage can be placed and the load can be estimated by monitoring the deviation of the

steady-state value of dc[n]. Note that this deviation strongly depends on the total

loop resistance Rtotal, which can be estimated from LCO amplitude in (3.28) if not

known.


3.5.2 Compensator Design Considerations

A non-negligible equivalent series resistance Resr of the output capacitor C introduces

a zero in the converter transfer function at the frequency fesr = 1/(2ResrC). Here

we show that this zero can affect the system in two ways causing noise problems or

reducing the bandwidth of the loop and causing erroneous load estimation.

The first situation is depicted with the discrete-time Bode plots of Fig. 3.21

showing frequency characteristics of the discrete-time compensator (3.23), labeled as

Gc(z), the control-to-output transfer functions of a digitized buck converter model

for three different values of fesr, and corresponding loop gains T (z).

The cases when the frequency of the ESR zero is a little bit higher then the desired

crossover frequency of the system fc, i.e. fesr ≈ 1.5fc and fesr ≈ 5fc as well as when

it is below fc, i.e. fesr ≈ 0.8fc, but still significantly higher than the converter’s

corner frequency f0 = 12π

√LC

are demonstrated.

In practice, this situation can happen when a tantalum or an aluminum capacitor

with a high Resr is used. Then, the PID (3.23), designed to have a pair of complex

zeroes at a frequency slightly lower than f0 [19] has a low attenuation of high frequency

components, and in some cases, seemingly, results in a non-zero-crossing as shown

for the case of fesr ≈ 0.8fc in Fig. 3.21. In practice the non-zero-crossing is not

likely to exist because an anti-aliasing filter at the ADC’s input or the natural low-

pass filtering effect of a delay-line or ring oscillator based ADC [5,59] acts as a high

frequency pole forcing the loop gain to drop. As shown in Fig. 3.22, showing time-

domain simulations of the system of Fig. 3.1, in those situations, the system stability

and dynamic response are not compromised, although noise related problems can

occur. The low attenuation of the high frequency components causes a poor noise

rejection which can be seen at the converter output. To minimize the noise problem,


Figure 3.21: Magnitude and phase characteristics of the uncompensated and compen-sated buck converter for the cases when the frequency of a zero introduced by Resr isaround the desired crossover frequency of the system.

if needed, a pole at a constant frequency, higher than the desired system bandwidth,

can be introduced.

In modern converters having low-Resr capacitors, a more serious but not common

situation is that fesr can be close to f0. As shown in Fig. 3.23 this zero increases the

frequency point where the phase shift of the open loop system is 90 and, according

to (3.1), forces the LCO frequencies and the placement of the compensator’s complex

zeroes beyond f0. From the Bode plots it can be seen that this mismatch results in

a lower crossover frequency, i.e. slower dynamic response, than expected and an in-

correct estimation of the output resistance, but does not cause system instability. To


avoid these problems, an additional delay component, causing a phase shift propor-

tional to the negative value of that introduced by fesr zero can be applied during the

system identification phase. The delay will cause the LCO to occur at the resonant

frequency and thus a more accurate estimation of the damping factor is achieved.


Figure 3.22: Time-domain simulations of the closed-loop operation of the system ofFig. 3.2 when Resr is not negligible; Top: the output voltage vout(t) during a light toheavy load transient (0.65 A to 1.3 A); Bottom: vout(t) during a heavy to light loadtransient (1.3 A to 0.65 A).


Figure 3.23: Magnitude and phase characteristics of the uncompensated and com-pensated buck converter for the cases when the frequency of a zero introduced byequivalent series resistance is close to the corner frequency of the power stage.

3.6 General Limitations of PWM Voltage-Mode

Controllers

Even with the proposed auto-tuning PID controller where the controller speed is op-

timized for different load conditions, the achievable control bandwidth is still limited

up to about 1/10 of the switching frequency, approximately the same as the maximum

bandwidth of the conventional voltage mode PWM controllers.

This limitation is mostly due to the natural sampling effect of the PWM mod-


ulation [60]. System phase margin is compromised due to the sampling and process

delays. In the following chapter, a nonlinear control technique that addresses these

bandwidth limitations and results in load transient responses limited by the filtering

components of the power stage only is presented. The technique further enables a

reduction in the size of the output capacitor.

Chapter 4

Continuous-Time Digital

Controller

In modern low-power dc-dc switch-mode power supplies (SMPS), fast response to

load transients and tight voltage regulation are among the most important require-

ments [1]. In cost-sensitive point-of-load (POL) applications and portable systems,

improvements in the load transient response usually result in a substantial reduction

of the size and weight of the power stage filter components [61]. In distributed power

systems (DPS) for personal computers and telecom, the faster control also reduces

voltage and current stress on downstream converters providing more reliable operation

of the supplied equipment. Even though numerous fast transient response methods

have been developed [14,25,27–30,34,35,62–73], in most commercial low-power SMPS,

analog voltage mode pulse-width modulation (PWM) or current-program mode reg-

ulators with quite limited bandwidth of the voltage loop [23, 60] are used. Among

the main reasons are operation at a constant switching frequency minimizing noise

problems, tight output voltage regulation, and simple cost-effective practical imple-

mentation [1].

70

Chapter 4. Continuous-Time Digital Controller 71

In the previous chapter, an auto-tuning controller has been presented and the

regulation performance is improved and is comparable to state-of-the-art analog con-

trollers using a linear compensation scheme. However, the obtained response may not

be sufficiently fast for the upcoming computer voltage regulation modules (VRMs)

applications where the load current slew-rate continues to rise and is expected to

exceed 120A/µs [15].

The main goal of this chapter is to introduce a new digital controller with load

transient response approaching physical limitations of a given power stage that is suit-

able for low-power SMPS. It can be realized with fairly simple components, allowing

full utilization of the advantages of digital implementation without introducing a sig-

nificant hardware overhead. The controller eliminates the delay-related problems of

digital systems by using a simple continuous-time digital signal processor (CT-DSP)

[74–77], which executes an algorithm for the optimal-time output voltage recovery.

The algorithm relies on the capacitor charge balance principle [28, 29, 62] [30, 65, 70]

and utilizes detection of the peak/valley point of the output voltage deviation to

eliminate the need for a costly current sensing/amplifying circuit [24]. The algorithm

requires information about the corner frequency of the power stage, which can be

obtained with the auto-tuning system presented in the previous chapter.

In the following section, we describe the system operation and briefly review basics

of continuous-time digital signal processing. Section 4.2 explains the capacitor charge

balance based algorithm of this controller. In Section 4.3 we describe the architecture

of a novel application-specific CT-DSP that implements the algorithm. Section 4.4

shows results obtained with a dc-dc converter utilizing the continuous-time digital

controller, as an experimental verification of the effectiveness of the proposed system

and method.


4.1 System Description

The continuous-time digital controller of Fig. 4.1 has two distinctive modes of output

voltage regulation. In steady-state it operates as a conventional digital PWM reg-

ulator producing signal c(t). Every period Tsw = 1/fsw, where fsw is the switching

frequency, the PID compensator calculates a new value d[n], controlling the digital

pulse-width modulator (DPWM), according to the following algorithm:

d[n] = d[n − 1] + Ae[n] + Be[n − 1] + Ce[n − 2] (4.1)

where, e[n], e[n − 1], and e[n − 2] are digital equivalents of the present value of

the output voltage error, and the errors of one and two switching cycles before,

respectively. The coefficients A, B, and C are used to establish the compensator gain

and zeroes [78].

As soon as a transient of the output voltage occurs, without waiting for any

clock signal, the mode control logic detects the deviation and switches the system

into dynamic mode. Then, the key part of this controller, the application-specific

continuous-time digital signal processor (CT-DSP) starts recovering the output volt-

age. The CT-DSP consists of a set of asynchronous comparators forming a windowed

flash analog-to-digital converter (ADC), delay cells with a very short propagation time

T << Tsw, and asynchronous digital logic. The CT-DSP utilizes the general concept

of the real-time processing of quantized analog signals in the digital domain, recently

introduced by Tsividis [74–77]. This concept makes the full use of the best properties

in both analog and digital signal processing. It combines the superior speed of ana-

log implementation with the flexibility and computational power offered by digital

hardware only. As shown in Fig. 4.1, without a sampling clock, any change at the


Figure 4.1: Continuous-time digital controller regulating operation of a buck converter(top); a simplified structure of the continuous-time digital signal processor (CT-DSP)used for fast voltage recovery (bottom).


input of the CT-DSP is instantaneously sensed by the asynchronous ADC, captured

by the set of delay cells, and processed by asynchronous digital logic. The elimination

of synchronous sampling avoids the aliasing effect that limits the bandwidth of con-

ventional digital systems and also minimizes the quantization error [76]. The error is

minimized due to the fact that at the comparators transition points, the value of the

input signal is exactly known and equal to the pre-defined thresholds. An additional

benefit of continuous-time digital signal processing is power savings [76]. The proces-

sor is active only when the input signal changes and, unlike clocked systems, does not

burn power in steady state. This allows for the design of digital controllers taking

very low-power, which is of very high importance in SMPS for low-power systems,

where the controller power consumption can have a significant effect on the overall

power supply efficiency [5]. In this particular case, the CT-DSP implements a capac-

itor charge balance algorithm. It accurately detects the time instant of the maximum

output voltage deviation as well as the magnitude of the peak/valley point. Based on

those two values only, the asynchronous digital logic determines the transistor on/off

times ton/toff that result in the fastest possible voltage recovery, i.e. optimal recovery

time. The results of the calculation are sent to the optimal sequence generator cre-

ating the optimal on/off transistor switching sequence u(t). When the mode control

logic detects that the voltage is in a close proximity to its reference Vref , the CT-DSP

passes the control task to the PID compensator.

4.2 Optimal Recovery Time Algorithm

The novel optimal recovery time algorithm developed in this thesis implements the

well-known charge balance principle [28–30,62,66,70], which can be described by ob-

serving Fig. 4.2 showing a buck converter’s output capacitor voltage and inductor


current recovery after a light-to-heavy load transient (or some other disturbance caus-

ing a loss of the output capacitor charge). Here, a modified algorithm is presented

and implemented with the CT-DSP.

The response can be divided into two phases. In the first phase, immediately

following the transient, the CT-DSP turns on the main switch Q1 (see Fig. 4.1)

increasing the inductor current iL(t). The first phase ends when the maximum voltage

deviation, in this case the valley point, is detected. At this time instant the load and

inductor currents are equal. In the following phase the CT-DSP calculates ton and

toff transistor switching times (Fig. 4.2) and produces a switching sequence such

that:

• At first, the inductor current further increases exceeding the load value, to make

up for the loss of the output capacitor C charge:

Q = C∆v (4.2)

where v is the maximum output voltage deviation during the transient.

• Right after the optimal switching sequence is completed, the inductor current

returns to its new steady state value IL = Iload.

In other words, the optimal-time response is obtained by sizing the shaded triangle

shown in Fig. 4.2, such that its area Qon + Qoff (the capacitor charge introduced by

the inductor current) is equal to Q.

To simplify the calculation of ton and toff times, and consequently CT-DSP im-

plementation, it is assumed that voltage deviation during the transient is relatively

small compared to its regulated dc value (less than 10 %), i.e. v ≈ Vref = Vout, which

for most properly designed power supplies is the actual case.


Figure 4.2: Optimal recovery after a disturbance causing the output voltage drop.Top: the output capacitor voltage, v(t); middle: gate-drive control signal c(t); bot-tom: inductor and load currents iL(t) and iload(t).


Under such an approximation, the amounts of charge comprising the shaded tri-

angle can be expressed as:

Qon =

∫ ton

0

∫ t

0

Vg − Vout

Ldtdτ (4.3)

Qoff =

∫ toff

0

∫ t

0

Vout

Ldtdτ (4.4)

where Vg is the input voltage of the converter.

Furthermore, by observing the waveform of Fig. 4.2, the relation between ton and

toff can be obtained geometrically:

ton

toff

=Qon

Qoff

=Vout

Vg − Vout

(4.5)

By combining (4.2), (4.3), and (4.4) and the capacitor charge balance equation,

Qon + Qoff = Q = C∆v, (4.6)

we derive the following expressions for the optimal transistor on and off times:

ton =

√

2LC∆vVout

Vg(Vg − Vout)= k1

D√1 − D

√∆v (4.7)

toff =

√

2LC∆v(Vg − Vout)

VgVout

= k1

√1 − D

√∆v (4.8)

where D is the steady state value of duty ratio, and k1 =√

2LC/Vout.

It can be easily shown that the same results for optimal ton and toff times are

obtained for a heavy-to-light load transition, with a difference that the switching

sequence is reversed. Analysis for other converter topologies yields optimal times

expressions of similar complexity.


4.3 Practical Implementation

Seemingly, the practical implementation of (4.7) and (4.8) requires a fairly powerful

processor as well as fast and accurate analog hardware. However, as shown in this

section, by utilizing digital correction of measurement errors and easily accessible

information obtained from the PID loop, this application specific CT-DSP can be

realized with simple elements.

4.3.1 Application Specific CT-DSP

A. System Architecture

The architecture of the application-specific continuous-time digital signal processor

for obtaining the optimal switching sequence and its waveforms during the recovery

from a voltage drop are shown in Figs. 4.3 and 4.4.

The CT-DSP has two main blocks. The first comprising comparators, delay cells,

and adders, captures the time instant and magnitude of the maximum deviation, i.e.

valley point. The second block is the optimal ton/toff calculator. It creates control

signals for the optimal switching sequence (Fig. 4.1). After a comparator i, 0 <

i < 2k, is triggered by a change of the output voltage, the corresponding continuous-

time digital signal y∗i (t) (Fig. 4.4) is generated. Like the signals of conventional

continuous-time systems, it can start at any point in time without a sampling delay,

which typically exists in clocked digital systems. The digital value of y∗i (t) is calculated

by an asynchronous adder. It is a stair function with the time step T and magnitude

proportional to the number of delay cells signal bi(t) has propagated through.

Chapter

4.

Contin

uous-T

ime

Dig

ital

Controller

79

Figure 4.3: The architecture of the application-specific continuous-time digital signal processor.


Figure 4.4: Main signals of the application-specific continuous-time digital signalprocessor during a voltage dip. Top: output voltage; bottom five: continuous-timedigital outputs.


The rise of y∗i (t) ends when the comparator i resets to zero or a neighboring one

is triggered. The change of comparators states is sensed by a simple detector (Fig.

4.3) and, at that point, the state of y∗i (t) is captured with D-latches. In this way the

conversion of a short time interval between two changes of comparators’ states into

a digital value is performed, with the time resolution equal to the propagation time

of a delay cell. The value produced by the comparator that is last to set and first

to reset is used to determine the time instant of the valley point shown in Fig. 4.2,

which is the time reference for ton and toff time intervals. For the voltage deviation

given with the example of Fig. 4.4 the continuous-time digital signal y∗5(t) is used for

the instant determination.

At the same time, detection of the magnitude of the maximum voltage deviation

is performed by the block named bi-falling edge detector and time instant correction

circuit, shown in Fig. 4.3. It detects the output of the comparator that first changes

its state from high to low and, as described shortly, uses the results of time-to-digital

output conversion, to precisely determine parameters of the extreme deviation point.

To eliminate the need for an extra ADC, out of the two forms of (4.7) and (4.8),

the equations for calculating ton and toff not requiring information about the input

voltage Vg are implemented. The obtained amplitude of the voltage deviation is

fed to a look-up table (LUT) that produces k1

√

∆v[n]. Then, the output of the

LUT is multiplied by D/√

1 − D and 1/√

1 − D, respectively. Immediately after the

computations of the optimal times are completed the results are sent to the optimal

sequence generator of Fig. 4.1, together with a peak detection signal st(t), used for

the generator triggering.

The steady-state duty ratio value D is obtained by low-pass filtering of the PID

compensator output, as shown in Fig. 4.3. Due to recent advances in mass-memory

design [79] the above mentioned square-root functions are also implemented with


look-up tables, which occupy a small silicon area.

B. Digital Correction of Measurement Errors

To accurately capture the point of the maximum voltage deviation, a large number

of very precise high-speed comparators and delay cells can be used. However, such a

solution would probably increase the controller complexity so that its implementation

is impractical, both in terms of the overall system cost and its power consumption.

Instead, we use a windowed flash ADC, with large quantization steps Vq, sized to

barely satisfy the output voltage regulation requirements [5]. This selection signifi-

cantly simplifies the hardware by minimizing the number of comparators , but at the

same time compromises the accuracy in finding both the magnitude and time instant

of the peak/valley point.

The effects of the coarse ADC resolution are demonstrated in Fig. 4.5. We can see

that, since the valley occurs in between two quantization thresholds, the calculation

of the deviation parameters is delayed by ∆t. It is possible only after y∗i (t) reaches its

final value Nmax. Also, an error in amplitude measurement ∆verror can be observed.

To compensate for these, digital error correction is applied. First, the delay is

approximated as ∆t = NmaxT/2 and used for the correction of the calculated ton

value, as shown in Fig. 4.3. The estimated delay time is also used for effective

resolution improvement, where the quantization error for the buck converter of Fig.

4.1 is calculated as

∆verror =1

C

∫ t0+∆t

t0

∆iL · dτ =1

C

∫ t0+∆t

t0

Vg − Vout

L· τ · dτ (4.9)

=1

2

Vg − Vout

LC∆t2 = k2

1 − D

D∆t2 (4.10)

and added to the initially measured voltage deviation ∆vmeas, where k2 = Vout

2LC.


Figure 4.5: Signals of the CT-DSP during a voltage dip. Top to bottom: outputvoltage v(t) , inductor current iL(t), the output of the last triggered comparator bi(t),corresponding continuous-time digital signal y∗

i (t), the optimal switching sequenceu(t).


It might be interesting to note that fast processing of the signals during transients

could also be obtained with an over-sampling ADC and a powerful processor. How-

ever, to achieve the same time resolution as that of a delay cell, a very high frequency

ADC would be needed. For example, for a time step of 1 ns, easily achievable with a

5-transistor delay cell [7], an ADC with 1 GHz sampling rate would be required. Such

an ADC is probably more complex and costly than a complete low-power SMPS.

4.3.2 Optimal Sequence Generator

The optimal sequence generator is shown in Fig. 4.6. It comprises two delay lines

for generating ton and toff time intervals, an S-R latch, and 2-XOR gates. An out-

put voltage deviation activates the generator. At that time, the switching selector

recognizes the type of the transient and the SR-latch controlling the transistor Q1 of

Fig. 4.1 is set or reset, through the u/o signal. After the maximum voltage devia-

tion is sensed and optimal times calculated either the triggering pulse st(t) for the

ON-Delay line or st′(t) for the OFF-delay line is created, depending on the type of

transient. As a result, u(t) goes from high to low after ton in the case of a voltage dip

or in the other direction after an overshoot. As soon as the initially excited delay line

changes its output, it triggers the opposite line as well as the SR latch changing the

value of u(t). After the signal propagates through the second delay line, the optimal

switching sequence is completed and the PID compensator of Fig. 4.1 resumes voltage

regulation.


Figure 4.6: Optimal sequence generator.

4.3.3 Influence of the Output Capacitor and LC Parameter

Variations

A. Equivalent Series Resistance

Even though this system is designed for low-power SMPS, where predominantly ce-

ramic capacitors with very small equivalent series resistance (ESR) are used, it might

be interesting to analyze the influence of a non-negligible ESR. Then, the output

capacitor can be modeled as shown in Fig. 4.7 and the output voltage vout(t) written

as

vout(t) = vc(t) + Resric(t) = vc(t) − Resr (iL(t) − iload(t)) (4.11)

where Resr is the ESR value and vc(t) is the voltage across the ideal capacitor. Ide-

ally, ESR should not affect the optimal switching sequence. At the point where the

inductor and load currents are the same, i.e. ic(t) = 0, the ESR does not have any

influence on the output voltage deviation and the equations for the optimal sequence


remain the same as in the ideal case. The sequence should start when the zero ca-

pacitor current is detected and have the ton and toff times defined by (4.7) and (4.8).

However, as described below, ESR causes the peak/valley point to happen at ic(t) 6= 0

and erroneous detection of the key time instant. As a consequence the ton and toff

times can be miscalculated and a sub-optimal switching sequence created.

Figure 4.7: Circuit model of the output filter of a buck converter that includes ca-pacitor ESR.

To quantify this influence we observe the buck converter of Fig. 4.1, as an exam-

ple. Again, a light-to-heavy load transient is analyzed, where at t = 0 a step of Iload

occurs and the CT-DSP immediately turns on the main switch Q1 responding to the

transient. For this case (4.11) can be rearranged as

vout(t) = Vout + Resr

(

Vg − Vout

Lt − ∆Iload

)

+1

C

∫ t

0

(

Vg − Vout

Lt − ∆Iload

)

dt(4.12)

Now the valley happens at the point where the time-derivative of (4.12) is zero.

By finding the derivative and replacing the result in (4.12) both the time instant of

the valley point tesr, and its magnitude ∆vesr can be obtained:

tesr =L

Vg − Vout

∆Iload − CResr (4.13)

∆vesr =

(

∆IloadtesrC

− Vg − Vout

LC

t2esr2

)

+ Resr

(

∆Iload −Vg − Vout

Ltesr

)

.(4.14)


It can be seen that the ESR causes the valley to happen before ic(t) = 0 (while

iload(t) is still larger than iL(t)) and, consequently, a pre-mature triggering. This

effect also increases the magnitude of the valley and, as shown in Section 4.4, in most

of the practical cases, causes an undershoot and a slower than ideal response.

From (4.13) we can see that compared to the ideal case, the valley leads by

τesr = CResr. If τesr is known with a certain accuracy it can be taken into account

and the CT-DSP algorithm modified accordingly. More precisely, the sampling of the

peak deviation and the triggering of the switching sequence can be delayed by τesr to

compensate for the ESR influence.

B. LC Parameter Variations

From (4.7) and (4.8) it can be seen that the parameter k1, depends on the L and

C values affecting the calculation of ton and toff times. Hence, the tolerance of the

components and their changes due to external influences can result in a non-optimal

switching sequence. However, since k1 depends on the square root of the LC product,

this effect is often small over a relatively large range of product variations, causing a

slight undershoot or overshoot that can be compensated by the PID regulator.

In the case of a large variation, the auto-compensation method described in the

previous chapter can be applied. Alternatively, gain k1 can be adjusted in two steps,

as demonstrated in a predictive current mode controller [80] suffering from a similar

problem. First, the initial value of k1 can be set, then, in the next step, it can be

adjusted depending on the size of undershoot/overshoot. A similar two-step gain cor-

rection technique for the compensation of the LC variations has also been applied in a

modification of the previously mentioned all-digital optimal controller [69]. Alterna-

tively, the LC product can be estimated from the frequency of limit-cycle oscillations,

as described in [81].


4.4 Experimental Systems and Results

Based on the diagrams shown in Figs. 4.1, 4.3 and 4.6, an experimental controller

system was built around a 5 V to 1.8 V, 5W buck converter operating at a switching

frequency of fsw = 400 kHz. The continuous-time digital controller is implemented

with an FPGA based system as well as with commercially available comparators and

programmable delay lines. To design an asynchronous flash ADC, only 8 comparators

were used and a constant quantization step of Vq = 25 mV was set. The delay lines are

comprised of 64 cells, each having 40 ns propagation time. They provide sufficiently

long total delay to capture a time interval between two successive triggerings of CT-

DSP’s comparators which is usually shorter than the switching period. It should be

noted that in on-chip implementation, where it is desired to minimize silicon area,

the number of cells can be significantly reduced by sharing only one delay line among

all comparators and using current-starved delay elements. The propagation time of

the current starved cells can be shorter than 1 ns, allowing the use of the continuous-

time digital controller in SMPS operating at switching frequencies of several MHz

and higher.

4.4.1 Functional Verification

To verify the operation of the developed continuous-time digital signal processor, its

key signals were observed during a 0.2 A to 1.5 A load transient. The results are

shown in Figs. 4.8 and 4.9. As it can be seen from Fig. 4.8, right after the transient,

the mode signal m(t) (also shown in Fig. 4.1) enables the CT-DSP and the transistor

Q1 stays in on state (had it been open it would have turned on immediately). When

the peak point is detected, the detection signal st(t) is activated, with a delay ∆t.

The remaining part of the optimal u(t) is generated by the programmable delay line


Figure 4.8: Signals of the CT-DSP during a 0.2 A to 1.2 A load transient. Ch.1:Output voltage v(t), 200 mV/div; Ch 2: gate-drive signal u(t); Ch.3: control signalfor load transient circuit; D0-D3: binary-weighted continuous-time digital error e∗(t)of the PID compensator; D6: mode control signal m(t); D7: peak detection signalst(t). Time scale is 2 µs/div.

and the voltage recovers in a single on-off switching cycle. Once the steady state is

reached, the mode control signal disables the CT-DSP and the PID compensator of

Fig. 4.1 used for the regulation and compensation of small voltage variations is active

again. Because the optimal sequence directly brings the system to the new steady

state while the error is zero and the information about D is known the bumpless

transfer between controls is obtained. Waveforms of the binary weighted error signal

that is fed into the PID compensator are also shown.

The waveforms also verify proper operation of the digital error correction block

described in Section 4.3.1.B. It can be seen that due to the coarse quantization steps

of the flash ADC the peak detection signal st(t) is delayed. Still, the previously

described algorithm takes the delay into account and corrects the transistor on-time

to achieve virtually optimal response.


It should be noted that compared to the ideal case, shown in Fig. 4.2, a slight

delay in the reaction to a load transient, indicated by signal m(t), exists. This is

because of the digital logic for load transient recognition that only reacts to output

voltage variations larger than 2 quantization steps and the finite propagation time of

the FPGA’s digital circuits. Since the ton and toff times are calculated with respect to

the peak/valley point, this delay does not affect CT-DSP algorithm but does influence

the overall response time. If the CT-DSP is fully implemented on a chip, this effect

can be significantly minimized by using faster application-specific digital logic and/or

a simple trans-impedance sensor for transient detection.

Fig. 4.9 shows experimental voltage and current waveforms similar to the idealized

signals of Fig. 4.2. As described in Section 4.2, over the duration of the optimal

switching sequence the inductor current exceeds the load value to make up for the

lost capacitor charge and returns to the new steady state right at the end of the

sequence. Also, it can be seen that the PID compensator completely eliminates

the steady state error, which the CT-DSP itself is not able to accomplish, due to

components variations and other imperfections that are not taken into account in the

optimal sequence calculations.

4.4.2 Performance Comparison

To verify the advantages of the continuous-time digital controller over commonly

used voltage mode digital PWM regulators, the load transient response with and

without the CT-DSP based recovery mechanism was compared. The conventional

controller has a PID compensator designed such that the crossover frequency of the

system is fc ≈ fsw/15, which is a common choice for a conventional digital PID de-

sign [17] [16] where the sampling nature imposes bandwidth limitations. The results


Figure 4.9: Voltage and current waveforms of the experimental system during a 0.2A to 1.2 A load transient. Ch.1: Output voltage v(t), 150 mV/div - ac; Ch.2: thecontrol signal of a load change circuit; Ch.3: Gate drive signal; Ch.4: Inductor currentiL(t), 1 A/div - dc; Time scale is 5 µs/div.

for heavy-to-light and light-to-heavy load transients are shown in Figs. 4.10 to 4.13.

They verify that the CT-DSP results in a significantly improved load transient re-

sponse. In this case, the recovery time is about three to four times shorter and the

overshoots/undershoots are about three times smaller, allowing for the proportional

reduction of the output capacitor [61]. A detailed performance comparison between

the PID controller and CT-DSP system implemented in this buck example can be

found in Table 4.1. The response of the CT-DSP is practically limited by the power

stage inductor and capacitor values only. The maximum voltage deviation in response

to a load change of ∆I can be expressed as the following way:

∆v =∆I2L

2C(Vg − Vout)(4.15)


Figure 4.10: PID controller’s response to a 0.2 A to 1.2 A load step change. Ch.1:output voltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drivesignal, 2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.

Figure 4.11: CT-DSP controller’s response to a 0.2A to 1.2A load step change. Ch.1:output voltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drivesignal, 2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.


Figure 4.12: PID controller’s response to a 1.2 A to 0.2 A load step change. Ch.1:output voltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drivesignal, 2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.

Figure 4.13: CT-DSP controller’s response to a 1.2 A to 0.2 A load step change. Ch.1:output voltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drivesignal, 2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.


Table 4.1: Controllers’ Load Transient Response ComparisonPID PWM Controller CT-DSP ControllerBandwidth=1/15fsw

Light-to-heavy Transient 200 80Voltage Deviation (mV)Light-to-heavy Transient 60 8

Settling Time (µs)Heavy-to-light Transient 230 125Voltage Deviation (mV)Heavy-to-light Transient 60 8

Settling Time (µs)

4.4.3 System Behavior for Parameter Variations

To show the influence of LC variations and that of the ESR, two modifications on

the power stage of the original system were performed while the CT-DSP algorithm

was left unchanged. First, the value of the output ceramic capacitor was changed

by 20%. Then, the widely available ceramic capacitor with Resr smaller than 5 mΩ

was replaced with a tantalum capacitor having an ESR that was approximately seven

times larger.

Fig. 4.14 shows a load transient response for the case when the output capacitance

is 80% of the rated value. It can be seen that in this case, the ton and toff times, given

by (4.7) and (4.8) are miscalculated so they are larger than optimal, causing a 70 mV

overshoot after the switching sequence is completed. This overshoot is followed by

a much smaller dip. Even in this case the load transient causes 2.5 times smaller

deviation than when the PID regulator is used and 1.5 times shorter settling time.

As mentioned earlier, by applying a two-step gain correction algorithm [69,80] or the

auto-tuning methods presented in [16, 81] this response can be improved.

A load transient response with a tantalum capacitor having large ESR (Resr ≈


Figure 4.14: CT-DSP controller’s response to a 0.2 A to 1.2 A load step change forthe case when the output capacitance is 20 % smaller than the rated value. Ch.1:output voltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drivesignal, 2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.

35mΩ) is shown in Fig. 4.15. As described in Subsection 4.3.3.A, the ESR causes

earlier triggering, a shorter capacitor charging time than optimal, and incomplete

recovery of the lost capacitor charge after the sequence produced by the CT-DSP is

completed. However, since at the end of the sequence a new steady-state is almost

reached and voltage deviation is relatively small, the PID compensator compensates

for the mismatch. By comparing the response with that of the conventional PID,

shown in Fig. 4.10, we can see that even in the presence of a large ESR the proposed

method significantly improves the load transient response.


Figure 4.15: CT-DSP controller’s response to a 0.2 A to 1.2 A load step change forthe case when the capacitor ESR is 7 times larger (Resr ≈ 35 mΩ). Ch.1: outputvoltage v(t), 150 mV/div - ac; Ch.2: load change command; Ch.3: gate drive signal,2.5 V/div; Ch.4: inductor current iL(t), 1 A/div. Time scale is 20 µs/div.

4.5 Summary of Results

A voltage mode digital controller for low-power high-frequency dc-dc converters that

has a recovery time approaching physical limitations of a given power stage is pre-

sented. To achieve such a quick response, during transients the controller utilizes

an asynchronous windowed flash analog-to-digital converter, delay lines, and digital

logic forming an application specific continuous-time digital signal processor (CT-

DSP), which is the key part of this new system. The CT-DSP processes signals that

are continuous in time and have a quantized magnitude to exploit the advantages

of both digital and analog worlds. By eliminating sampling, the characteristics for

conventional digital systems such as the aliasing and delay problems are eliminated,

which allows significant increase in processing speed. On the other hand, the quanti-


zation in amplitude makes advanced data processing, the main advantage of digital

implementation, possible. To eliminate the need for current measurement, and con-

sequently, significantly simplify the system implementation, the CT-DSP implements

a capacitor-charge balance based algorithm. Based on the maximum amplitude of

voltage deviation and its time instant, the hardware calculates the optimal on and

off times of the power switch resulting in virtually the fastest recovery time possible.

To further ease the hardware requirements, a digital error correction logic, minimiz-

ing the magnitude quantization effects and compensating for delays in the system, is

applied. An FPGA-based controller prototype was built and tested with a low-power

dc-dc converter operating at a 400 kHz switching frequency. The experimental results

show very fast recovery time limited by the values of the power stage inductor and

capacitor only.

Chapter 5

Conclusions and Future Work

This thesis presents two new digital controllers for low-power switch-mode power

supplies (SMPS). Compared to traditional solutions, the controllers have improved

transient response, power processing efficiency and allow auto-tuning of the low-power

SMPS.

5.1 Limit-Cycle Oscillation based Auto-Tuning

Controller

The first controller developed in this thesis utilizes a new limit-cycle oscillation based

(LCO) auto-tuning method. In this method, the power stage parameters, such as

the corner frequency of the output filter and the load value, are estimated from

intentionally introduced limit cycle oscillations in the first phase. In the following

phase the estimated parameters are used for improving the dynamic response through

an on-line PID compensator adjustment. The extracted parameters are also used

to improve the overall efficiency of the SMPS. From the estimated load value, an

optimal switching sequence of a segmented power stage is selected such that the sum

98

Chapter 5. Conclusions and Future Work 99

of switching and conduction losses is optimized for each operating point.

The operation of the controller is successfully verified with an experimental proto-

type having a load transient response comparable to state of the art analog solutions

with up to 7% higher processing efficiency.

The LCO auto-tuning system can serve as a foundation for building power stage

“state-of-health monitoring” systems and universal “plug-and-play” digital controllers.

For example, by monitoring the output capacitor or load value, the state-of-health

monitoring systems will be able to detect potential failures of the SMPS in advance

and take preventive action. The “plug-and-play” digital controllers will be able to

automatically detect the parameters of the power stage they are connected to and, ac-

cordingly, adjust their mode of operation. They will be able to eliminate the need for

a case-by-case compensator design and significantly reduce the SMPS development

time.

5.2 Continuous-Time Dual-Mode Controller

To overcome the inherent bandwidth limitations of voltage-mode PWM control schemes

caused by the natural sampling effect, a digital controller with a transient response

approaching the physical limitations of a given power stage is developed. In steady-

state, the controller operates as a conventional PWM voltage-mode controller. During

transients the controller utilizes an application specific continuous-time digital signal

processor (CT-DSP) to achieve output voltage recovery in the optimal time, i.e. the-

oretically the fastest possible time.

The CT-DSP, which, to the best of our knowledge, is the first time that this system

is used in power electronics applications, combines the advantages of analog and

digital implementation in a single device. It consists of an asynchronous flash ADC,


a set of delay-lines, and simple digital logic. The ADC and delay lines, which comprise

the analog part of the system, eliminate the sampling and consequent aliasing effect

allowing for data to be processed in real-time.

The digital part implements a novel algorithm that calculates optimal on and

off times for a switching transistor that ensure recovery from a transient through

a single on/off action of the transistor. The algorithm is based on the capacitor

charge balance principle and the detection of the peak/valley point of the output

capacitor voltage. This approach eliminates the need for a current measurement

circuit, which is common in existing charge balance based methods. Therefore, it

significantly simplifies the system implementation.

Furthermore, a new digital error correction scheme, alleviating the quantization

effects of the ADC in conventional continuous-time digital signal processors, is in-

troduced. The effectiveness of the continuous-time digital controller is verified both

through experiment and simulation. An FPGA-based controller prototype was built

and tested with a low-power dc-dc converter operating at a 400 kHz switching fre-

quency. The experimental results verify very fast recovery time approaching the

physical limitation of the power stage.

5.3 Limitations and Comparison of the Two Con-

trollers

The auto-tuning controller is predominantly designed as a system that can be obtained

through simple modifications of the existing digital voltage mode PWM structures.

It does not require highly specialized hardware for implementation and, as such,

is simple to implement. However, even though it significantly improves dynamic


response, flexibility, and efficiency of the low-power SMPS, its bandwidth is still

limited by the inherent sampling effect.

The CT-DSP controller provides a solution for eliminating the bandwidth limita-

tion and pushing the speed of the transient response to the physical limits. However,

its implementation requires simple, yet specialized hardware. In particular, it requires

the design of an asynchronous ADC and delay lines, which are not commonly present

in conventional digital controllers. The developed FPGA based prototype can serve as

a good proof of concept but is not the most suitable implementation from a practical

point of view. Besides the cost issue, problems with temperature sensitivity of digital

logic based delay lines could significantly influence the behavior of the systems. The

delay time varies significantly with temperature and consequently affects the optimal

switch times of the control sequence. Hence, it requires development of application

specific on-chip integrated blocks.

5.4 Future Work

Future work can include two streams. First is the development of a more sophisti-

cated auto-tuning algorithm that further estimates capacitor ESR value and performs

continuing auto-tuning and the second is on-chip integration of the continuous-time

digital controller.

The auto-tuning could include online identification of the output capacitor ESR/ESR-

zero, which can play a critical role in the operations of both controllers. Preliminary

simulation results of Appendix C show that the recursive least square (RLS) [43]

based parameter estimation is a promising candidate for the task. However, at this

point, the results can only be used as a scientific foundation for future research. More-

over, the computational burden and implementation challenges that come with this


method need to be justified in the future.

The on-chip implementation of the continuous-time digital controller can reduce

the overall cost of the system. It can also include specialized delay lines with tem-

perature calibration that eliminate previously mentioned problems.

Appendices

103

Appendix A

Matlab Routines Used in Thesis

Two of the Matlab routines used in this thesis are provided here. They are for the

PID compensator design of Chapter 3 and the RLS parameter estimation of Appendix

C.

A.1 Matlab Routine for Compensator Design

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

% Matlab Routine for PID Design %

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%input voltage

Vin=9;

% voltage reference

Vref=3.3;

104

Appendix A. Matlab Routines Used in Thesis 105

%voltage divider gain

H=1;

%Resolution of DPWM

RES=8;

%Total number of DPWM steps

LIM=2^RES;

%Half window range of the ADC

ADC_half_window=0.25;

%Resolution of the ADC

ADC_RES=5;

%Total number of ADC quantization steps

ADC_LIM=2^ADC_RES;

%Power stage inductance

L=10e-6;

%Power stage capacitance

C=40e-6;

%Inductor series resisance including Rds_on

Rl=0.1;


%Capacitor ESR

Rc=0.1;

%Open loop gain of the power stage

gain=Vin*Rc/L;

%Numerator of the power stage

B=[1 1/C/Rc];

%Denominator of the power stage

A=[1 (Rc+Rl)/L 1/C/L];

%Transfer function of the open loop converter without Resistive load G(s)

G=tf(gain*B, A);

%ADC gain

Gad=ADC_LIM/(2*ADC_half_window);

%DPWM gain

Gdpwm=1/LIM;

%DC gain of the converter plus ADC and DPWM

gain_G=Gad*H*Gdpwm*Vin;

%Transfer function of the open loop converter without Resistive load

%including adc gain and voltage divider


G=Gad*H*Gdpwm*G;

%Switching frequency

fs=400e3;

%modeling of the ADC conversion delay

T_delay=0.5/fs;

%Converter corner frequency

fc=sqrt(1/L/C)/2/pi;

%PID centre frequency is set to be close to corner frequency

fz=0.99*fc;

%Desired controller bandwidth, at best, is 1/10 of the switching frequency

bw=40e3;

%Desired damping ratio to be set in PID

damp=0.8;

%Calculation of the controller gain with assumption that ESR of C is small

gain_Cs=2*pi*fz*(bw/fz/gain_G);

%Design of the continuous time PID

Cs=gain_Cs*tf([1 2*damp/sqrt(L*C) (2*pi*fz)^2],[(2*pi*fz)^2 0]);


%digital transformation of the PID

Cs2=c2d(Cs,1/f,’matched’);

% add one cycle delay to make it casual

Z=tf(’z’); Cs2=Cs2/Z;

% zero-order hold transform for power stage discrete time equivalent

G2=c2d(G,1/f,’zoh’);

%Bode plots of the total loop

bode(Cs2*G2);

A.2 Matlab Routine for RLS Identification

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

% RLS Power Stage Parameter Estimation Algorithm %

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

%Initialize the auto-regressor vector

d=[0 0 5 5]’;

%Initialize the Auto-covariance matrix

c=100*eye(4);

%Initialize parameter estimate vector


theta=[-2 1 0.01 0]’;

%length of the Ac component duty command input vector from simulink

ll=length(duty_ac);

%Initialize parameter estimate matrix

THETA=theta;

%Initialize the estimation error vector

EP=[0];

%Recursive calculations start here

for i=4:ll

%update of auto-regressor

d=[error(i-1) error(i-2) duty_ac(i-1) duty_ac(i-2)]’;

%update of the estimation error

ep=-error(i)-theta’*d;

%update parameter vector

eps=d’*c*d; theta=theta+(c*d*ep)/(1+eps);

%update of the Auto-covariance matrix

c=c-(c*d*d’*c)/(1+eps);


%update of parameter estimate matrix

THETA=[THETA,theta];

%update of estimation error vector

EP=[EP,ep];

%End of the recursive calculations

end

Appendix B

Two-Step Tuning Procedure

B.1 Two-Step Tuning Concept

Figure B.1: Block diagram of the two-step tuning controller

The auto-tuning procedure presented in Chapter 3 is called one-step tuning be-

cause it is completed with a single test phase where LCO at power stage corner

111

Appendix B. Two-Step Tuning Procedure 112

frequency is excited and measured. Sometimes, especially when the estimates of

power stage parameters are not reliable, it is preferred to tune the compensator with

multiple LCO tests to meet specific performance criteria such as control bandwidth,

phase margin etc. [16] [17]. Here, we propose a simple two-step tuning procedure,

which provides guaranteed stability and a precise estimate of the control bandwidth

and phase margin. A block diagram of the proposed two-step auto-tuner is shown in

Fig. B.1.

The two-step auto-tuning process can be explained through the following example

assuming again that a buck-converter with control-to-output transfer function,

Gvd(s) =Vg

1 + sQω0

+ s2

ω2o

∼= Vout/D

1 + sQω0

+ s2

ω2o

(B.1)

, is the power stage, where corner frequency ω0 and Q-factor are determined with the

power stage components and its load [81]. The value D defines the steady-state duty

ratio value.

As stated in Chapter 3, during a LCO test, the resolution of the DPWM is

intentionally reduced by sending truncated binary control signal dtr[n] to its input. As

a result a strong nonlinearity causing LCO is introduced allowing dynamic adjustment

of the PID compensator parameters. After the first LCO test the PID compensator

zeroes ωz1 and ωz2 are selected according to the identified power stage as shown in

Chapter 3. The intermediate design of the PID has the following transfer function:

C(s) = KC

1 + sQzωz

+ s2

ω2z

s= KC

1 + 2ξzs

ωz+ s2

ω2z

s(B.2)

where in this case, the damping factor ξz can be made a design parameter following

the design procedure in Section 3.3.1. Initially the gain KC is set at a low value and


the self-tuning compensator is switched into the second auto-tuning mode.

As shown in Fig. B.2, the resulted loop gain, TAT2(s), in this mode reassembles

the behavior of a pole at the origin and the whole system behaves as an integrator,

i.e.

TAT2(s) = MDPWM(|d|, s)C(s)Gvd(s)MADC (B.3)

where MDPWM ,MADC are the equivalent gains of the DPWM and ADC respectively.

To complete the compensator design and achieve the desired bandwidth, the ap-

propriate gain of the compensator needs to be determined. As the second step of

the auto-tuning, another test introducing LCOs at the desired crossover frequency

i.e. control bandwidth is performed, during which the appropriate gain of the com-

pensator, KC , is determined from the measurements of the small signal gain of the

nonlinear element, i.e. DPWM. Consequently, a predefined control bandwidth of the

controller fbw[n] is obtained. In both steps, the resolution of the ADC is kept suf-

ficiently high, so that its nonlinear quantization effects are negligible compared to

those of the DPWM. This is based on the fact that at the amplitude and frequency

of the LCO the gain of the nonlinear element, i.e. DPWM, is automatically adjusted

to result in unit loop gain TAT2(s). In other words, if the LCO occur at a predefined

crossover frequency, the additional gain of DPWM will make the compensator gain

KC equal to the desired value, KI , to use when the nonlinear effect is eliminated and

the controller operates in a regular mode utilizing the high-resolution DPWM.

The abovementioned two-step process is performed during the second auto-tuning

step, when all switchers of Fig. B.1 are in the position a.t.2. In this case, the PI

compensator of the first step is replaced with the initially designed low-gain PID

(B.2) and a programmable phase shift block is added. The programmable phase shift


Figure B.2: Bode plots of systems during second step tuning

introduces additional −90 at the desired frequency, fbw[n], and results in a total

phase shift of 180 and LCO at the same frequency. In this study, the phase shift

is provided by a second order low pass filter (LPF), which introduces a 90 phase

lag at its centre frequency. After the LCOs are initiated the gain of the DPWM is

determined through measurement of the ratio of variations of the truncated signal

dtr[n] and its high resolution value (see Fig. B.1).

Mdpwm =KI

KC

=∆dtr[n]

∆d2[n](B.4)

Finally, the self-programming PID is switched to regular mode and the initial

low gain, KC , is increased by a factor of Mdpwm to meet the desired controller gain,

KI , as shown in B.4. It should be noted that in an actual system implementation,

the bandwidth of the controller can be compromised by the processing delays of

the other elements of the system caused by finite processing and analog-to-digital

conversion times. In this case, the control delays need to be taken into account and


the corresponding desired bandwidth needs to be adjusted accordingly. For example,

the LCO frequency during the second phase of tuning can be less than the centre

frequency of the additional phase shifter. The control delays make the system phase

margin less than 90 degree at high frequencies. Therefore LCO could happen at

frequencies where the phase shifter provides a phase lag less than 90 degrees. One

solution to this problem could be to make the second order LPF based phase shifter

less-damped so that the provided phase lag drops from 45 to 90 degrees in a narrow

frequency window. By adjusting the damping of the LPF the accuracy of bandwidth

control can be improved.

B.2 System Validation

Figure B.3: Input (bottom) and output (top) of the nonlinear element (DPWMquantizer)

Based on diagrams shown in Fig. B.1 a Matlab/Simlink model is built and the

results proving the proper operation of the system are obtained. Results of first step


Figure B.4: Transient response of the auto-tuned system to a load current changefrom 0.4A to 1A

auto-tuning have been explicitly reported in Chapter 3 and will not be included here.

Results of the newly proposed second step auto tuning are shown in Fig. B.3 and B.4.

In order to achieve a control bandwidth of 40 kHz, a phase shifter block is inserted.

The truncated DPWM signal dtr[n] and its high resolution input signal d2[n] are

shown in Fig. B.3 respectively. The gain of DPWM is equal to 5 by applying (B.4).

Figure B.4 shows the load transient response of the auto-tuned system for an output

current change from 0.4A to 1A. It is seen that the output is able to settle down in

6 switching cycles (30µs), which is comparable to state-of-the-art analog solutions.

Appendix C

RLS based Parameter Estimation

of SMPS

It is shown in Chapter 3 and 4 that in both the linear PWM and nonlinear CT-DSP

control schemes the output capacitor ESR influences the compensation performance.

Although there is a trend in the industry to move toward using ceramic capacitors

having very low ESR, it is not unusual to find other types of capacitors with larger

ESR in today’s low-power SMPS designs. Thus, it is desirable that the ESR value

can also be identified online and taken into account in the PID design. As shown

in [42], a pole located at the same location as the ESR zero can then be introduced

to the PID compensator to cancel out its effect.

In this appendix, the recursive estimation methods (REMs) [43] that could po-

tentially overcome the limitations of the presented systems by extracting ESR and/or

ESR zero information is reviewed. Among various REMs, the recursive-least-square

(RLS) method is of the most interest. Simulations are performed on a Matlab/Simulink

model and some preliminary results show that accurate estimation and quick con-

vergence are obtained. The practical implementation challenges of the RLS based

117

Appendix C. RLS based Parameter Estimation of SMPS 118

auto-tuning system are also discussed.

C.1 RLS Method for Parameter Estimation

Real-time process parameter estimation is a key element in every adaptive control

problem. Various types of estimation methods have been developed and extensively

analyzed in the general control field [43]. Among them, recursive algorithms based

methods show promising results and a relatively simple structure. However, it is still

considered too complex in hardware implementation and computationally demanding

for use in SMPS controllers. Despite an attempt of using a costly DSP to estimate

disturbance characteristics using a DSP in [46], the application of recursive algo-

rithms for power stage parameter estimation in low-power SMPS is still absent in the

literature. In this section, we would like to investigate the possibilities of employing

recursive algorithms with application specific integrated circuits for SMPS parameter

estimation.

The key elements of such a recursive estimation scheme consist of the selection of

model structure, experiment design, parameter estimation conditions and system val-

idation which will be discussed in the following sections. Some design considerations

are also suggested.

C.1.1 Model Selection and the RLS Algorithm

Linear auto-regression (AR) system models are naturally selected for the parameter

estimation of digitally controlled SMPS as it is a time-sampled single-input/single-

output (SISO) system [43]. As an example, a discrete-time transfer function of a buck

converter taking into account the capacitor ESR zero can be expressed with a second


order z-domain transfer function as:

Gvd(z) =b1z + b2

z2 + a1z + a2(C.1)

or in difference equation form as:

y[n] = −a1y[n − 1] − a2y[n − 2] + b1u[n − 1] + b2u[n − 2] (C.2)

where y[k] is the output voltage error signal and u[k] the input duty ratio signal.

The equation (C.2) can be rewritten in a matrix form:

y[n] = ϕT [n − 1] · θ (C.3)

where θT= [a1 a2 b1 b2 ] is the parameter vector and ϕT [n − 1]=[ -y [n-1 ] –y [n-2 ]

u[n-1 ] u[n-2 ] ] ] is often called the auto-regressor vector.

Because θT is not explicitly known, an estimate θT is used in (C.3) to estimate

the output:

y[n] = ϕT [n − 1] · θ (C.4)

The problem now is to find parameter vector θT in such a way that the output

computed from the model in (C.4) agree as closely as possible to the measured output

voltage error y[n] in the sense of least squares. In other words, the following least-

square loss function needs to be minimized in a recursive manner:

J(θ, n) =1

2

n∑

k=1

(y[k] − ϕT [k − 1]θ[k − 1])2 (C.5)


Among the various recursive estimation algorithms in the literature, the recursive

least square (RLS) approach shows fast convergence and accurate estimation results.

For simplification purposes, we will not show the detailed derivation of the algorithm

but rather show the recursive adaptive law directly [43]. The classic RLS algorithm

for estimating all coefficients in (C.2) and (C.3) follows the iterative steps below:

θ[n] = θ[n − 1] + K[n](

y[n] − ϕT [n − 1]θ[n − 1])

K[n] = P [n]ϕ[n − 1] = P [n − 1]ϕ[n − 1](

I + ϕT [n − 1]P [n − 1]ϕ[n − 1])−1

P [n] = P [n − 1] − P [n − 1]ϕ[n − 1](

I + ϕT [n − 1]P [n − 1]ϕ[n − 1])−1

ϕT [n − 1]P [n − 1]

=(

I − K[n]ϕT [n − 1])

P [n − 1]

(C.6)

Initial values for θ[0] and the square covariance matrix P [n] are given as [D D 0

0] and an identity matrix respectively. The procedure takes in the input and output

of the system being identified and minimizes the energy J(θ, n) i.e. least squares of

parameter estimation errors as shown in (C.5) recursively at the sampling frequency.

If the system model’s order is equal to or greater than that of the actual process, all

model coefficients will eventually converge to the real system parameters [43]. Note

that this approach accurately estimates the capacitor ESR zero from parameters b1

b2 in (C.2).

In order to obtain the input and output signals with necessarily large amplitudes

in the closed loop, the system needs to be persistently excited. The selection of the

persistent excitation signal is proposed next.


C.1.2 Design of Experiment

For the power stage identification concerned in this thesis, the only estimator input is

the duty ratio signal applied to the switching converter. The properties of this input

signal are crucial to the accuracy of the estimation. As stated in [43], in order to have

the parameter estimates converge to their true values, a persistent exciting signal

(PES) with sufficient high order should be applied to the system in the SI process.

It has been also shown that a sinusoid can be PES of order 2 and a periodic signal

with period n can be PES of at most order n. To identify a second order system as

in our buck converter example, it is natural to excite the system with intentionally

introduced high frequency limit cycle oscillations (HF-LCO). Detailed steps of the

initialization of high frequency LCO can be found in appendix A. As we know, the

HF-LCO signal is not a pure sinusoid but a periodic signal with high order harmonics

of the HF-LCO fundamental frequency. Thus, it is PES of order 3 or more as long as

the period of the HF-LCO is longer than 3 sampling period. This is true for most of

the cases when the HF-LCO is excited at the control bandwidth frequency which is

usually 10 times lower than the switching frequency. In other words, it has a period

consisting of about 10 switching cycles. Therefore the HF-LCO signal indeed qualifies

as a PES for identifying the second-order linear model of a buck power stage.

C.1.3 Parameter Estimation Conditions

The RLS method assumes both the input and output signals to have zero mean, which

means that the DC component of the d[n] should be removed prior to the identification

process. This can be accomplished by subtracting the steady-state average duty ratio

from input d[n] or by low-pass filtering.


Figure C.1: Estimates of the parameters of a buck converter model when the RLSmethod is used.

C.1.4 System Validation

Preliminary simulation results have been obtained from a matlab/simulink model.

The parameter estimator is built to work in parallel with the LCO PE system. The

identified power stage model parameters of (C.2), a1, a2, b1 and b2 are shown in Fig

C.1. It can be seen that the parameter estimates achieve convergence in about 20

cycles. In Table C.1, the identified parameters are compared to those in a mathemat-

ically derived model [42] and they match very closely.

The estimated error in capacitor ESR zero location is below 20%, which is suffi-

ciently accurate for compensator design.


Table C.1: Parameter Estimation ResultsMathematically derived Estimated parameter values

parameter values after 20 iterationsa1 -1.984 -1.984a2 0.9880 0.9876b1 3.732 4.127b2 -1.474 -1.872

C.2 Practical Issues and Design Considerations

The advantages of the proposed RLS compared to the LCO method of Chapter 3

include more accurate identification, more identifiable parameters, and simple con-

struction of compensator structure and parameters. However, the obvious drawbacks

of it are the heavy computation load and higher requirements on hardware. To

implement the sophisticated RLS adaptation law in (C.6), the total high precision

computations required in one iteration, i.e. in one switching cycle, are about 104

multiplications, 101 additions and 1 division. This high computational demand puts

a significant cost penalty on the system. In addition, the ADC and DPWM used in

the simulation have quantization steps of 1 mV and 5 mV respectively, which is not

easy to realize in a cost-sensitive system such as a low-power SMPS controller.

C.2.1 Other Alternative REM for Simplification

Other REM such as Least-mean-square (LMS), Projection-Algorithm (PA), Stochas-

tic Approximation (SA) etc. may be used instead of RLS for further simplification

purposes. Basically these algorithms all have the same adaptive form as shown below:

θ[n] = θ[n − 1] + P [n]ϕ[n − 1](

y[n] − ϕT [n − 1]θ[n − 1])

(C.7)

Instead of recursively updating P [n] in RLS, different forms of the gain scalar


P [n] in (C.7) is given by the following algorithms:

Least mean squares (LMS): P [n] = γ

Projection algorithm (PA): P [n] = γ

α+ϕT [n−1]ϕ[n−1]Where α ≥ 0, 0 < γ < 2

Stochastic approximation (SA): P [n] = γPnk=1

ϕT [k−1]ϕ[k−1]

Compared to the recursive calculation of P [n] in (C.6), they have much sim-

pler forms and can significantly reduce the computational load required in the RLS

algorithm.

By utilizing as much as possible the prior knowledge of the power stage being

identified, the order of the REM models may be further reduced. For example, with

the proposed LCO PE of Chapter 3, the corner frequency and damping factor of the

power stage can be obtained first, and the order of (C.2) can be reduced from 4 to

2 as two of the parameters are known a priori. Consequently, the matrix calculation

in (C.6) and (C.7) can be drastically simplified. The proper selection of the REM

methods and the validation of model reduction based on prior knowledge will be the

focus of future investigations.

With the advances in techniques of VLSI and materials science, we believe it would

be possible to implement the simplified version of the REM method for mission-critical

systems where cost is less of an issue than performance.

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