Design and Practical Implementation of Advanced ...€¦ · The main goal of this thesis is to...

Design and Practical Implementation of Advanced Reconfigurable Digital Controllers for Low-Power

Multi-Phase DC-DC Converters

by

Zdravko Lukic

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering University of Toronto

© Copyright by Zdravko Lukic 2011

ii

Design and Practical Implementation of Advanced Reconfigurable Digital

Controllers for Low-Power Multi-Phase DC-DC Converters

Zdravko Lukic

Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering University of Toronto

2011

Abstract

The main goal of this thesis is to develop practical digital controller architectures for multi-phase

dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications.

The proposed controllers are suitable for on-chip integration while being capable of providing

advanced features, such as dynamic efficiency optimization, inductor current estimation,

converter component identification, as well as combined dynamic current sharing and fast

transient response.

The first part of this thesis addresses challenges related to the practical implementation of

digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-

use high-frequency digital PWM controller IC that can regulate up to four switching converters

(either interleaved or standalone) is presented. Due to its configurability, low current

consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high

switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc

converters. The applications range from dc-dc converters used in miniature battery-powered

electronic devices consuming a fraction of watt to multi-phase dedicated supplies for

communication systems, consuming hundreds of watts.

iii

A controller for multi-phase converters with unequal current sharing is introduced and an

efficiency optimization method based on logarithmic current sharing is proposed in the second

part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the

number of active converter phases based on the output load current, a significant improvement in

efficiency over the full range of operation is obtained (up to 25%). The stability and inductor

current transition problems related to this mode of operation are also resolved.

At last, two reconfigurable digital controller architectures with multi-parameter estimation are

introduced. Both controllers eliminate the need for external analog current/temperature sensing

circuits by accurately estimating phase inductor currents and identifying critical phase

parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-

linear, average current-mode controller is introduced to provide fast transient response (under 5

μs), small voltage deviation and dynamic current sharing with multi-phase converters. To

equalize the thermal stress of phase components, a conduction loss-based current sharing scheme

is proposed and implemented.

iv

Acknowledgments I wish to thank my supervisor, Professor Aleksandar Prodić, for his great support during my

doctoral studies. Professor Prodić’s dedication, scientific vision, and research passion have

served as inspiration and motivation for me to achieve more and perform better than I could have

ever imagined. I am also thankful for his valuable advices that often extended beyond my thesis

work. Professor Prodić was always able to give me honest constructive feedback that helped me

to improve. His wisdom will stay with me, following me in my future career path.

During my doctoral studies, I had the great honor and pleasure to work with my dear

colleagues and friends: Zhenyu Zhao (‘Frank’), Amir Parayandeh, S M Ahsanuzzaman, Andrija

Stupar, Aleksandar Radić, Jason Weinstein, Massimo Tarulli, and Jurgen Alico. We always

acted as a terrific team and helped each other to succeed. I will always remember those mission-

impossible chip tape-outs with Amir, Aleksandar, and Jason, and conference paper deadlines

with Ahsan and Frank.

I would like to also thank our industry partners Lee Clevelend, Dimitry Goder, and Rob de

Nie for sharing with us their faith and excitement for digitally-controlled SMPS. It was a

remarkable experience to work and learn from these leading industry professionals. I am grateful

for their invaluable support to our group during numerous research projects.

I would like to mention family Milenov from Toronto and family Huerta-Calva from Celaya,

Mexico. They shared the warmth of their home with me. I thank them for their generous help and

for all those unforgettable moments that always kept me positive even through hard times.

I am deeply thankful to my mother Slavica, father Rajko, and sister Milijana for their support

and understanding of my passion for scientific work. The hard work of my parents and

persistence always inspired me to be a better student.

Finally, I would like to dedicate this thesis to my wife Santa Concepción Huerta Olivares. I

thank her for unlimited understanding, profound love, and all the sacrifices she made during our

doctoral studies. I am thrilled about our joined future. Forever and ever!

v

Table of Contents Acknowledgments .......................................................................................................................... iv

Table of Contents ............................................................................................................................. v

List of Tables .................................................................................................................................. ix

List of Figures .................................................................................................................................. x

List of Appendices ........................................................................................................................ xiv

Chapter 1 − Introduction .............................................................................................................. 1

1.1 Design Requirements for Modern Power Management Systems in Low-Power Applications ......................................................................................................................... 1

1.2 Multi-Phase Digital Controller Design Challenges ............................................................. 3

1.3 Thesis Objectives and Organization .................................................................................... 4

References ............................................................................................................................ 5

Chapter 2 – Multi-Use and Fault-Tolerant Digital Controller IC ............................................ 9

2.1 Introduction .......................................................................................................................... 9

2.2 System Operation and Controller Architecture ................................................................. 11

2.3 Multi-Phase Digital Pulse-Width Modulator ..................................................................... 11

2.3.1 Operation with 3 Phases and Number Conversion Logic ...................................... 13

2.3.2 Dual-Biased Delay Cell for Wide-Frequency Range ............................................ 14

2.3.3 Segmented Bias Circuit ......................................................................................... 16

2.3.4 Digital Delay-Lock Logic ...................................................................................... 18

2.4 Programmable Dead-Time Circuit .................................................................................... 19

2.5 ADC Implementation ......................................................................................................... 19

2.6 IC Implementation ............................................................................................................. 20

2.7 Experimental Results ......................................................................................................... 21

2.7.1 Open Loop Tests .................................................................................................... 21

vi

2.7.2 Closed Loop Tests ................................................................................................. 22

2.7.3 Fault-Tolerant Operation ....................................................................................... 23

2.8 Conclusion ......................................................................................................................... 24

References .......................................................................................................................... 24

Chapter 3 − Dynamic Efficiency Optimization for Multi-Phase Converters ......................... 29

3.1 Introduction ........................................................................................................................ 29

3.2 System Architecture ........................................................................................................... 31

3.3 Practical Implementation ................................................................................................... 32

3.3.1 Accurate Current Regulation ................................................................................. 33

3.3.2 Jitter Elimination.................................................................................................... 34

3.4 Transient Operation ........................................................................................................... 35

3.5 Design of Converter Phases ............................................................................................... 38

3.6 Experimental System and Results ..................................................................................... 40

3.6.1 Steady-State Operation .......................................................................................... 40

3.6.2 Transient Operation ............................................................................................... 41

3.6.3 Measured Converter Efficiency ............................................................................. 42

3.7 Conclusion ......................................................................................................................... 43

References .......................................................................................................................... 43

Chapter 4 − Reconfigurable Digital Controllers with Multi-Parameter Estimation ............ 46

4.1 Introduction ........................................................................................................................ 46

4.2 Principle of Current-Estimator Operation ......................................................................... 49

4.3 Practical Implementation of the Current Estimator ........................................................... 51

4.3.1 Filter Architecture and Self-Calibration ................................................................ 52

4.3.1.1 Filter Gain Calibration Procedure ........................................................... 53

4.3.1.2 Filter Time Constant Calibration Procedure ........................................... 55

4.3.1.3 Offset Calibration Procedure ................................................................... 57

vii

4.3.2 Steady-State Current Estimator Architecture ........................................................ 58

4.4 Principle of Temperature Monitoring Operation ............................................................... 59

4.5 Inductor and Output Capacitor Identification .................................................................... 60

4.5.1 Inductor Identification ........................................................................................... 61

4.5.2 Output Capacitor Identification ............................................................................. 61

4.6 Oversampled Non-Linear Average Current-Mode Controller for Multi-Phase Converters .......................................................................................................................... 62

4.6.1 Steady-State Mode ................................................................................................. 62

4.6.2 Multi-Phase Current Estimator Tuning and Phase Identification .......................... 63

4.6.3 Conduction Loss-Based Current Sharing Scheme ................................................. 64

4.6.4 Transient Mode ...................................................................................................... 66

4.6.5 Hardware Optimization and Controller On-Chip Complexity .............................. 69

4.7 Experimental Systems and Results .................................................................................... 70

4.7.1 Filter Gain Calibration ........................................................................................... 71

4.7.2 Filter Time Constant Calibration ........................................................................... 72

4.7.3 Offset Calibration .................................................................................................. 74

4.7.4 Calibrated Operation .............................................................................................. 74

4.7.5 Current Estimation with the Steady-State Current Estimator ................................ 75

4.7.6 Temperature Monitoring and Protection ............................................................... 76

4.7.7 Overload Protection ............................................................................................... 76

4.7.8 Multi-Phase Operation with the Non-Linear Average Current-Mode Controller ............................................................................................................... 77

4.7.9 Accuracy of Current and Temperature Estimation ................................................ 80

4.8 Conclusion ......................................................................................................................... 81

References .......................................................................................................................... 81

viii

Chapter 5 − Conclusions and Future Work .............................................................................. 87

5.1 Thesis Contributions .......................................................................................................... 87

5.2 Future Work ....................................................................................................................... 89

Appendix A − Filter Time Constant Calculation ...................................................................... 90

Appendix B − Quantization Error Effects on Current Estimator Accuracy ......................... 92

ix

List of Tables Table 2.1: Summary of the IC parameters. .................................................................................... 20

Table 3.1: Important parameters of the 4-phase logarithmic buck converter……………………40

Table 4.1: The silicon area and gate count of the multi-phase controller when implemented in

TSMC 0.18-µm CMOS process………………………………………………………………….70

Table B.1: Current estimator relative error versus quantization step of the output

voltage ADC…….……………………….………………………………………………………92

x

List of Figures Figure 1.1: Block diagram of a power management system implemented in notebooks (source:

Texas Instruments). .......................................................................................................................... 1

Figure 2.1: A block diagram of the multi-use and fault-tolerant digital controller IC regulating

operation of a 4 phase interleaved buck converter. ....................................................................... 10

Figure 2.2: A block diagram of the proposed multi-phase digital pulse-width modulator............ 12

Figure 2.3: Phase synchronization: a) start signals during 4-phase interleaved operation; b) 3-

phase interleaved operation. .......................................................................................................... 12

Figure 2.4: The 3-phase MDPWM operation: a) the absolute duty cycle error vs. 8-bit duty ratio

command dc[n]; b) actual duty cycle versus dc[n]. ........................................................................ 14

Figure 2.5: A delay cell with adjustable propagation time tpd: a) conventional current-starved

delay cell b) proposed dual-biased current-starved delay cell. ...................................................... 15

Figure 2.6: Proposed adjustment of the current-starved delay cell current im(t) in the delay line

versus the desired switching frequency fsw. ................................................................................... 16

Figure 2.7: Digitally controlled segmented-bias circuit. ............................................................... 17

Figure 2.8: a) A block diagram of digital delay-locking logic; b) MDPWM delay line signals

when 1, 2, or 4 phases are active. .................................................................................................. 18

Figure 2.9: Programmable dead-time circuit. ................................................................................ 19

Figure 2.10: a) Fabricated chip die of the multi-use digital controller IC b) Current consumption

breakdown. ..................................................................................................................................... 20

Figure 2.11: MDPWM linearity test at 100 kHz – Ch1: output converter voltage (1 V/div). ....... 21

Figure 2.12: MDPWM operation at 10 MHz: a) the duty ratio command is changed between 4

consecutive values b) linearly distributed falling edges of the pulse-width modulated signals (8-

bit resolution at 10 MHz). .............................................................................................................. 22

xi

Figure 2.13: Closed-loop operation of the controller IC: a) four 1-MHz buck converters are

regulated to produce four supply rails between 1.2 and 3.3 V; b) transient response of the

controller when the voltage reference is dynamically changed; c) two-phase interleaved steady-

state operation; d) four-phase interleaved steady-state operation; ................................................ 23

Figure 2.14: Fault-tolerant operation in the closed loop. ............................................................... 24

Figure 3.1: Block diagram of a digitally controlled multi-phase converter with logarithmic

current sharing. .............................................................................................................................. 30

Figure 3.2: Detailed system architecture of the proposed controller with a logarithmic current

sharing. ........................................................................................................................................... 31

Figure 3.3: The output voltage regulation is affected by the jitter (shown in the red circle) of

itot[n]. .............................................................................................................................................. 34

Figure 3.4: Operation of the hysteretic logic – output phase enable signal versus input control

value itot[n]. .................................................................................................................................... 35

Figure 3.5: The effect of finite rising Δ1 and falling current slope Δ2 on itot(t) for a step of the

digital current command itot[n] from 5.4Inom A to 3.6Inom. ............................................................. 36

Figure 3.6: Simulated transient operation of the controller during a heavy-to-light load transient

between 5.4Inom and 3.6Inom. .......................................................................................................... 38

Figure 3.7: a) Simulated efficiency characteristics of the converter phases operating at different

switching frequencies b) Simulated efficiency of the whole system. ........................................... 39

Figure 3.8: Steady-state operation with two different load currents: a) 39 A b) 12 A. ................. 40

Figure 3.9: Transient response for a load step from 21 A to 19 A when the phase enable corrector

and transient current estimator are: a) disabled b) enabled. .......................................................... 41

Figure 3.10: Transient response: a) from 9 A to 38 A; b) from 38 A to 9 A. ............................... 42

Figure 3.11: Measured efficiency characteristics of the converter based on: a) logarithmic current

sharing and uniform current sharing b) logarithmic current sharing and phase shadowing. ......... 43

xii

Figure 4.1: a) A digitally-controlled buck converter with the self-tuning current estimator and

remote temperature monitoring system b) A dual-phase buck converter regulated by the non-

linear multi-phase digital average current-mode controller based on the multi-phase self-tuning

current estimator. ........................................................................................................................... 47

Figure 4.2: Current sensing techniques: a) conventional analog implementation b)

implementation with a self-tuning digital filter. ............................................................................ 49

Figure 4.3: Test current sink circuit used for the filter calibration. ............................................... 51

Figure 4.4: Signals of a filter implemented with an over-sampling ADC. .................................... 52

Figure 4.5: The architecture of the tunable IIR filter used in the current estimator. ..................... 53

Figure 4.6: Filter gain calibration procedure: simulated response of the current estimator during

output load change for two cases (bottom curve) the initial value of RL is twice the actual value

(top curve) after the filter adjustment. ........................................................................................... 54

Figure 4.7: The buck converter (a) and its steady-state dc equivalent circuit Req (b) used for

current estimation. ......................................................................................................................... 55

Figure 4.8: Calibration of the time constant: simulated response of the current estimator during

output load change between 2 A and 2.5A; (bottom) for τf=0.5τL; (top) for τf=τL. ....................... 56

Figure 4.9: Offset in the estimated current isense[n] caused by the operation of the dead-time

circuit and converter. ..................................................................................................................... 57

Figure 4.10: The implementation of the steady-state current estimator. ....................................... 59

Figure 4.11: Change of RL_calibrated due to the ambient temperature for different output load

current conditions. ......................................................................................................................... 60

Figure 4.12: Differential output capacitor and phase inductance identification. ........................... 64

Figure 4.13: Mismatch in phase equivalent resistances generates unequal thermal stress on power

switches. ......................................................................................................................................... 65

xiii

Figure 4.14: Transient mode operation of the non-linear average current-mode controller. ........ 68

Figure 4.15: A time-multiplexed N-phase digital current estimator. ............................................. 70

Figure 4.16: System operation. ..................................................................................................... 71

Figure 4.17: The filter gain (1/RL_calibrated) calibration procedure. ................................................. 72

Figure 4.18: The filter time calibration procedure: a) τf=0.5τL ; b) τf ≈ τL. ................................... 73

Figure 4.19: The filter offset calibration procedure ....................................................................... 74

Figure 4.20: The estimated current during load steps between 1.5 A and 4.5 A. .......................... 75

Figure 4.21: The estimated current with a steady-state current estimator during the load step

between 0.8 A and 5.1 A................................................................................................................ 75

Figure 4.22: Thermal monitoring: a) at 45 °C; b) at 105°C. ......................................................... 76

Figure 4.23: Overload protection implemented with the current estimator................................... 77

Figure 4.24: Current estimator tuning and component identification with the multi-phase

converter. ....................................................................................................................................... 78

Figure 4.25: Transient response of the nonlinear average current-mode controller. ..................... 79

Figure 4.26: The effectivness of the conduction-loss based current sharing scheme. ................... 79

Figure 4.27: a) Estimated inductor current versus the output load current with a 1 A sink step

size b) Relative error of the estimated current for two sink step sizes: 1 A and 2 A..................... 80

Figure 4.28: Estimated temperature versus sensor temperature. ................................................... 81

xiv

List of Appendices Appendix A – Filter Time Constant Calculation………………………………………………...90

Appendix B – Quantization Error Effects on Current Estimator Accuracy……………………..92

1

Chapter 1 Introduction

This thesis presents the design and practical implementation of advanced digital controllers for

multi-phase dc-dc converters utilized in low-power applications such as consumer electronics,

computer servers, and telecommunication equipment. In the following sections, common design

requirements in such applications are examined, multi-phase controller design challenges are

identified, and thesis objectives are formulated accordingly.

1.1 Design Requirements for Modern Power Management

Systems in Low-Power Applications

Figure 1.1 shows a complex power management system found in a typical notebook computer.

The power is delivered to internal devices (i.e. processor, graphic card, and memory) by several

high-efficiency, power processing units (PPU). All PPUs are connected to a shared dc-bus

voltage generated from either a lithium-ion battery source or an ac adapter. The PPUs usually

employ multi-phase switching converters regulated by a dedicated controller circuit.

Figure 1.1: Block diagram of a power management system implemented in notebooks (source: Texas Instruments).

CHAPTER 1. INTRODUCTION 2

The multi-phase converters, shown in Fig. 1.1, utilize between two and four dc-dc converter

phases connected in parallel. The primary role of these phases is to step down the dc-bus voltage,

usually between 0.5 V and 3.3 V, and supply and share the output load current. The number of

parallel converter phases depends on the current consumption ratings of the specific load device.

The common design requirements for the controller circuit and multi-phase converters, used

in power management systems for low-power applications (up to 100 W), are:

• small size of required components due the small form factor of electronic devices,

• minimized component count and reduced cost obtained through on-chip integration of

controller circuitry and regulation of a larger number of converter phases with a single

controller integrated circuit,

• high efficiency of the converter and low power consumption of the controller circuitry

required to reduce amount of generated heat, improve the battery life, and energy

efficiency ratings of the device,

• fast transient response required to minimize the size of energy storage components and

provide reliable operation of supplied devices during load current transients,

• over-current and over-temperature protection of the converter components and load

devices,

• proper current sharing between paralleled converters to avoid unequal stress of converter

components, provide equal aging of all converters, and uniform heat distribution.

Digital controllers [1]-[23] that are capable of satisfying some of these stringent requirements

have emerged just recently. To reduce the size of converter components, they usually operate at

high switching frequencies [2]-[5], while having small power consumption and low hardware

complexity suitable for on-chip integration. More advanced digital controllers are also able to

achieve fast transient response [6]-[9] limited by the converter components, identify single-phase

converter parameters, self-compensate [10]-[13], and optimize the efficiency of single-phase

converters by adjusting the size of switching devices [4], [14] and changing modes of the

controller operation [3], [15].


Previous controller designs were mainly focused on single-phase converters and practical

controller solutions for multi-phase converters are still missing. The multi-phase converters are

currently used in many applications that could greatly benefit with utilization of advanced

control and power management techniques from single-phase converters. However, applying

these techniques to multi-phase converters is not straightforward due mainly to various design

challenges and implementation problems that will be discussed in the following section.

1.2 Multi-Phase Digital Controller Design Challenges

The utilization of the state-of-the-art digital controller ICs [19], [21], [23] for multi-phase and

multiple standalone dc-dc converters, used in the systems similar to the one shown in Fig. 1.1, is

still restricted to high-end products such as computer servers and data communication

equipment. There are two primary reasons for this limitation: 1) high power consumption of

multi-phase digital controllers (several tens of milliwatts), and 2) higher development/production

costs. The power consumption makes the multi-phase digital controllers impractical for

utilization in battery-powered electronic devices, such as cellphones, ebook readers, and

computer tablets. There are also several major technical problems that remain unsolved.

The first problem is related to dynamic efficiency optimization of multi-phase converters used

in power management systems of Fig. 1.1. To improve efficiency, reduce generated heat, and

increase the battery life, digital controllers commonly utilize efficiency optimization schemes

[24]-[26] based on the phase shedding method. However, controller designs with such schemes

are quite challenging because the controlled plant dynamically changes every time the active

number of phases is adjusted. To avoid potential stability problems, conservative controller

designs that sacrifice transient response of the converter for improved efficiency are utilized in

practice.

The second major problem is associated with the current sensing for single-phase and multi-

phase converters and temperature monitoring. The current information is essential for over-

current protection [27], efficiency optimization [22], [26], [28], [29] and current sharing

purposes [30]-[36]. The converter inductor currents are still measured using analog circuitry

[37]. Implementation of external analog current sensing circuits and their integration with

integrated digital controllers is usually costly and difficult due to the requirement for multiple


analog-to-digital converters (ADCs).

The third problem is related to parameter estimation of multi-phase converters. Existing

identification methods [10]-[13] are designed to determine inductor-capacitor products of single-

phase converters. However, they cannot be directly applied to multi-phase converters where

multiple inductor branches are connected to a common output capacitor. If phase components

(i.e. phase inductances and output capacitor) could be identified separately, their values could be

used to improve the transient response of the converter.

Combined fast transient response and dynamic current sharing is also an important design

issue with multi-phase converters. Recent multi-phase digital controllers [38]-[40] provide

proper sharing of the load current between multiple converter phases but they suffer from the

limited controller bandwidth and slow converter response under large load steps.

1.3 Thesis Objectives and Organization In this thesis solutions for the above listed problems are presented. Mainly, new concepts are

introduced and tested on single phase systems, then adapted for multi-phase systems. In other

words, even designs for single-phase converters are implemented with the final goal of multi-

phase application in mind. The thesis goals and content of remaining chapters are briefly

summarized below.

A low-cost flexible multi-phase digital controller IC that can be easily configured and

employed in various applications will be developed in the first part of this thesis. The IC will

operate between 100 kHz and 10 MHz and it will exhibit low power consumption for use in

portable applications. The IC will be utilized for interleaved converters having between 2 and 4

converter phases and/or it will simultaneously regulate up to 4 standalone converters providing

different output voltages. All major controller parameters (i.e. switching frequency, number of

active phases, etc.) of the IC will be externally programmable in order to achieve optimum

performance for a specific application. The design, implementation and experimental operation

of the system will be presented in Chapter 2.

The problem of dynamic efficiency optimization for multi-phase converters will be addressed

and resolved in Chapter 3. This chapter will present a current-program mode digital controller

architecture and a multiphase dc-dc converter with non-uniform current sharing that dynamically


optimize converter efficiency over the full load range of operation.

Chapter 4 will introduce advanced reconfigurable digital controllers with multi-parameter

estimation for single-phase and multi-phase converters. They can accurately estimate inductor

currents, perform identification of key converter parameters, and provide remote temperature

monitoring of power switches. In the case of the multi-phase converters, the proposed sensorless

non-linear average current-mode controller will utilize the identified power stage parameters and

estimated inductor currents to provide fast transient response, while maintaining dynamic current

sharing and equalized thermal stress between converter phases.

Chapter 5 concludes this thesis and suggests potential new research directions with author’s

anticipation that presented technical solutions in this thesis will fuel development of digitally-

controlled multi-phase converters that are inexpensive, energy efficient, and environmentally

friendly.

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[26] J.A. Abu Qahoug, L. Huang, “Highly efficient VRM for wide load range with dynamic

non-uniform current sharing,” in Proc. IEEE Applied Power Electronics Conf., 2007, pp. 543 - 549.

[27] H. Peng, D. Maksimović, “Overload protection in digitally controlled DC-DC converters,"

in Proc. IEEE Power Electronics Specialist Conf., Jun. 2006, pp. 1 – 6. [28] Z. Lukić, Zhenyu Zhao, A. Prodić, D. Goder, “Digital controller for multi-phase DC-DC

converters with logarithmic current sharing,” in Proc. IEEE Power Electronics Specialist Conf., 2007, pp. 119 – 123.

[29] A. Parayandeh, Chu Pang, A. Prodić, “Digitally controlled low-power DC-DC converter

with instantaneous on-line efficiency optimization,” in Proc. IEEE Applied Power Electronics Conf., 2009, pp. 159- 163.

[30] B. Tomescu, H.F. Vanlandingham, “Improved large-signal performance of paralleled DC-DC converters current sharing,” IEEE Trans. Power Electron., vol. 14, pp. 573 – 577, May 1999.

[31] Peng Li, B. Lehman, “A design method for paralleling current mode controlled DC-DC converters,” IEEE Trans. Power Electron., vol. 19, pp. 748 – 756, May 2004.

[32] J. Abu-Qahouq, Mao Hong, I. Batarseh, “Multiphase voltage-mode hysteretic controlled DC-DC converter with novel current sharing,” IEEE Trans. Power Electron., vol. 19, pp. 1397 – 1407, Nov 2004.

[33] Jaber A. Abu Qahouq, Lilly Huang, Doug Huard and Allan Hallberg, “Novel current sharing schemes for multiphase converters with digital controller implementation,” in Proc. IEEE Applied Power Electronics Conf., Feb. 2007, pp. 148 – 156.


[34] Y. Zhang, R. Zane, D. Maksimović, “Current sharing in digitally controlled masterless multi-phase DC-DC Converters,” in Proc. IEEE Power Electronics Specialist Conf., Jun. 2005, pp. 2722 – 2728.

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9

Chapter 2 Multi-Use and Fault-Tolerant Digital Controller IC

2.1 Introduction In multi-phase dc-dc converters, potential advantages of digital controllers over traditional

analog solutions are evident. Digital systems allow implementation of complex power

management techniques and advanced control laws [1]-[13]. It has also been shown that digital

controllers are able to closely match multiple pulse-width modulated signals [14], which is

important in implementing accurate current sharing [14,15].

Despite these advantages, there has been limited utilization of digital controllers in multi-

phase systems, largely due to unsolved practical implementation problems. Compared to analog

solutions [16,17], most existing digital architectures require significantly larger silicon area and

have a relatively high power consumption (usually in the range of tens of mW/MHz) [18,19],

both of which are making them impractical for on-chip implementation required in targeted high-

volume systems. High power consumption presents a very serious limitation in upcoming

converters, which are expected to switch much faster than the existing converters, in order to

reduce the size of energy storage components.

The main goal of this chapter is to introduce a versatile multi-phase digital controller IC

architecture, shown in Fig. 2.1, which has low power consumption and takes small silicon area,

comparable to that of analog systems. The new IC also exploits flexibility of digital

implementation. It can be set to operate as a controller for interleaved converters having 2 to 4

phases and/or simultaneously regulate up to 4 standalone converters providing different output

voltages. Furthermore, in multi-phase mode, this architecture features fault-tolerant operation

providing uninterrupted output voltage in the case of a failure in one of the phases.

The key block of the new IC is a reconfigurable multi-phase digital pulse-width modulator

(MDPWM). The programmable parameters are switching frequency (between 100 kHz and 10

MHz), phase shifts between PWM signals, as well as dead-times.

CHAPTER 2. MULTI-USE AND FAULT-TOLERANT DIGITAL CONTROLLER IC 10

In this IC, compensator coefficients and voltage references can be also dynamically adjusted

through a digital communication interface based on either a parallel or serial I2C [20]

communication protocol.

All of the features allow the use of this flexible controller in various applications, including

modern voltage regulator modules (VRMs) [21]-[23], multiple output converters for

communication devices and television sets as well as in portable electronics. In interleaved mode

the controller tolerates failures in up to three phases and it automatically switches to operation

with reduced numbers of phase (for example, from 4 to 3). Potentially, the dynamic reduction of

active converter phases can be exploited to improve efficiency at light and medium loads [24]

when up to three phases can be disabled. Although very valuable, these features have not been

presented in other MDPWM architectures [14], [25], [26], mostly due to the lack of solutions for

the operation with an odd number of phases and overly large hardware complexity. In the

following section, the operation of the multi-use controller IC is explained.

Figure 2.1: A block diagram of the multi-use and fault-tolerant digital controller IC regulating operation of a 4 phase interleaved buck converter.


2.2 System Operation and Controller Architecture

Figure 2.1 shows the multi-use controller regulating operation of a 4-phase interleaved buck

converter. The controller consists of four analog-to-digital converters (ADCs) [27], four

programmable look-up table PID compensators [28,29], MDPWM, dead-time circuits, and

master management unit (MMU). The number of active ADCs and PID compensators is

regulated by the MMU, through external mode control and over-current protection signals (mode

and OCP). In interleaved mode, only one ADC and a compensator are used to regulate the

operation of all the phases. When the regulation of multiple outputs is required, a larger number

of these blocks are activated. The MMU generates clock signals for ADCs and PID

compensators, adjusts phase shifts of control signals, and shuts down critical phases if the OCP

signal, activated by a separate measurement circuits, is received. Based on the difference

between the output voltage references Vref, set by a sigma-delta digital-to-analog converter [27],

the ADCs produce error signals e[n] for PID compensators. The PID calculates duty ratio

commands for MDPWM. Depending on the mode of operation, the MDPWM creates up to 4

pulse-width modulated signals, whose duty ratios can be independently adjusted.

2.3 Multi-Phase Digital Pulse-Width Modulator

The architecture of the 4-phase MDPWM, shown in Fig. 2.2, is based on a modification of a

hybrid DPWM [29,30], in which a low-resolution counter and delay line are combined to create

a high-resolution pulse-width modulated signal. In this case, a programmable counter and a

synchronization block are introduced, both of which are shared by all phases to minimize

hardware complexity and improve matching between the phases.

Each phase contains a first-order Σ-∆ modulator [31]-[35], a programmable delay line, a

segmented delay matching circuit and a number conversion block. The system uses an external

clock signal whose frequency never exceeds nine times the switching frequency making

MDPWM power consumption relatively low. At the beginning of each switching cycle, in each

of the phases, a set pulse for the SR latch is created and the rising edge of the corresponding

dpwm signal cpmwi(t), where i=1,…,4, is created. The on-time duration is varied using the counter

and delay lines, which reset the latch. The core steps (3 most significant bits - MSBs) of the


Figure 2.2: A block diagram of the proposed multi-phase digital pulse-width modulator.

Figure 2.3: Phase synchronization: a) start signals during 4-phase interleaved operation; b) 3-phase interleaved operation.

desired 11-bit duty ratio value di[n] (i =1,..,4) are set by the counter, the fine adjustments (middle

5 bits) are performed through delay lines, and even finer ones (3 least significant bits - LSBs) are

obtained through Σ-∆ modulation. The mode of MDPWM operation depends on phase enable

and phase angle signals, which select the combination of active phases and the angles between

them, respectively. When the number of selected phases is 1, 2 or 4, the counter output changes

from 0 to 7. While operating with 3 phases, it counts from 0 to 8. Based on the phase angle


signal, the synchronization block creates set pulses spi that set SR latches. As an example, Fig.

2.3 illustrates set and counter’s output signals during interleaved operation with 4 and 3 phases

when phase shifts of 90° and 120° respectively are required.

2.3.1 Operation with 3 Phases and Number Conversion Logic

When operating in the single-phase mode or with an even number of phases, the creation of the

duty ratio value proportional to the 8-bit control input dc[n] (see Fig. 2.2) is quite simple. The

counter output goes through eight cycles and its ramping output r[n] is compared with the 3-

MSBs of dc[n] increased by phase angle value. When the two compared numbers are equal, pulse

δ(t) for the delay line is created. The propagation time of the pulse through the 32-cell-long delay

line is defined with the 5-MSBs of dc[n]. In the 3-phase mode, the situation is more complex.

Now, in each switching cycle the counter goes through 9 steps, which combined with 32 delays,

result in 288 different output duty ratio values. This number is higher than the number of

possible values for dc[n], creating a problem of assigning a duty ratio value to appropriate input.

If wrongly interpreted, the input values can cause non-linear or even non-monotonic input-to-

output DPWM characteristic and consequent closed-loop stability problems.

In order to generate a monotonic characteristic, for each input value dc[n], a portion of the

duty ratio increment is created by the counter and delay line. To determine this mapping, a

minimum-error criterion is used. Here, the difference between the desired increment and sum of

increments of the delay line ∆Dcn = Ncn[n]/9 and the counter ∆Ddl = Ndl[n]/256 is compared.

Where Ncn[n] is a 4-bit value controlling the number of counter steps before the delay line is

triggered and Ndl[n] is a 5-bit value defining the number of delay cells as shown in Fig. 2.2. More

precisely, we look for the minimum of the following function representing the absolute error in

dc[n] representation:

[ ] [ ]

+−=∆

2569256][ nNnNnd dlcnc

d . (2.1)

The solution of this equation gives a set of 256 values of Ncn[n] and Ndl[n] that result in the error

distribution shown in Fig. 2.4.a) limited to less than ±0.5 LSB. As a result, monotonic operation

is obtained as illustrated in Fig. 2.4.b). The values of Ncn[n] and Ndl[n] are stored in two look-up


tables used for generating proper increment portions during 3-phase operation.

Figure 2.4: The 3-phase MDPWM operation: a) the absolute duty cycle error vs. 8-bit duty ratio command dc[n]; b) actual duty cycle versus dc[n].

2.3.2 Dual-Biased Delay Cell for Wide-Frequency Range

One of the main challenges of DPWM architectures involving a delay line and a counter [36,37]

or segmented delay lines [38,39] is linearity.

When good matching between the counter time increment and the total propagation time of all

delay cells is not achieved, a non-monotonic characteristic can occur [36]. As a result, at certain

duty-ratio operating points, local stability problems [40] occur. In practice this undesirable

behavior is caused by fabrication defects and temperature variations. The delay-locked loop

(DLL) based structures are utilized [25], [37], [39], [41] to adjust the delay cells and allow linear

operation at programmable switching frequencies [41].

Except for the segmented delay-line DPWM [41], existing DLL-based DPWM

implementations are not designed for operation over a wide frequency range of the multi-use

controller from Fig. 2.1. To achieve the 8-bit resolution of the core DPWM (without sigma-delta)

in the frequency range between 100 kHz and 10 MHz, the delay cell propagation time tpd needs

to be varied significantly.


To change the propagation time, current-starved delay cells [42], from Fig. 2.5.a) are often

employed. Their propagation time tpd is regulated by a programmable bias current source Ibias.

The finite steps ΔIbias of the current source are then further reduced through the mirroring stage

1/K1 (K1 >> 100), to obtain very precise control over tpd. The main problem of this circuit is that

it requires a large biasing current (~ 1 mA) to reduce tpd from 39 ns to 390 ps, corresponding

switching frequencies of 100 kHz to 10 MHz, respectively. Such a high bias current value is not

acceptable for low-power applications.

Figure 2.5: A delay cell with adjustable propagation time tpd: a) conventional current-starved delay cell b) proposed dual-biased current-starved delay cell.

To solve for this problem, a power efficient dual-bias delay cell is developed. The proposed

circuit is shown in Fig. 2.5.b). It consists of two CMOS inverters and a dual current mirroring

input stage that discharges the output equivalent capacitance seen at the node A. The propagation

time of a signal entering the cell is inversely proportional to the instantaneous current of the

mirroring stage im(t). This current is formed as a scaled sum of currents produced by two current

sources Icoarse, Ifine and during the delay cell transition period its value is

( )21 K

IKI

ti coarsefinem += , (2.2)

where current ratio K1 is larger than K2. In this way, the need for a single current source having a

wide current range and high power consumption, at high switching frequencies, is eliminated as

shown in Fig. 2.6. Still, a relatively high current im(t) ensuring short propagation time of delay


cells can be achieved by Icoarse. When long propagation times are required, Icoarse can be reduced

and a precise delay regulation can be achieved through Ifine adjustments. It should be noted that,

in this application, im(t) has a relatively small influence on the delay line’s power consumption.

This is because im(t) occurs only during short state transients, and in the targeted range of

switching frequencies its average value is small. This structure also provides more accurate

regulation of delay times. For large delays, conventional current starved delay cells have poor

regulation of delay times, due to inaccurate adjustment of low bias currents. In this case, this

problem is minimized.

Figure 2.6: Proposed adjustment of the current-starved delay cell current im(t) in the delay line versus the desired switching frequency fsw.

2.3.3 Segmented Bias Circuit

Current sources Icoarse and Ifine , introduced in Fig. 2.5, are designed to be digitally programmable

with fixed current increments ΔIfine and ΔIcoarse. The implementation of the bias circuit is shown

in Fig. 2.7. It can be integrated in deep sub-micron CMOS technologies, due to a requirement for

only two stacked transistors between supply rails. The current source Ifine, consists of 5 binary-

sized PMOS transistors and 20 equally-sized PMOS transistors. This arrangement in the

transistor sizing simplifies the digital logic that controls their operation while providing very

accurate and monotonic change of im(t) provided by Ifine. The precise adjustment of Ifine and tpd is

then achieved by turning on/off the binary-sized PMOS transistors using a 5-bit binary pmos

select input. Even finer current increments are obtained by using the 20-bit point pmos select


Figure 2.7: Digitally controlled segmented-bias circuit.

input tied to the equally-sized transistor. The coarse change of tpd is achieved by adjusting the 8-

bit range pmos select input. The transistors controlled with this input are sized in a thermometer

code fashion. This was implemented in order to guarantee monotonic behavior of tpd during

coarse bias current change. Additionally, to generate a smooth change of tpd when changing

Icoarse, the current ratio K2 of the right-side mirror has to be sized according to:

21

max

KI

KI coarsefine ∆

= . (2.3)

Due to the smaller current mirror ratio K2, the maximum value of Icoarse required to obtain the

smallest tpd (390 ps) is an order of magnitude smaller than that of the conventional cell, shown in

Fig. 2.5.a. The propagation delay tpd can be also accurately controlled. In this case, over the

proposed switching frequency range, the number of frequencies where propagation delay tpd is

accurately adjusted is 5120 (25 x 20 x 8). The effective frequency resolution of the delay-lock

loop is less than 2 kHz. If further improvement is desired, one can change the number and sizing

of biasing transistors and adjust the current mirror ratios K1 and K2.


2.3.4 Digital Delay-Lock Logic

The block diagram of the digital delay-lock logic [37], [41] that adjusts the segmented bias

circuit based on the input external clock is shown in Fig. 2.8.a). During each switching period,

the reset pulse rpi(t) from the MDPWM is injected into the delay line. Depending on the delay

cell bias current im(t), the rising edge of rpi(t) travels through the delay line with a certain

propagation speed. If im(t) is set properly, when the falling edge of rpi(t) occurs 1/8∙Tsw after the

pulse was created, the rising edge of rpi(t) should reach the last delay line node n32. This situation

is illustrated in Fig. 2.8.b). Similarly, when the MDPWM operates in the three-phase mode, the

output of the last small cell (0.44∙tpd) at node n28a exhibits the rising edge 1/9∙Tsw after the pulse

was generated. However, if im(t) is larger than required, the pulse propagates faster through the

delay line. Consequently, when the falling edge of rpi(t) occurs, all delay cell outputs are set high

including the last two nodes n31 and n32. Similarly, if the bias current is lower, the pulse

propagates slower than desired and logic levels at both node n31 and n32 remain low. Therefore,

by observing only n31 and n32 during the falling edge of rpi(t), an appropriate decision about

increasing/decreasing the bias current can be made. Logic levels at n31 and n32 (1, 2, or 4 phases

are active) or n28 and n28a (3 phases are active) are sampled each switching cycle at the falling

edge of rp(t). Depending on the mode of operation (3-phase/4-phase), the sampled levels are fed

to a current adjust finite-state machine (FSM) in Fig. 2.8.a). The FSM then decides the

adjustment of the bias current for delay cells. For instance, if the total propagation time for the

delay line is not matched initially, the sampled logic levels at n31 and n32 are “00” ( rpi(t)

Figure 2.8: a) A block diagram of digital delay-locking logic; b) MDPWM delay line signals when 1, 2, or 4 phases are active.


propagates too slow) or “10” (to be determined). The bias current is then gradually increased by

the FSM until “11” state (rpi(t) propagates too fast) is detected. The current level is then reduced

until state “10” is reached. In this way, the rising edge of the pulse at node n32 and falling edge of

rpi(t) are tuned as close as possible as shown in Fig. 2.8.b). The bias current is then considered

adjusted and further corrections are not performed unless state “00” or “11” are sensed again. In

the opposite case, if the initial bias current is too large and state “11” is detected, the bias current

is decreased until pulse slows down and state “10” is sampled for the first time. At that point, the

bias current for the delay line is “frozen” and delay line is locked.

2.4 Programmable Dead-Time Circuit A simplified block diagram of the programmable dead-time circuit generating non-overlapping

control signals c(t) and c’(t) is shown in Fig. 2.9. The non-overlapping clock generator circuit

[35] is modified to include two delay lines and two 16/1 multiplexers for dead time value

adjustment. Two multiplexers MUX 16/1 allow selection of the desired falling and rising dead

time values by adjusting the effective length of the delay lines. The maximum dead-time value

that can be obtained with 16 delay cells is 6.25% of Tsw. The dead-time increment is equal to

0.39% of the switching period.

Figure 2.9: Programmable dead-time circuit.

2.5 ADC Implementation The ADCs from Fig. 2.1 are implemented, as described in [27]. This low-power differential

delay-line ADC architecture is suitable for fabrication in deep sub-micron CMOS IC

technologies. To provide tight output voltage regulation (error ≤ 1%) of the digital loop, the

ADC quantization step scales with the analog voltage reference. Each of four analog ADC


references can be dynamically adjusted with four 10-bit Σ-Δ DACs interfaced with the MMU as

shown in Fig. 2.1. This allows the use of this controller in modern power management systems

with dynamic or adaptive voltage scaling [43].

2.6 IC Implementation

The digital controller of Fig. 2.1, was fabricated in TSMC 0.18-µm CMOS process. A

photograph of the fabricated chip is shown in Fig. 2.10.a) and its important parameters are

summarized in Table 2.1. The four-phase controller blocks occupy 1.72 mm2 of the silicon area,

which is comparable or even smaller than the area required for implementation of analog

solutions [44]. The utilized area can be further reduced by using custom-designed memory

blocks for storing controller parameters instead of flip-flop arrays and by time-sharing digital

hardware blocks (PID compensators, delay-lock loops, etc.) between phases. The measured chip

current consumption is 3.6 mA at the maximum switching frequency of 10 MHz when all 4

Table 2.1: Summary of the IC parameters.

Technology TSMC 0.18 µm CMOS Supply voltage 1.8 V / 3.3 V Switching frequency 100 kHz – 10 MHz No. of phases 4 Max. current consumption 3.6 mA @ 10 MHz Normalized current consumption 90.25 µA/MHz/per phase Controller silicon area 1.7 mm2

Figure 2.10: a) Fabricated chip die of the multi-use digital controller IC; b) Current consumption breakdown.


phases are active and running separately. The current consumption breakdown is also presented

in Fig. 2.10.b). The normalized current consumption figure of 90.25 µA/MHz for each phase is

equivalent to the state-of-art analog solutions [16,17] and much smaller than commercial digital

controllers [18,19], that consume up to 50 mA when regulating four converter phases switching

at 2 MHz. Consequently, this controller could be used in portable applications [41] as well.

2.7 Experimental Results

To verify the operation of the controller IC, open-loop and closed-loop tests with four buck

converters are performed. The buck converter phases used for the closed loop tests are designed

to operate at the nominal switching frequency of 1 MHz and supply up to 5 A of the load current.

All desired controller parameters and configuration settings for different tests are loaded to the

on-chip memory via the built-in communication interface.

2.7.1 Open Loop Tests

To test the monotonic behavior and check linearity of the MDPWM the pulse-width modulated

output is first connected to a buck converter switching at 100 kHz. The MDPWM is set in the

three phase mode. The input 11-bit duty ratio command d[n] was gradually changed between

10% and 90% of its maximum value. The waveform shown in Fig. 2.11 demonstrates that the

output voltage changes linearly. Large non-monotonic regions caused by the MDPWM cannot be

observed due to the automatic delay adjustment performed by the digital delay-lock loop.

Figure 2.11: MDPWM linearity test at 100 kHz – Ch1: output converter voltage (1 V/div).


In the next step, the external clock frequency is increased in order to create a 10-MHz

switching signals. The input duty ratio command is now varied between four consecutive values

to produce pulse-width modulated signals shown in Fig. 2.12.a). From the zoomed part of the

waveform, shown in Fig. 2.12.b), it can be observed that the propagation time of delay cells is

properly adjusted to 390 ps as required for 8-bit resolution at 10 MHz. The measured current

consumption of one MDPWM phase operating at 10 MHz is 260 µA.

Figure 2.12: MDPWM operation at 10 MHz: a) the duty ratio command is changed between 4 consecutive values b) linearly distributed falling edges of the pulse-width modulated signals (8-bit resolution at 10 MHz).

2.7.2 Closed Loop Tests

The closed loop operation of the controller IC is tested for both multiple-output and interleaved

modes of operation. In the multiple-output mode, 4 buck converters operating at 1 MHz are used

to provide the output voltages of 1.2 V, 1.8 V, 2.5 V, and 3.3 V. The desired voltage references

are set digitally. Fig. 2.13.a) shows the captured waveforms. All output voltages are regulated/ at

their designated values. Fig. 2.13.b) shows the response of the controller when a phase voltage

reference is now dynamically modified through the communication interface. Once the data is

received by the controller, the MMU quickly updates the reference value fed to the dedicated Σ-

Δ DAC. As a result, the ADC reference voltage is increased from 1.5 V to 2.7 V and the

controller regulates the converter output voltage to reach the new steady state within 30 μs,

which is sufficiently fast for a most power saving techniques based on dynamic voltage

adjustment [43], [45], [46]. Finally, the interleaved mode of operation is first verified with two

phases enabled as shown in Fig. 2.13.c). The controller IC recognizes that only two phases are

active, and it adjusts phase shifts between control signals to Tsw/2 to reduce the output voltage


ripple. In the next step, two additional phases are enabled and phase shift is now again updated to

Tsw/4 by the MMU, as demonstrated in Fig. 2.13.d).

Figure 2.13: Closed-loop operation of the controller IC: a) four 1-MHz buck converters are regulated to produce four supply rails between 1.2 and 3.3 V; b) transient response of the controller when the voltage reference is dynamically changed; c) two-phase interleaved steady-state operation; d) four-phase interleaved steady-state operation;

2.7.3 Fault-Tolerant Operation

The fault tolerant operation is tested by intentionally generating the over-current protection

signal (OCP) (from Fig. 2.1) in one of the phases as shown in Fig. 2.14. Once the OCP is

detected, the faulty phase is turned off by the MMU. The MMU then observes the remaining

number of phases and starts updating phase angles for all active phases until all control signals

are shifted by 1/3 of the switching period. Similarly, if one more phase is turned off, the MMU

will adjust the phase shift to one half of the switching period. The automatic phase shift

reconfiguration can be also utilized for optimizing the multi-phase converter efficiency when the


number of enabled phases varies with the load current. In other words, at light load currents up to

three phases can be turned off [24] to reduce switching losses and improve the efficiency.

Figure 2.14: Fault-tolerant operation in the closed loop – Ch1: output converter voltage vout(t) at 3.3 V (500 mV/div); Ch2: Output converter voltage vout(t) – AC component (50 mV/div); D1-D4: MDPWM control signals switching at 1 MHz; D5 – OCP signal; Time scale is 2 μs/div.

2.8 Conclusion In this chapter a flexible multi-phase/multi-stage digital controller IC having low power

consumption and occupying a small silicon area is presented. The controller can be used in

various applications including portable electronic devices. To achieve these characteristics, novel

architecture of a multi-phase DPWM is developed and combined with a newly designed current

starved delay cell. The performances of the controller IC are experimentally verified on several

experimental setups, including multiple-output and interleaved dc-dc converters.

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29

Chapter 3 Dynamic Efficiency Optimization for Multi-Phase Converters

3.1 Introduction The efficiency of a typical multi-phase dc-dc switch-mode power supply (SMPS) used in

telecommunication devices, consumer electronics, and personal computers depends on its load

[1]-[3]. Even though the supplied devices usually do not take constant power at all times, the

converters are often designed to be most efficient at a certain load (usually maximum). As a

result the efficiency at light and medium loads is degraded. In modern systems this causes

significant losses, since the devices operate in suboptimal modes over large time intervals.

In multi-phase systems, utilized for high-current applications [4], the load current is usually

shared equally among several converter stages [5]-[8], to reduce the inductor current ripple [9],

stress on components, and improve dynamic response. To optimize efficiency of multiphase

converters over the full load range, several approaches have been proposed. The phase

shadowing techniques [10] improve the efficiency of the converter with uniform current sharing

by switching off phases at lighter loads. This technique provides a significant efficiency

improvement over the full-range of operation but requires a relatively large number of phases to

achieve a flat efficiency curve. The method based on non-uniform current sharing [11] utilizes

multiple power stages with different current ratings. To improve the efficiency in this

implementation, the phases are switched on and off in a predermined fashion similar to the phase

shadowing method while the load current is distributed among converter phases by a current

sharing loop according to their current ratings. This method results in a smaller number of phases

but the shape of the efficiency curve is degraded.

However, in both of the abovementioned methods the power stages are presented but the

controller implementation issues have not been addressed. In particular, controller stability

problems [12] during phase on/off transients, which will be addressed soon, cannot be solved in

a simple manner. Hence, the authors demonstrate steady-state operation of the presented

architectures only and suggest possible controller implementations.

CHAPTER 3. DYNAMIC EFFICIENCY OPTIMIZATION FOR MULTI-PHASE CONVERTERS 30

The main goals of this chapter are to address and solve the problems of practical controller

implementation in multi-phase converters and to show a new system that results in a small

number of phases having both a flat and optimized efficiency curve. To achieve these

characteristics the system, shown in Fig. 3.1, utilizes two key elements: a multi-phase digital

current program-mode based controller, which does not require analog-to-digital converters for

the inductor current measurements, and a power stage with logarithmic current sharing. The

system employs N parallel converters operating as binary-weighted constant current sources

based on a concept similar to the method previously used for designing high-frequency resonant

converters [13]. Each of the N phases is optimized by selecting the size of semiconductor

switches, the inductor value, and the switching frequency such that the maximum efficiency at its

designated current Ii = 2i−1 ∙Inom, is achieved, where i = 1, 2,…, N. The instantaneous number of

phases operating at any point of time is dynamically regulated by the digital current program

mode controller (DCPM). Depending on the load current (Iload) requirements, the controller

generates a digital control variable itot[n] that enables or disables the phases, such that Iload = ΣIi.

The state of each phase is controlled through phase enable signals s1, s2,…, sN. In this

implementation, s1 corresponds to the least significant bit (LSB) of itot[n] and sN, controlling the

current of 2N−1∙Inom, is the most significant bit (MSB). Since each of the converters individually

operates at the most efficient point, in this way, the optimal efficiency over the full range of

Figure 3.1: Block diagram of a digitally controlled multi-phase converter with logarithmic current sharing.


operation is dynamically achieved. Also, as discussed in the following section, the hardware

requirements for a relatively complex current loop are minimized.

3.2 System Architecture

Fig. 3.2 shows a 4-phase implementation of the proposed system. Its controller has a digital

voltage loop containing an analog-to-digital converter (ADC) for the output voltage error e[n]

measurement and a PI compensator producing the signal itot[n], controlling the total current of

the converter. The sampling of the output voltage and the update of itot[n] is performed at the

frequency equal to the rate of the fastest-switching converter phase.

Compared to the traditional implementation of a fully-digital current programming controllers

(DCPM) [14]-[16], which requires multiple ADCs for the phase current measurements, the

system of Fig. 3.2 is much simpler. It eliminates the need for a large number of fast ADCs and

Figure 3.2: Detailed system architecture of the proposed controller with a logarithmic current sharing.


instead, as shown in Fig. 3.2, uses a set of comparators with thresholds vnom, 2vnom, and 4vnom that

are proportional to the binary weighted currents. As a result, the peak current-mode control [17]

in all phases is achieved. It should be noted that the elimination of a large number of ADCs

greatly simplifies the controller implementation and complexity. On the other hand, the

comparators of Fig. 3.2 can be fairly simple. They need to be fast but not necessarily very

accurate. Any offset in the comparator threshold is automatically compensated by the voltage

loop and in most cases has only a negligible effect on the phase efficiency.

To provide accurate current regulation and eliminate the stability problem related to the phase

toggling, which will be addressed in the following sections, a digital-to-analog converter (DAC),

an additional low-current phase, and a hysteretic logic block followed by a transient current

estimator and a phase enable corrector blocks are added. Similar to conventional

implementations [17], the controller also has current amplifiers and an SR latch, whose operation

is either enabled or disabled with the phase enable signal si.

3.3 Practical Implementation

One of the advantages of the new controller architecture over the voltage-mode controllers

[10,11] is the simplicity of the compensator implementation. This can be explained by looking at

the control-to-output transfer function of voltage-mode controlled N-phase buck converter [17]

( )( )

20

2

00

1

1)(

ωω

ωs

Qs

s

Vsdsv

sG esrin

outvd

++

+⋅== , (3.1)

where the corner frequency ω0 is

CNL⋅

=1

0ω . (3.2)

It can be seen that the corner frequency ω0 depends on phase inductance L, total output

capacitance C, as well as on the number of active phases N. This dependence on the number of

active phases dynamically changes “transfer function” and creates a serious control problem in


voltage mode controlled converters using efficiency optimization schemes [10,11] based on the

phase shadowing method. To provide stability under all operating conditions, a slow

compensator is often used, meaning that the dynamic performance of the system is sacrificed to

improve power processing efficiency.

The current-mode controller of Fig. 3.2 does not suffer from the phase-dependent transfer

function variation problem. In this system the phases behave as control-signal dependent current

sources [17], [21] connected to the parallel connection of the load resistance R and the output

capacitance C. The small-signal first-order transfer function Gvic(s) is shown [17] to be:

( )

p

esr

c

outvic s

s

Rsisv

sG

ω

ω

+

+⋅==

1

1

)()( , (3.3)

where the pole frequency ωp is inversely proportional to the RC product:

RCp1

=ω . (3.4)

3.3.1 Accurate Current Regulation

The main problem of the architecture shown in Fig. 3.1 is the accuracy of current regulation.

Since the current can be changed in discrete steps only, related limit cycling problems affecting

system stability and output current/voltage regulation can occur [22]. To eliminate the

quantization effects without a significant increase in the number of phases, the originally

proposed structure is modified as shown in Fig. 3.2. A phase with variable current that can be

continuously changed from 0 to 1.5Inom is added and, for the 4-phase implementation, the

remaining three phases are scaled as Inom, 2Inom, and 4Inom. As described in the following section,

the rating of the variable phase is selected such that jittering of the system is eliminated.

To achieve the desired current regulation, in this case with an 11-bit resolution, the 3 MSBs of

the control signal are used as phase enable/disable variables and the 9 LSBs are fed into a single-

bit Σ-∆ DAC [23], which sets the reference for the phase with variable current. It should be noted

that the implementation of the DAC is significantly simpler than that of an ADC [23,24] and its


introduction has a relatively small effect on the system complexity. Also, since the power rating

of the variable-current phase is small, its wide-range operation does not significantly affect the

system efficiency.

3.3.2 Jitter Elimination

An additional difficulty in implementing the proposed controller is jittering (chattering) of the

control signal itot[n]. It occurs when the PI controller frequently changes its output between two

approximate values resulting in a phase reconfiguration. For example, assume that a light load

change requires the total inductor current, i.e. current reference itot[n], to change between

3.99Inom and 4.01Inom. Initially, to provide a current of 3.99Inom, two constant current phases are

switched on to produce Inom, 2Inom and the variable current phase produces 0.99Inom. To increase

the current to 4.01Inom, the 4Inom can be turned on and the remaining part, of 0.01Inom, can be

provided by the variable current phase. However, such an operation is undesirable since it

requires inductor currents of all constant-current phases to change from rated values to zero or in

opposite direction. This abrupt change of all currents can negatively affect the output voltage

regulation, as shown in Fig. 3.3.

Figure 3.3: The output voltage regulation is affected by the jitter (shown in the red circle) of itot[n].


For this reason, a hysteretic logic block of Fig. 3.2 is introduced, and the maximum current of

the variable-current phase is set to 1.5Inom. The operation of the hysteretic logic that creates the

actual phase enabling signal is described using Fig. 3.4.

Figure 3.4: Operation of the hysteretic logic – output phase enable signal versus input control value itot[n].

3.4 Transient Operation

Sudden load current changes ΔIload generate output voltage disturbances. To keep the output

voltage tightly regulated, the PI compensator from Fig. 3.2 immediately reacts by adjusting the

digital command itot[n] until the output voltage returns to steady state (e[n]=0). To achieve a fast

transient minimizing voltage deviation ΔV, it is necessary for the actual total current itot(t)=ΣiLi(t)

from all active phases to quickly follow the digital command itot[n]. This condition is challenging

to satisfy because the current slew rates are limited by the phase inductances and input-output

voltage conditions. For example, in a buck converter, the rising slope Δ1 of a phase current is

significantly larger than the falling slope Δ2 due to large difference between the input voltage vin

and the output voltage vout. The slope Δ1 and Δ2 can be calculated as:

L

vv outin −=∆1 , (3.5)

Lvout=∆ 2 . (3.6)


The effect of current slopes on itot(t) when the digital current command itot[n] is stepped down

from 5.4Inom to 3.6Inom is illustrated in Fig. 3.5. From Fig. 3.5, such a change in the itot[n] requires

that the largest phase 4Inom is disabled while phases 2Inom and Inom are enabled and the variable

phase is adjusted from 1.4Inom to 0.6Inom. The phases that are enabled quickly reach their nominal

currents within a single switching cycle Tsw since Δ1 is large due to vin>>vout. On the other hand,

for the largest phase it takes several switching cycles of the variable phase until the current in

that phase reaches zero. As a result, itot(t) initially goes in the opposite direction of itot[n],

creating an undesirable large voltage overshoot that will be demonstrated in Section 3.5.

Figure 3.5: The effect of finite rising Δ1 and falling current slope Δ2 on itot(t) for a step of the digital current command itot[n] from 5.4Inom A to 3.6Inom.


To eliminate this problem, two new blocks: phase enable corrector and transient current

estimator are added into the system as shown in Fig. 3.2. The role of the transient current

estimator is to calculate phase currents i4Inom[n], i2Inom[n], iInom[n] and ivar[n] and their total sum

isum[n] during the load transient. This can be achieved by monitoring the digital current command

itot[n-1] and the 4-bit corrected phase enable [n-1] command calculated in the previous switching

cycle. For example, if a corrected phase enable bit associated to a specific phase, changes from 1

to 0, the current in that phase starts to decrease from its nominal value at a rate equal Δ2 ∙ Tsw, in

each switching cycle. Similarly, based on the rising slope Δ1 the phase current can be estimated

when the phase is enabled again. Finally, by summing up all estimated phase currents, isum[n] is

obtained. The value of isum[n] is a digital equivalent of the actual total current itot(t) fed to the

load during the transient. To improve the accuracy of the estimation, when the converter reaches

steady state (e[n]=0 for several switching cycles), the current values for each phase are calibrated

using itot[n] from the PI compensator.

Simultaneously, based on the estimated currents, the phase enable corrector tries to match the

estimated current sum isum[n] to the digital current command itot[n] as close as possible. To

achieve this, it calculates necessary correction of the phase enable signal and the proper current

reference iref1[n] for the variable phase. The decision process starts by calculating the difference

δmax between the current command itot[n] and estimated current sum isum[n] less the estimated

current in the variable phase ivar[n]:

])[][(][ varmax ninini sumtot −−=δ . (3.7)

The value of δmax indicates the value of the maximum current increment that can be handled by

fixed-current phases 4Inom, 2Inom and Inom. Then by comparing the states of phase enable

command and the previous corrected phase enable command and by using δmax, phases are

enabled/disabled in such a way that the sum of all individual current increments in the fixed

phases δest = δ4 + δ2 + δ1 (δ4, δ2, and δ1 are obtained from Δ1 and Δ2 and current levels in the

phases during transient) does not exceed δmax. In the final step, the reference iref1[n] for the

variable phase applied in the next switching cycle is calculated as:

[ ]estsumtotref nininini δ+−−= ])[][(][][ var1 . (3.8)


Note that iref1[n] cannot exceed 1.5Inom and therefore if iref1[n] becomes larger than 1.5Inom it is

saturated to 1.5Inom.

Fig. 3.6 shows the simulated operation of the controller during a heavy-to-light load transient

between 5.4Inom and 3.6Inom. The PI compensator reacts to the increasing voltage deviation and

decreases itot[n] to the vicinity of the new load current level. Therefore the largest phase 4Inom

needs to disabled while phases 2Inom and Inom enabled. To perform the phase reconfiguration and

improve the converter efficiency without increasing the voltage deviation, the phase enable

corrector and transient current estimator first discharge the inductor current in the largest phase,

and then sequentially enable phases Inom and 2Inom as shown in Fig. 3.6. As a result, the multi-

phase converter is dynamically readjusted to operate at the most efficient phase configuration,

while providing small voltage deviation and fast response.

Figure 3.6: Simulated transient operation of the controller during a heavy-to-light load transient between 5.4Inom and 3.6Inom.

3.5 Design of Converter Phases Converter phases (i.e. power MOSFETs, gate driver circuit, the inductor and the phase switching

frequency) for the proposed system from Figs. 3.1 and 3.2, are selected to obtain high efficiency


based on the practical converter design guidelines given in [25]. In particular, the power

MOSFETs and gate driver circuits are chosen such that each phase operates at high efficiency

around its nominal operating current as illustrated in Fig. 3.7.a). To improve the overall

efficiency, the switching frequency of the largest phase is reduced to be twice lower than the

phase operating at 2Inom. On the other hand, to provide fast transient response, the variable and

Inom phase are configured to operate at the switching frequency 1.3 times faster than 2Inom phase.

The resulting efficiency curve of the complete system is shown in Fig. 3.7.b). It can be seen that

the resultant efficiency characteristic is improved compared to individual phase efficiency

characteristics and it is nearly constant for most of the load current range allowing for significant

energy loss reductions especially at light and medium load currents. The efficiency simulations,

presented in Fig. 3.7 are performed using loss models, in which detailed switching and

conduction losses of the power stages, as well as those of the gate drive circuits are included.

The models are developed based on the practical guidelines provided in [25].

The non-identical switching frequencies and non-uniform rated currents of the converter

phases impose a larger overall current ripple injected into the output capacitor. To provide small

output voltage ripple, a larger output capacitor is required. However, in portable applications, the

additional cost/size associated with the increased output capacitor can be compensated with the

Figure 3.7: a) Simulated efficiency characteristics of the converter phases operating at different switching frequencies b) Simulated efficiency of the whole system.


reduced battery size due to improved power supply efficiency. In practice, the number of phases,

their rated nominal currents, and switching frequencies can be further customized to suit a

particular application and expected load behavior.

3.6 Experimental System and Results Based on the block diagram of Fig. 3.2 an experimental 4-phase 40-A, 12 V-to-1.8 V system was

built. All digital blocks (PI compensator, hysteretic logic, phase enable corrector and transient

current estimator) are implemented with an Altera FPGA DE2 board as well as the DAC that

also uses an external reference and an RC filter. The main characteristics of the prototype buck

converter are listed in Table 3.1. The nominal current Inom is set to be 5 A, and the switching

frequencies of all stages but the two largest ones are the same.

Table 3.1: Important parameters of the 4-phase logarithmic buck converter

phase current [A]

fsw [kHz]

L [μH]

C [μF]

Ivar 0-7.5 650 0.9

800 Inom 5 650 0.9 2Inom 10 500 0.9 4Inom 20 250 0.9

3.6.1 Steady-State Operation

The steady-state converter operation for two different output load current is shown in Figs. 3.8.a)

Figure 3.8: Steady-state operation with two different load currents: a) 39 A b) 12 A; Ch.1: Output voltage (500 mV/div); Ch.2, Ch.3 and Ch.4: inductor current of variable phase, phase 2Inom, phase 4 Inom respectively – 6.66 A/V; D1-D4: Gate drive signals of all four phases. Time scale is 2 μs/div.


and 3.8.b). Fig. 3.8.a) shows the case when the output load current is 39 A, and all the phases are

turned on (4Inom = 20 A, 2Inom = 10 A, Inom = 5 A, and the current of the variable phase is Ivar = 4

A). The other case shows the situation when the load current is reduced to 12 A. To improve the

efficiency, the controller now turns off the phases 2Inom and 4Inom. A tight output voltage

regulation in both cases can be observed due to the operation of the variable phase that

dynamically changes to accommodate the difference between the load current and other phase

currents.

3.6.2 Transient Operation

To test the dynamic behavior of the proposed system and verify proper operation of the phase

enable corrector and the transient current estimator, both blocks are intentionally disabled first.

Then the output load is stepped down from 21 A to 19 A. The controller response is shown in

Fig. 3.9.a). As it is predicted in Section 3.4, due to the inappropriate transition in the inductor

currents, the output voltage exhibits a large overshoot of 150 mV although the load change is

only 2 A. In the next step, the phase enable corrector and the transient current estimator are

enabled and the controller response is tested again. The voltage deviation is now reduced by a

factor of 6 to 25 mV due to the operation of these blocks as shown in Fig. 3.9.b). The subsequent

phase reconfigurations are also prevented by the operation of hysteretic logic.

Figure 3.9: Transient response for a load step from 21 A to 19 A when the phase enable corrector and transient current estimator are: a) disabled b) enabled; Ch.1: Output voltage (200 mV/div); Ch.2, Ch.3 and Ch.4: inductor current of variable phase, phase 2Inom, and phase 4 Inom respectively – 6.66 A/V; D1-D4: Gate drive signals of all four phases. Time scale is 10 μs/div.


Figure 3.10: Transient response: a) from 9 A to 38 A; b) from 38 A to 9 A; Ch.1: Output voltage (200 mV/div); Ch.2, Ch.3 and Ch.4: inductor current of variable phase, phase 2Inom, and phase 4 Inom respectively – 6.66 A/V.

Finally, the converter operation is also verified with a large light-to-heavy (9 A – 38 A) and

heavy-to-light load step (38 A – 9 A) as shown in Figs. 3.10.a) and 3.10.b) respectively. During

the load transient, since the total current command itot[n] is dynamically changing to

accommodate new load conditions, the phases are turned on and turned off until the output

voltage settles down and itot[n] becomes constant. The response time is around 30 μs while the

maximum voltage deviation is 200 mV. Fast response of variable and Inom phases due to the

higher switching frequency helps also to reduce the peak of the voltage drop at the output

capacitor during the load transient.

3.6.3 Measured Converter Efficiency

Fig. 3.11.a) shows the measured efficiency of the converter with logarithmic current sharing and

that of an equivalent 4-phase power stage with the uniform current distribution. It can be seen

that the converter with logarithmic current sharing has a virtually flat characteristic over the

analyzed range of operation and results in an efficiency improvement of up to 25% at light loads,

and about 6% at medium loads. Compared to a 4-phase converter, switching at 500 kHz and

utilizing a phase shadowing method [10] for efficiency optimization, the converter with the

logarithmic current sharing provides on average a 1.5% efficiency improvement as illustrated in

Fig. 3.11.b) when the output load current is slowly varying. As the frequency of load disturbance

changes increases, the efficiency improvement for the logarithmic current sharing method

increases due to faster selection of the optimum number of the active converter phases.


Figure 3.11: Measured efficiency characteristics of the converter based on: a) logarithmic current sharing and uniform current sharing b) logarithmic current sharing and phase shadowing.

3.7 Conclusion In this chapter, a current-mode based digital controller and power stage with logarithmic current

sharing are introduced. The controller dynamically configures the number of active phases to

improve the efficiency of the converter. It is shown that by using a relatively simple controller

and a small number of phases a virtually flat efficiency characteristic can be achieved. The

digital controller requires no analog-to-digital converters for inductor current measurements and,

as such, is suitable for systems operating at high switching frequencies. In addition, due to the

use of the current-program mode, potential stability problems that exist for similar voltage mode

configurations are eliminated. Quantization effects and phase toggling problems existing due to

coarse current adjustments are addressed and resolved. The new system is implemented on a 4-

phase prototype and efficiency improvements and good dynamic characteristics are verified.

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46

Chapter 4 Reconfigurable Digital Controllers with Multi-Parameter Estimation

4.1 Introduction Power management systems used for low-power electronic devices require dedicated controller

circuits that provide protection from overload conditions [1], increase energy efficiency through

multi-mode operation [2,3] and obtain fast dynamic response [4]-[18]. For multi-phase

converters, controllers are also needed to ensure proper current sharing [19]-[25] between the

converter phases. Even if all phases are comprised of the same components, mismatches in their

actual values can result in serious problems. Some of the phases could take on significantly

larger currents than others, resulting in current-stress related system failures [1] due to

overheating and uneven component stress. To implement these critical features, actual converter

parameters need to be identified [26]-[28] and inductor currents need to be measured and

actively regulated to maintain safe operation.

Generally, the current measurement methods for dc-dc converters can be categorized into

voltage drop and observer based methods. In voltage drop based methods, a current passing

through a sense-resistor or a MOSFET is extracted from the voltage drop it causes [29]-[33]. The

observer-based systems usually estimate current from the voltage across the power stage inductor

[34,35].

In most cases, the existing methods are not well-suited for integration with the rapidly

emerging digital controllers of switch-mode power supplies (SMPS) for battery-powered

electronic devices, where the overall size, the system cost, and the overall efficiency are among

the main concerns [2,3]. The voltage drop methods either decrease efficiency of the converter

[29] or require a wide-bandwidth amplifier, which is very challenging to implement in the latest

CMOS digital processes. This is due to very limited supply voltages of standard digital circuits

(often below 1 V), at which traditional analog architectures cannot be used. Hence, bulkier and

less reliable multi-chip solutions are needed for such architectures, requiring a sensing circuit

and controller implemented in different IC technologies. On the other hand, the observer based

CHAPTER 4. RECONFIGURABLE DIGITAL CONTROLLERS WITH MULTI-PARAMETER ESTIMATION 47

methods suffer from limited accuracy [36]. The current estimation relies on prior knowledge of

the inductance and equivalent series resistance values [35,36], which depend on operating

conditions and change under external influences.

In addition to the current sensing methods described above, temperature monitoring of

switching components can be used to further improve system reliability. Dedicated temperature

sensors [37,38] can be placed next to the power switches as parts of the over temperature

protection system. They send information to the thermal protection circuit of the controller,

which, in the case of overheating, shuts down the SMPS. Again, the implementation of such a

system requires a multi-chip solution and is therefore unsuitable for low-power systems. Hence,

though very useful, the temperature protection of switching components is seldom applied.

The first goal of this chapter is to introduce a combined digital current and temperature

estimator, shown in Fig. 4.1.a), which is suitable for single-chip integration with modern low-

power digital controllers regulating the operation of single-phase and multi-phase converters.

The self-tuning current estimator, from Fig. 4.1.a), utilizes the flexibility of digital

implementation to compensate for the changes in the inductor parameters and achieve accurate

Figure 4.1: a) A digitally-controlled buck converter with the self-tuning current estimator and remote temperature monitoring system b) A dual-phase buck converter regulated by the non-linear multi-phase digital average current-mode controller based on the multi-phase self-tuning current estimator.


current estimation. In addition to a simple digital IIR filter and a load step circuit, the current

estimator only requires a slow analog to-digital converter for the input voltage measurement.

Therefore, a practical realization of the estimator results in a modest increase in digital controller

complexity. Additionally, from the converter parameters identified during the current estimator

calibration, such as the converter equivalent resistance Req that inherently includes the resistance

of the switching components, the temperature of the switches can be estimated and remotely

monitored in real-time to prevent system failures due to overheating, as shown in Fig. 4.1.a).

Both the current estimator and remote temperature monitoring system are also fully

implementable in the latest digital CMOS technologies allowing for a simple integration with the

upcoming digital controllers.

The second goal of this chapter is to propose a non-linear average current-mode digital

controller, shown in Fig. 4.1.b) that utilizes information about the estimated phase currents and

identified converter parameters (phase inductances and output capacitance) to achieve fast

transient response and dynamic current sharing. Recent digital and analog controllers [7], [12]-

[16], based on a capacitor charge-balance principle [7], are designed to provide superior time-

optimal response of single-phase converters. Unfortunately, their control actions and output

voltage response are sensitive to component tolerances and require both fast and accurate

detection of the voltage valley point. To effectively resolve previous implementation challenges,

the new two-step transient algorithm is introduced. The algorithm takes into account component

mismatches, eliminates the need for fast valley-point detection, and provides a bumpless

transition between two steady states by also considering the inductor current ripple. Uneven

aging and thermal stress of converter phases due the parasitic parameter mismatches are

prevented by dynamically adjusting the current distribution ratio based on the identified

information about phase equivalent resistances Req. As a result, dominant phase conduction

losses at heavy load and heat dissipation are dynamically equalized between all phases.

In the following section the basics of the inductor voltage based current estimation are briefly

reviewed and the principle of the operation of the self-tuning digital current estimator is

explained.


4.2 Principle of Current-Estimator Operation

Figures 4.2.a) and 4.2.b) explain the principle of operation of the conventional analog current

estimator [35] and the self-tuning digital system introduced in this paper, respectively. In the

analog implementation of Fig. 2.a), the inductor current iL(t) is extracted by placing an R-C filter

in parallel with the power stage inductor and measuring the filter’s capacitor voltage vsense(t). The

relationship between the capacitor voltage and the inductor current is given by the following

transfer function:

( ) ( ) ( ) ,11

1

1

f

LLL

ff

LLLsense s

sRsICRs

RLs

RsIsVττ⋅+⋅+

⋅⋅=⋅+

⋅+⋅⋅= (4.1)

where L and RL are the inductance and its equivalent series resistance values, respectively, and Rf

and Cf are the values of the filter components. When the filter parameters are selected so that τf

= Rf ⋅ Cf = L/RL = τL, the capacitor voltage becomes an undistorted scaled version of the inductor

current (the zero and pole cancel each other). This allows the inductor current to be reconstructed

from the capacitor voltage measurements. As mentioned earlier, the main drawback of this

method is that the inductor parameters are not exactly known and change over time, often

causing large errors in the estimation [36]. To compensate for these variations, an analog filter

Figure 4.2: Current sensing techniques: a) conventional analog implementation b) implementation with a self-tuning digital filter.


with programmable resistive networks is proposed in [39,40] where, in the latter publication, an

on-chip implementation of the filter is shown. Even though the method significantly improves

the estimator accuracy, its implementation still requires a relatively large number of analog

components and the sensed current is still an analog signal, making it less suitable for integration

with digital controllers in low-power SMPS.

In the new estimator of Fig. 4.2.b) the analog filter is replaced with a fully-digital and tunable

equivalent. In this implementation, the voltage across the inductor is converted into a digital

value vL[n] and then processed in the digital domain, to extract the output value isense[n], which is

directly proportional to the inductor current.

By manipulating (4.1) and applying a bilinear transformation, the simple difference equation

suitable for the practical digital filter implementation can be derived:

{ },])1[][(]1[1][][ 21 −+⋅+−⋅⋅⋅== nvnvcniRcRR

nvni LLsenseLLL

sensesense (4.2)

where c1 and c2 are filter coefficients:

),21/()12(1sLsL TR

LTR

Lc ⋅+−⋅= (4.3)

,)21( 12

−⋅+=sLTR

Lc (4.4)

and Ts is the filter sampling rate. The estimator adjusts the filter gain factor 1/RL from (4.2) and

coefficients c1 and c2 through a self-calibrating process. This is obtained with the help of a test

current sink connected at the converter output, as shown in Figs. 4.1 and 4.3. Periodically, the

sink implemented with a known resistor and a small switch connected parallel to the load, turns

on for a short time. Then, based on the response of the filter, the Gain/τ Calibration Logic block

adjusts the filter gain and coefficients so that the increase in isense[n] corresponds to the exact

increase in the load current. The calibration technique introduced here is similar to that in [40]

where a known test current is injected into the inductor during the converter start-up phase for

the purpose of calibrating an analog filter for current estimation. However, the limitation


Figure 4.3: Test current sink circuit used for the filter calibration.

of this method is that it cannot be used during regular converter operation because it requires

both converter switches to be turned off during the filter calibration phase. Since the series

inductor resistance RL and inductance L dynamically change, due to variations of converter

operating conditions (e.g. output load current or temperature), the accuracy of the current

estimation might be compromised. Since the current sink of Fig. 4.3 does not require any change

in converter operation, the method presented here can be used during normal converter operation

and the calibration can be performed regularly.

4.3 Practical Implementation of the Current Estimator

Even though the principle of operation of the self-tuning digital estimator is relatively simple, its

practical implementation is not trivial. It potentially requires a very fast ADC, with a sampling

rate significantly higher than the switching frequency, as well as an equally fast processor for the

filter implementation. These components threaten to make the estimator impractical for

cost-sensitive, low-power applications.

The precision and speed of the estimator depend on the accuracy of the measurement of the

average inductor voltage value. Even a small inaccuracy in this measurement can cause a large

estimation error. To obtain fast estimation, accurate measurement of the inductor voltage over

one switching cycle is required. This could be done with an ADC whose sampling rate is much

higher than the switching frequency. The need for a very high sampling rate converter is

illustrated in Fig. 4.4. In this case, the average value of the inductor voltage can be calculated by

summing the sampled voltage values and dividing the result by the number of samples taken

during one switching cycle. However, as seen in Fig. 4.4, the accuracy of this approach strongly


depends on the number of samples taken (i.e. the speed of the ADC), especially if the samples

are not perfectly aligned with the inductor voltage transition point.

Figure 4.4: Signals of a filter implemented with an over-sampling ADC.

To alleviate this dependency, the input voltage of the power stage vg(t) is sampled at a rate

lower than the switching frequency and the average value of the inductor voltage is calculated as:

],[][][][ nvnvndnv outinaveL −⋅=− (4.5)

where d[n] is the DPWM’s control variable and vout[n] is the converter output voltage, both of

which are readily available in the control loop of Fig. 4.1. The vout[n] value is provided by the

already existing ADC of the voltage control loop and the duty ratio is provided by the digital PID

compensator. A lower sampling rate is possible because in targeted battery-powered applications

the input voltage often changes in a very slow fashion. It should be noted that the complete

implementation of the new estimator, including ADC-s, is possible in standard CMOS processes.

Recent publications [2], [3], [41], [42] show application-specific ADCs for SMPS that are

implemented in the latest low-voltage CMOS technologies.

4.3.1 Filter Architecture and Self-Calibration

The calculation of the average voltage described in the previous subsection reduces hardware

requirements but concurrently affects the estimation accuracy. The actual average inductor

voltage might differ from (4.5), due to the action of non-overlapping, i.e. dead-time circuit, and

other parasitic effects. To compensate for this effect, as well as for the previously mentioned


variations in the inductor values, a current sink and calibration logic (Fig. 4.1) are used to tune

the parameters of the infinite impulse response (IIR) digital filter shown in detail in Fig. 4.5. The

calibration of the filter coefficients described with (4.2) and other parameters is performed in

three phases.

In the first phase, a known load current step is introduced by enabling the current sink and the

accurate value of the filter gain 1/RL is found from the variation in the estimated inductor current.

In the second phase, the current sink is disabled and the time constant τL = L/RL, determining

coefficients c1 and c2, is calculated from the estimator output overshoot/undershoot during the

load step-down transient. Finally, in the third phase, any offset in the estimated current due to the

action of the dead-time circuitry is removed by temporarily changing the switching frequency

and monitoring the response of the estimator. A more detailed description of the calibration

procedure is given in the following subsections.

Figure 4.5: The architecture of the tunable IIR filter used in the current estimator.

4.3.1.1 Filter Gain Calibration Procedure

The Calibration Logic block, shown in Fig. 4.1, periodically performs the calibration

procedure. The correct value of filter gain 1/RL is determined from the difference between two

steady state current values, estimated before and after a load step is applied as shown in Fig. 4.6.

The initial steady state is detected by monitoring the error signal e[n] and at the time instant A

(Fig. 4.6), the current before the transient is estimated as I1=isense[n] and stored in a register. After

a step ΔI is introduced and steady state is reached again, the new current I2 = isense[n] is found and

the difference,

ΔIm=I2−I1, (4.6)

is calculated. This value is then compared to the actual value of the current step and the actual


Figure 4.6: Filter gain calibration procedure: simulated response of the current estimator during output load change for two cases (bottom curve) the initial value of RL is twice the actual value (top curve) after the filter adjustment.

value of RL , named as RL_calibrated , is calculated as:

,__ initalLm

calibratedL RI

IR∆∆

= (4.7)

where RL_inital is the initially set resistance value. The filter gain value is then adjusted as:

.1

_ calibratedLRgainfilter = (4.8)

The value of RL_calibrated includes not only the actual inductor DCR resistance, but also all

parasitic resistances that are in the inductor current path between the input voltage and output

voltage sampling instance: parasitic drain-source on-resistances of switching devices and PCB

trace resistances. This is illustrated in Fig. 4.7.b) showing the steady-state dc equivalent circuit

derived from the converter shown in Fig. 4.7.a). From Fig. 4.7.b), based on Ohm’s law, the

correct filter gain that, in steady state, multiplies the average inductor voltage vL-

ave[n]=d[n]∙vin[n]-vout[n] to obtain the inductor current, is then:

[ ] ,)1(][

1

_2_1 tracesondsondsL RRndRndRgainfilter

+⋅−+⋅+= (4.9)

which is also calculated based on (4.8) as 1/RL_calibrated.


Figure 4.7: The buck converter (a) and its steady-state dc equivalent circuit Req (b) used for current estimation.

4.3.1.2 Filter Time Constant Calibration Procedure

The uncertainties of an actual inductor value L and its parasitic series resistance RL affect the

time constant τf (4.1) and therefore the time response of the filter. This effect is demonstrated in

Fig. 4.8 showing the actual and estimated inductor currents during a load step for different time

constants: the actual time constant τL, and 50% of this value. It can be seen that the estimated

current accurately follows iL(t) only when filter coefficients for the actual inductor value L and

RL are properly set. In other cases, the estimated current exhibits either undershoot or overshoot

as illustrated in Fig. 4.8. The calibration of τf is performed during the transient, at the output

voltage peak point (time instant B in Fig. 4.8), where the inductor current is equal to that of the

load current [12]. At this time instant, the estimated current is compared with the expected value

I1-ΔI and the difference, ΔIpeak, is calculated:

(4.10)

Based on ΔIpeak, the initially selected filter time constant τf, and the measured time interval ΔTpeak

between the moment when the sink circuit is disabled and the peak point is detected, the actual

inductor time constant τL is obtained:


(4.11)

For instance, for the simulation result shown in Fig. 4.8, τL is selected to be equal to 2τf and the

filter response exhibits a large overshoot when the sink circuit is disabled. By using the

parameters ΔIpeak=0.68 A and ΔTpeak=22 μs, dynamically obtained from the estimator response,

for the τf=32.6 μs and sink step size ΔI of 1 A, the inductor time constant τL according to (4.11)

is calculated to be equal to 2.02τf. As a result, it is possible to adjust the new filter time constant

τf based on the calculated τL from a single action of the sink calibration circuit. Once the correct

τL =L/RL is known, filter coefficients c1 and c2 are adjusted according to (4.3) and (4.4)

respectively.

The filter time constant tuning procedure presented here is significantly faster than previous

iterative-based procedures demonstrated in [39], [40], [43]. This allows the current estimator to

be utilized as a reliable solution for over-current protection and monitoring even if the power

stage components have large tolerances. The detailed derivation of (4.11) is given in Appendix

A.

Figure 4.8: Calibration of the time constant: simulated response of the current estimator during output load change between 2 A and 2.5A; (bottom) for τf=0.5τL; (top) for τf=τL.


4.3.1.3 Offset Calibration Procedure

Due to the operation of the dead-time circuit and unbalanced timing delays of gate driver

circuitry driving parasitic capacitances of power MOSFETs, the duty-ratio value of non-

overlapping control signals is different than the duty ratio command d[n] calculated by the PID

compensator from Fig. 4.1. Although the output voltage regulation is not affected since the

compensator automatically adjusts d[n] to compensate for Δd introduced by the dead-time

circuit, the current estimator produces an incorrect estimate of the inductor current as shown in

Fig. 4.9. The difference between the current estimation and inductor current is caused by the

incorrectly calculated average inductor voltage vL-ave[n] from d[n] according to (4.5). From Fig.

4.9 it can also be observed that the actual inductor voltage obtained as a difference of the voltage

at the switching node vLx(t) and the output voltage vout(t) does not have an ideal square-wave

shape shown in Fig. 4.4. The presence of voltage ringing at vLx(t), caused by converter parasitics,

influences the actual average inductor voltage calculated by the estimator from (4.5).

For instance, in steady state, with a duty ratio mismatch Δd added to the true duty ratio value,

the estimated current becomes equal to:

.][][)][(][][L

outintrue

L

aveLsense R

nvnvdndR

nvni −∆+== − (4.12)

If we rearrange (4.12), an offset in the estimated current becomes proportional to the duty

Figure 4.9: Offset in the estimated current isense[n] caused by the operation of the dead-time circuit and converter.


ratio mismatch Δd:

.][][][][][L

in

L

outintrue

sense Rnvd

Rnvnvndni ⋅∆+

−⋅= (4.13)

To eliminate the offset the following procedure is applied. By monitoring the error signal e[n],

the converter steady state is first detected and current sample I1 of the estimated current is taken.

In the next step, the switching frequency fsw of the DPWM is increased by k-times ( fsw’ = k∙ fsw )

and another sample I2 is taken once the steady state is reached again. Since the duty ratio

mismatch Δd is proportional to the switching frequency:

,swsw

ftT

td ⋅∆=∆

=∆ (4.14)

where Δt is a constant time interval caused by the dead-time circuit, from (4.13) and (4.14), I2

becomes larger than I1. Based on the difference between I2 and I1, the current offset from (4.13)

and (4.14) can be calculated as:

.1

][ 12

−−

=⋅∆

=k

IIR

nvdoffsetL

in (4.15)

In applications, where the input voltage may change significantly between two offset

calibrations, a sample of vin[n] (i.e. Vin_offset) can be also taken during the calibration and then

used to additionally scale the offset value by a factor vin[n]/ Vin_offset . This scaling dynamically

compensates for the offset deviation proportional to vin[n] as predicted by (4.13) and (4.15). The

estimated current is then corrected by subtracting the final offset value in the digital filter

architecture as shown in Fig. 4.5.

4.3.2 Steady-State Current Estimator Architecture

Knowledge about the inductor current in steady state is sufficient for significantly improving

system performance in many applications. For instance, to extend the battery life of portable

systems, multimode operation can be performed by monitoring the steady-state inductor current.

Examples of this include on-line switching between pulse-width and pulse-frequency modes of

operation [2], [44], dynamic sizing of power switches [45], and gate-drive circuit adjustments


[45]. For these cases, several parts of the current estimator system architecture of Fig. 4.1 can be

further simplified to obtain a steady-state current estimator [46,47] reducing system hardware

requirements and cost. For example, the programmable digital IIR filter calculating current

estimate isense[n] from Fig. 4.5 can be optimized for operation where only the steady-state current

is required. Consequently, the low-pass filtering logic shaping the response of the estimated

current during load transients is now removed. The average inductor voltage vL-ave[n] is fed

directly to the filter gain multiplication and offset adjustment. Since filter coefficients c1 and c2

are not used anymore, externally programmable look-up tables that keep their pre-calculated

values are also eliminated. Also, the calibration logic can be simplified by removing the filter

time-constant procedure that selects the proper set of filter coefficients.

Figure 4.10: The implementation of the steady-state current estimator.

4.4 Principle of Temperature Monitoring Operation

In the previous section, it is demonstrated that resistance RL_calibrated obtained during the gain

calibration procedure for the current estimator is represented by a sum of all parasitic resistances

in the inductor current path between the input voltage and output voltage sampling instance:

[ ] ..)1(][ _2_1_ tracesondsondsLcalibratedL RRndRndRR +⋅−+⋅+= (4.16)

According to (4.16), the parasitic on-resistances Rds1_on and Rds2_on of the converter power

switches are dominant parts of RL_calibrated. In addition to its original purpose of providing

accurate current estimation, the extracted value of RL_calibrated can now be used for monitoring the

temperature of the power switches and for overheating protection. As illustrated in Fig.11,

RL_calibrated depends on the temperature, meaning that, for a given operating condition, the

temperature of the switching components can be found from RL_calibrated and the load value.


As it will be shown later, a fairly accurate estimate of the temperature can be obtained by

using a look up table with pre-stored temperatures for a range of RL_calibrated and the load current

values. In Fig. 4.1, the look-up table is part of the temperature monitoring block. Overly high

temperature in the components causes RL_calibrated to exceed a certain threshold value Rthresh, at

which point the block shuts down the switches and also sends an external overheat signal.

Figure 4.11: Change of RL_calibrated due to the ambient temperature for different output load current conditions.

4.5 Inductor and Output Capacitor Identification

The system shown in Fig. 4.1.a), with little additional hardware, is also capable of providing the

controller with continuous information about key converter parameters: the sizes of the inductor

and output capacitor. These parameters can be further utilized to optimize the controller response

and implement power supply health monitoring [48]. To reduce the required hardware for the L

and C parameter identification, parameters obtained during the filter calibration are simply

reused for this purpose.


4.5.1 Inductor Identification

The inductor value L is estimated from the inductor time constant τL and resistance RL_calibrated.

Both τL and RL_calibrated are already found during the filter gain and time constant calibration

procedure described in Section 4.3. The inductance value L is then simply calculated from their

product:

._ calibratedLL RL ⋅=τ (4.17)

4.5.2 Output Capacitor Identification

The actual size of the output capacitor is estimated during the filter time constant calibration

when the output load current is stepped down by disabling the current sink as shown in Fig. 4.8.

The size of the output voltage deviation ΔVpeak caused by the sink action is obtained from the

voltage error signal e[n] at the peak point:

._ ADCqpeakpeak VeV ∆⋅=∆ (4.18)

where ΔVq_ADC is the quantization step size of the output ADC. Additional electric charge ΔQ

injected into the output capacitor C from the current difference between the inductor and load

current is proportional to the generated output voltage deviation ΔVpeak:

.peakVCQ ∆⋅=∆ (4.19)

Alternatively, if we approximate that the inductor current iL(t) linearly decreases with the slope

ΔI/ΔTpeak as shown in Fig. 4.8, the charge ΔQ during ΔTpeak can be expressed in terms of the sink

step size ΔI and time interval ΔTpeak as:

.21

peakTIQ ∆⋅∆=∆ (4.20)

By combining (4.19) and (4.20), the capacitor value C is estimated as:

peak

peak

VTI

C∆

∆⋅∆=

2, (4.21)


under the assumption that its ESR value is small. For example, for the waveform shown in Fig.

4.8, the output capacitor used for simulation is 200 μF. According to the waveform parameters

ΔTpeak = 22 μs and ΔVpeak = 54 mV for a sink step size ΔI of 1 A, the estimated capacitance is

equal to 203.7 μF.

4.6 Oversampled Non-Linear Average Current-Mode Controller

for Multi-Phase Converters

Unlike the voltage-mode controller from Fig. 4.1.a), the non-linear average current-mode

controller regulates both the output voltage and phase inductor currents by generating references

for the phase currents. As shown in Fig. 4.1.b), the new architecture is fully-digital, except for

the analog-to-digital converters (ADC) and the current sink. The multiple current-sensing circuits

are replaced with the multi-phase current estimator and current sink, allowing for significant cost

and size reduction of the multi-phase converter. Tight voltage regulation, fast transient response

and dynamic current sharing are obtained by switching between two modes of operation used for

steady-state and during large load transients. The new system is comprised of a PI compensator,

current sharing logic, current-compensator loops based on the multi-phase current estimator, and

a transient compensator. To enable rapid detection of sudden load disturbances and produce a

fast reaction of the controller, the output voltage ADC samples eight times per regular switching

cycle. The operation of the controller and its key blocks are described in the following

subsections.

4.6.1 Steady-State Mode

For light-load changes and in steady state, the controller operates as follows. Based on the error

between the output voltage and its reference, e[n], a PI compensator creates itot[n], a digital value

proportional to the total current of all phases, i.e. to the load current. The value itot[n], is then

passed to the current sharing logic that sets digital references irefi[n] for the currents of all phases

(i=1,…, N). To calculate the phase duty-ratio control signal di[n] such that the average of the

phase currents follows the reference irefi[n], the current compensators apply an average-current

dead-beat algorithm presented in [4], [49]:

[ ] [ ] [ ]( )ninikDnd senseirefiii −⋅+= , (4.22)


where D is the nominal steady-state duty ratio value, obtained as a ratio of the output voltage

reference Vref and input voltage vin[n]. The gain coefficient ki is proportional to the estimated

phase inductance Li and is dynamically adjusted as vin[n] changes according to:

swrefin

ii f

VnvLk ⋅−

⋅=][

5.0 . (4.23)

4.6.2 Multi-Phase Current Estimator Tuning and Phase Identification

The calibration process used for the single-phase topologies cannot be directly applied for multi-

phase converters regulated by the voltage-mode controllers. For the single-phase converter, the

load step introduced by the current sink must be equal to the inductor current. In multi-phase

converters, this is not the case. The current sink step can be shared between the phases in many

different ways, depending on the mismatch in power stage component values.

To solve this problem, the average current-mode controller is used and a phase-by-phase

calibration process, based on “freezing” the current of all phases but one, is implemented. As a

result only the current in the active phase increases and the increment is equal to that of the test

current sink allowing for proper current estimator calibration, as described in Section 4.3, for that

specific phase and accurate identification of parameters such as phase equivalent resistance Reqi,

where i =1,…,N.

The inherent capability of the current-mode controller from Fig. 4.1.b) to freeze the average

phase currents presents the possibility for a simplified capacitor/inductor identification algorithm

that does not require peak point detection. To eliminate errors in the identified parameters due to

periodic noise introduced by interleaved switching of the converter phases, the output capacitor

and inductances are also estimated based on a difference of two voltage samples. The samples

are taken at identical time instances during two switching cycles as illustrated in Fig. 4.12 so that

the common noise is subtracted. In the first step, the current references are frozen and the current

sink is disabled causing the output voltage to increase at a rate inversely proportional to the

output capacitor value. Shortly after the sink is disabled, the first voltage sample is taken. The

introduced delay eliminates the effect of the capacitor ESR on the capacitor identification. After

n switching cycles Tsw (e.g. n=2), the second voltage sample is then obtained. From the


accumulated voltage difference ΔV1 between two samples, the output capacitor is now estimated

as:

1VTnI

C sw

∆⋅⋅∆

= , (4.24)

where ΔI is the current sink current. In the second step, the current reference is reduced in the

phase where inductor value estimation is desired. This causes the inductor current to decrease.

After a delay of one switching cycle, the third sample is taken, and from the difference ΔV2 the

phase inductance is identified as:

sw

outswi TIVC

VTL⋅∆+∆⋅

⋅⋅=

2

22. (4.25)

Figure 4.12: Differential output capacitor and phase inductance identification.

4.6.3 Conduction Loss-Based Current Sharing Scheme

The output load current is often equally shared [19,20] between converter phases consisting of

components with identical nominal values and current ratings. Due to the enforced equal current

sharing, parasitic resistance mismatches of power switches and board traces between phases

produce higher conduction power losses in one of the phases. For instance, for modern high-

current integrated converters [50,51] supplying up to 35 A of current per phase, a small

mismatch of 1 mΩ generates more than 1 W extra power loss, or between 5% and 10% of total


conduction loss per phase at full load. The additional power loss generates more heat and

increases switch temperature [50], as shown in Fig. 4.13, leading to faster aging of components

and premature failure of one of the phases. To eliminate the temperature mismatch, the

controllers that adjust phase currents based on the feedback from external temperature sensors

mounted on the top of the power switches, were introduced in [52,53]. However, in practice,

such controllers are still not widely accepted in high-volume, cost-sensitive low-power

applications due to the increased component count, size, and circuit complexity.

To resolve this problem and eliminate the need for external temperature sensors, the controller

from Fig. 4.1.b) balances phase conduction losses based on the estimated phase resistances Reqi:

2222

211 LNeqNLeqLeq IRIRIR ⋅==⋅=⋅ , (4.27)

obtained during the calibration of the multi-phase current estimator. According to (4.27), for a

two-phase converter, shown in Fig. 4.1.b), the desired current sharing ratio is equal to:

2

1

1

2

eq

eq

ref

ref

RR

ii

ratio == . (4.28)

Figure 4.13: Mismatch in phase equivalent resistances generates unequal thermal stress on power switches.

From the resistance-based current ratio, the current-sharing logic from Fig. 4.1.b), splits total

current command itot[n] to produce current references iref1[n] and iref2[n] as:


[ ] [ ]niratio

ni totref ⋅+

=1

11 , (4.29)

[ ] ][][ 12 ninini reftotref −= . (4.30)

4.6.4 Transient Mode

The transient compensator block, shown in Fig. 4.1.b), detects large load current changes ΔIload

and dynamically overrides the operation of the conventional PI compensator to provide much

faster transient response and smaller output voltage deviation. It processes error values e[n] eight

times per switching cycle, which is four times faster than the PI compensator. From the error

difference between two consecutive samples e[n-1] and e[n], it calculates the slope of the output

voltage ΔVslope and accordingly estimates ΔIload:

sample

slopeload T

VCI

∆

∆⋅=∆ , (4.31)

where the actual value of the output capacitor C is obtained during the current estimator

calibration. If ΔIload surpasses a threshold (i.e. 1/3 of the maximum load current Iload), the

transient compensator temporarily disables the PI compensator, enters the transient mode and

executes a two-step control algorithm illustrated in Fig. 4.14 for a two-phase buck converter. The

load change threshold is set to prevent triggering of the transient compensator by the inductor

current ripple, switching noise, and more importantly to avoid frequent switch-on/off actions of

the power stage for light load changes that would decrease the power stage efficiency.

In the first step, depending on the sign of ΔIload the transient compensator decides whether to

turn on or turn off all phases in order to equalize the sum of average phase currents with the load

current. For a light-to-heavy load step, +ΔIload, the turn-on time ton is proportional to ΔIload and an

equivalent inductance Leq= L1 || L2 || … || LN of all phases now connected in parallel:

,loadoutin

eqon I

vvL

t ∆⋅−

= (4.32)

For a heavy-to-light load step, −ΔIload, the turn-off time is calculated as:


).( loadout

eqoff I

vL

t ∆−⋅= (4.33)

At the moment when all phases are switched on/off, the DPWM carrier value, used for the

synchronized generation of all pulse-width modulated signals, is frozen until either ton or toff are

finished. Once unfrozen, the original phase switching sequence resumes exactly where it was

interrupted as shown in Fig. 4.14. The inductor currents are brought to an average level,

accommodating the load current and the output voltage deviation is rectified. Before the first step

of the transient algorithm is fully completed, the transient compensator first updates itot[n] of the

PI compensator by adding an increment of ± ΔIload to its integral portion. The estimated average

phase currents isensei[n] are also modified by adding the transient increments Δvsensei to the

registers holding the sensed voltage vsensei[n]:

i

eqloadeqisensei L

LNI

Rv ⋅∆±

⋅=∆ . (4.34)

Once the voltage deviation is blocked, the transient compensator performs the second step that

quickly brings the output voltage back to steady state. The compensator now takes a voltage

sample, intended for the PI compensator, and measures the deviation ΔVdev at that point as shown

in Fig. 4.14. The total capacitor charge that needs to be recovered to reach the new steady state is

equal to:

devdev VCQ ∆⋅=∆ . (4.35)

To compensate for ΔQdev and achieve a bumpless transition when the PI compensator is

reactivated, the transient compensator increases the duty ratio of all phases to D+Δdi during the

first switching cycle. In the following cycle, the duty cycles are dropped to D−Δdi. As a result,

an additional charge, ΔQi, is injected by each phase but the phase average currents are positioned

properly for the PI compensator to resume as shown in Fig. 4.14. The injected charge by each

phase is proportional to Δdi:

2swi

i

ini Td

LvQ ⋅∆⋅=∆ . (4.36)


If ΔQdev is now shared between N phases, the required Δdi for each phase is equal to:

in

deviswi v

VN

CLfd ∆⋅

⋅⋅=∆ 2 . (4.37)

Figure 4.14: Transient mode operation of the non-linear average current-mode controller.


To generate increments ±Δdi with minimal additional hardware, the current-loop

compensators are utilized. They are produced by changing the current references by ± Δirefi. The

phase injected charge ΔQi can be expressed in terms of Δirefi from (4.22) and (4.36) as:

2swrefi

i

ini Tik

LvQ ⋅∆⋅⋅=∆ . (4.38)

Finally, by substituting (4.23), and (4.35) to (4.38), Δirefi for each phase is equal to:

devswrefi VCDfN

i ∆⋅⋅−⋅⋅

=∆ )1(2

. (4.39)

If necessary, to avoid current saturation of the inductors, the introduced current reference step

Δirefi can be reduced by extending it across several switching cycles ncycles as:

reficycles

refi in

i ∆⋅

=∆

1' . (4.40)

Once the charge ΔQdev is fully compensated, the transient compensator reactivates the PI

compensator which then continues to regulate the output voltage until the next large load

transient occurs.

4.6.5 Hardware Optimization and Controller On-Chip Complexity

To achieve a cost effective on-chip implementation, the controller hardware from Fig. 4.1.b) is

carefully optimized for multi-phase operation. Since all phase control signals are interleaved, the

current estimator is also time multiplexed to reduce computation resources (logic multipliers and

adders). The block diagram of the multi-phase current estimator is shown in Fig. 4.15. The same

approach is applied to the current compensators which are implemented as a single time-

multiplexed current compensator calculating duty cycles intermittently. Finally, to reduce the

number of internal registers used by both blocks and share partial computation results, the

transient compensator and current estimator tuning logic are merged. Table 4.1 shows the

occupied area and number of digital cells for each digital block when implemented in TSMC

0.18-µm CMOS technology. All digital blocks of the controller, shown in Fig. 4.1.b) occupy


0.43 mm2 of silicon area or equivalently 15,610 digital logic cells.

Figure 4.15: A time-multiplexed N-phase digital current estimator.

Table 4.1: The silicon area and gate count of the multi-phase controller when implemented in TSMC 0.18-µm CMOS process.

Design Block area [mm2] logic cell count

PI compensator 0.051 1767 Current sharing logic 0.017 632 Two-phase current estimator 0.080 2716 Current compensators 0.022 830 Transient compensator & current estimator tuning logic 0.247 8811 Two-phase DPWM (8-bits resolution) 0.021 854

Total (digital blocks) 0.438 15610

4.7 Experimental Systems and Results

An experimental single-phase system was first built based on the diagrams shown in Figs. 4.1.a),

4.3, and 4.5. The power stage is a 15-W, 1.5-V buck converter (nominal output filter component

values are L=1.5 μH and C=200 μF), switching at fsw=500 kHz, with an input voltage range

between 2 V and 6.5 V. The controller, digital filter, calibration logic, temperature and current

monitoring logic are realized with an Altera DE2 FPGA board by Verilog HDL. Two external

ADCs sampling at fsw and fsw/8 are used for output and input voltage measurements respectively.

The resolution of the ADC sampling the output voltage is 4 mV, while the resolution of the ADC

for the input voltage is 16 mV. The test current sink was set to produce a 1 A pulse current,


which is only 10% of the maximum output current. To visualize the operation of the estimator,

its digital output was sent to a flash digital-to-analog converter (DAC) and the resulting analog

signal was observed.

Figure 4.16 shows the closed loop operation of the controller during load transients between

1.5 A and 4.5 A (ΔI = 3 A) and demonstrates the self-tuning process of the current estimator. In

the first (uncalibrated) phase due to the mismatch in the converter parameters, the filter gain,

time constant τf , and offset are not properly adjusted and an error in the current estimation

occurs (the step is wrongly recognized as a 2.3 A to 4.3 A transition - ΔIest = 2 A). In the second

Figure 4.16: System operation – Ch1: Output converter voltage (200mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; D0-D1- load step and sink enable signals; Time scale is 500 μs/div.

(calibration) phase, a 1-A test current sink step is introduced and the filter gain, the filter

coefficients defining time constant τf, and offset are tuned accordingly. The third (calibrated)

phase shows repeated load transient, where the average current is estimated accurately both in

steady state and during the transient, verifying the effectiveness of the self-tuning filter and the

estimator operation.

4.7.1 Filter Gain Calibration

To correct the filter gain (34% lower than its correct value) causing the actual inductor current

step of 3 A to be recognized as a 2-A step in the estimated current during the uncalibrated phase


in Fig. 4.16, the filter gain calibration procedure based on a current sink is applied. Fig. 4.17

shows explicitly the operation of the current estimator during the filter gain calibration when the

current sink is enabled. By monitoring the voltage error signal e[n], the calibration logic detects

the steady state (e[n]=0 for 8 consecutive cycles) before and after the current sink is enabled and

measures the difference ΔIm in the estimated steady-state currents to be 0.66 A. From ΔIm and the

known value of the current sink step size ΔI=1 A, according to (4.7) and (4.8), RL_calibrated is

calculated and the filter gain is therefore updated as shown in Fig. 4.17. As a result, the estimated

current is increased by approximately ΔI/ ΔIm≈1.51 times. If a real load transient occurs during

the calibration, the obtained parameters are rejected and the procedure is repeated again.

Figure 4.17: The filter gain (1/RL_calibrated) calibration procedure – Ch1: Output converter voltage (100 mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; D0-D1- load step and sink enable signals; Time scale is 20 μs/div.

4.7.2 Filter Time Constant Calibration

Initially selected filter time constant τf = 25.5 μs during the uncalibrated phase is approximately

half of the inductor time constant τL =L/RL_calibrated=1.5 μH/ 30 mΩ =50 μs resulting in a large

overshoot of the estimated current as shown in Fig. 4.16. Shortly after the filter gain is calibrated

by enabling the current sink, the calibration of τf is performed by disabling the current sink

causing the inductor current to drop by the value of the sink step size ΔI = 1 A. The actual tuning

process of the filter time constant τf is demonstrated in Fig. 4.18.a). The calibration logic first

measures the estimated steady-state current I1 before the current sink is disabled. In the next step,


the sink enable signal is set to zero and due to the closed-loop operation the inductor current and

its estimate start to decrease. Once the calibration logic detects the output voltage peak recovery

point, meaning that the inductor current is equal to the new steady-state inductor current I1-ΔI,

the difference ΔIpeak between the estimated current and I1-ΔI is calculated to be 0.65 A according

to (4.10). At the same time, the time period ΔTpeak between disabling the sink circuit and the

detection of the peak point is captured to be ΔTpeak= 20 μs. Based on the initially selected τf, and

the parameters obtained from the estimator response ΔIpeak for the sink step size of ΔI, the

calibration logic calculates the inductor time constant τL according to (4.11) to be 52 μs. Once

the actual inductor constant is identified, the filter time constant is matched to τL and the

coefficients c1 and c2 are properly adjusted.

Figure 4.18: The filter time calibration procedure: a) τf=0.5τL ; b) τf ≈ τL – Ch1: Output converter voltage (100 mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; D0-D1- load step and sink enable signals; Time scale is 20 μs/div.

As a result, the estimator now exhibits proper response even during the transient as shown in

Figs. 4.18.b) and 4.16 (during the calibrated phase). From the parameters obtained during the

filter time constant calibration (ΔTpeak= 20 μs and ΔVpeak= 75 mV), the size of the output ceramic

capacitor is estimated to be 133 μF. The estimated capacitor value is 34% lower than its nominal

data sheet value at zero bias voltage. This is caused by the DC bias effect [52], caused by the

output voltage, that reduces the actual capacitance of ceramic capacitors.


4.7.3 Offset Calibration

Even though the filter gain and time constant are now properly adjusted, the current estimator

still exhibits an offset of 2 A between the estimated and the true inductor current as shown in

Fig. 4.19. To compensate for this offset, the calibration logic samples the estimated steady-state

currents before and after increasing the switching frequency by two times (k=2). Based on (4.15),

the estimated offset is calculated by the calibration logic to be 2 A. Shortly after the switching

frequency is reduced back to the nominal value, the offset value is subtracted in the digital IIR

filter and good matching between the estimated and actual inductor currents is obtained as

demonstrated in Fig. 4.19.

Figure 4.19: The filter offset calibration procedure – Ch1: Output converter voltage (100 mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; Time scale is 20 μs/div

4.7.4 Calibrated Operation

Figs. 4.20.a) and 4.20.b) demonstrate fast operation of the estimator when the gain, time constant

and offset are properly tuned. They compare actual and estimated inductor current during both

light-to-heavy and heavy-to-light load changes between 1.5 A and 4.5 A. As it can be seen, the

average value of the current over one switching cycle is accurately estimated without any

significant delay, allowing the estimator to be used for overload protection and power stage

efficiency optimization.


Figure 4.20: The estimated current during load steps between 1.5 A and 4.5 A– Ch1: Output converter voltage (200 mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; Time scale is 10 μs/div.

4.7.5 Current Estimation with the Steady-State Current Estimator

The operation of the simple steady-state current estimator based on Fig. 4.10 is experimentally

verified in Fig. 4.21 by varying the output load current between 0.8 A and 5.1 A. In this case, the

estimated current is calculated from the average inductor voltage with a direct multiplication by

the filter gain without filtering with coefficients c1 and c2. As a result, the estimator provides

accurate information about the inductor current only in steady state but its hardware

Figure 4.21: The estimated current with a steady-state current estimator during the load step between 0.8 A and 5.1 A– Ch1: Output converter voltage (200 mV/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current iL[n] – 2 A/V; Time scale is 50 μs/div.


implementation is much simpler since it does not require time constant calibration.

4.7.6 Temperature Monitoring and Protection

Figs. 4.22.a) and 4.22.b) verify proper operation of the temperature estimator/protection block

from Fig. 4.1.a). To test its operation, the converter power MOSFETs are intentionally heated

up. As it can be seen from Fig. 4.22.a), this results in an increase of RL_calibrated (see Fig. 4.22.b)

above the threshold resistance Rthresh, and the triggering of the overheating protection signal that

shuts down the converter.

Figure 4.22: Thermal monitoring: a) at 45 °C; b) at 105°C – Ch1: Output converter voltage (1 V/div); Ch2: estimated steady-state current isense[n] – 2 A/V; Ch3: estimated RL_calibrated – 1 mΩ/32.5 mV; Ch4: MOSFET temperature – 25 ºC/V; D1-D2- sink enable and overheat signal. Time scale is 200 μs/div.

4.7.7 Overload Protection

Simple overload protection of the converter circuitry can be obtained by comparing the output of

the current estimator with a predefined digital current threshold. Once the estimated current

exceeds the threshold value, to prevent converter damage, it is immediately turned off and the

estimator stops its operation as shown in Fig. 4.23. The output load current is intentionally

increased from 2 A to 7.5 A above the threshold of 7 A. Therefore the overload protection signal

is activated and the converter is rapidly turned off.


Figure 4.23: Overload protection implemented with the current estimator– Ch1: Output converter voltage (1 V/div); Ch2: actual inductor current iL(t) – 2 A/V; Ch3: estimated average current isense[n] – 2 A/V; Time scale is 20 μs/div.

4.7.8 Multi-Phase Operation with the Non-Linear Average Current-Mode

Controller

To verify the operation of the non-linear average current-mode controller, from Fig. 4.1.b), the

single-phase buck is now replaced with a point-of-load, two-phase, 80-W, 12-V-to-1.8-V buck

converter switching at fsw=500 kHz. The nominal phase inductances are 0.325 µH (±10%

tolerances) while the total nominal output capacitance is 800 µF (-20/+50% tolerance). To

accommodate the increased input voltage range (up to 16 V), the effective input ADC resolution

is decreased to 32 mV by a voltage divider (1/8). On the other hand, the sampling rate of the

output voltage ADC is increased to 8 times per switching cycle. The current sink used for the

calibration of the multi-phase current estimator is increased to 4 A (less than 10% of max. load

current) due to the increased output capacitance. Shortly after the system start-up, when the

output voltage reaches steady state, the controller initiates the tuning of the multi-phase current

estimator parameters and identifies the actual phase component values. Fig. 4.24 presents the

tuning procedure applied on the first phase, while the second phase current is “frozen.” Initially,

both the gain and time constant of the current estimator are incorrect. After injecting the step and

performing the multi-phase calibration procedure described in Section 4.6, the parameters are

identified. From Fig. 4.24 it can be observed that the current step of the sink fully excites the

active phase. After, the calibration is performed; the corrective action is taken and the estimated


current is now properly tuned. The identified output capacitance is 500 µF, which is 37.5% lower

than its nominal value due to the capacitor DC bias effect [54].

Figure 4.24: Current estimator tuning and component identification with the multi-phase converter – Ch1: Output converter voltage (50 mV/div); Ch2: actual phase 1 inductor current iL1(t) – 10 A /V; Ch3: actual phase 2 inductor current iL2(t) – 10 A /V; Ch4: estimated current isense1[n] – 10 A/V; D1 - sink enable signal. Time scale is 20 μs/div.

After the tuning and power-stage identification are completed, the response of the non-linear

multi-phase controller is tested with a large load step (0 A − 45 A) as shown in Fig. 4.25. As

soon as the sharp voltage drop is detected and ΔIload is estimated, the transient compensator first

turns on both phases to block the voltage deviation. It can be noticed that phase inductances are

significantly mismatched (≈20%), since iL1(t) is able to reach iL2(t) at the end of the turn-on

action. The transient compensator now measures the voltage deviation and performs the control

actions based on the change of current references producing duty ratio increments ±Δdi. The

current-loop compensators recognize the mismatch of phase inductances and current undershoot

in the second phase. To compensate they provide a larger initial current step for the second phase

as shown in Fig. 4.25. Once the output voltage reaches the new steady state within 5 μs, the

current compensator regulate inductor currents until they match the current ratio specified by

their equivalent resistances.

Finally, the effectiveness of the conduction loss-based current scheme that equalizes the

thermal stress of converter phases is verified. Initially, equal duty cycles of control signals c1(t)

and c2(t) are enforced to show that phase equivalent resistances are indeed mismatched. As

shown in Fig. 4.26.a), the average phase currents are now unequally distributed based on the


ratio of Req1 and Req2. Phase 1, taking significantly larger portion of the output load current than

Phase 2, has also much higher operating temperature (ΔT12 = 17.8 °C) as demonstrated in Fig.

4.26.b). Then, the conduction-loss based current sharing scheme is enabled. The load current

Figure 4.25: Transient response of the nonlinear average current-mode controller – Ch1: Output converter voltage (50 mV/div); Ch2: inductor current iL1(t) – 10 A /V; Ch3: inductor current iL2(t) – 10 A /V; Ch4: estimated phase 2 current isense2[n] – 10 A/V; D1-D3- sink enable and control signals. Time scale is 5 μs/div.

Figure 4.26: The effectiveness of the conduction-loss based sharing scheme – a) current sharing with equal duty cycles of control signals c1(t) and c2(t); b) mismatched phase temperatures with equal duty cycles of c1(t) and c2(t); c) conduction-loss based current sharing; d) phase temperatures with the conduction-loss based sharing scheme.


is now distributed between phases based on the square root ratio of Req1 and Req2 (Fig. 4.26.c)) to

equalize the conduction losses of both phases. Consequently, the phase temperatures are now

well balanced (ΔT12 = 1.4 °C) as demonstrated in Fig. 4.26.d).

4.7.9 Accuracy of Current and Temperature Estimation

The accuracy of the current estimation is assessed by changing the load current and comparing it

to the estimated value. Before the accuracy measurements are performed, the estimator is

calibrated only once at 30% of the maximum load current. Fig. 4.27.a) shows that a fairly good

estimate is obtained. For the full load, the relative error of the estimation is less than 5% while

for 90% of the full load it is less than 10%. At lighter load, the error increases due to

quantization effects. If the sink step size is increased from 1 A to 2 A, the error is reduced on

average by 1.3% as illustrated in Fig. 4.27.b). Fig. 4.28 shows results of the temperature

estimation. It can be seen that the absolute error of the temperature estimation is limited to ±7 °C

while the relative error is less than 10%. The precision of this measurement depends on the size

of the look-up tables and the accuracy of the data stored in the estimator look-up tables.

Figure 4.27: a) Estimated inductor current versus the output load current with a 1 A sink step size b) Relative error of the estimated current for two sink step sizes: 1 A and 2 A.


Figure 4.28: Estimated temperature versus sensor temperature.

4.8 Conclusion This chapter introduces a combined self-tunable digital current and temperature estimator and the

non-linear sensorless average current-mode controller with for multi-phase dc-dc converters.

Based on the measurement of the inductor voltage and its processing in the digital domain the

current estimator calculates the average value of the inductor current over one switching cycle.

To compensate for the variations in power stage parameters that currently limit the accuracy of

equivalent analog methods, the estimator automatically extracts the main converter parameters

and self-adjusts its parameters by using a test current sink and a tunable IIR filter. Compared to

previous iterative-based tuning methods, the tuning procedure is much faster since it requires

only a single action of the sink circuit. From the extracted equivalent resistance, the temperature

of the MOSFETs is remotely estimated and continuously monitored. The fast and accurate

operation of the current and temperature estimator is demonstrated on a digitally controlled buck

converter prototype.

The non-linear average mode controller utilizes the identified power stage parameters and

estimated phase currents to provide fast transient response and dynamic current sharing. To

equalize the thermal stress between phases, a conduction-loss based current sharing scheme is

implemented. The operation of the controller is verified with a two-phase point-of-load, 80-W,

buck converter showing the response time under 5 μs and a voltage deviation smaller than 100


mV for a 45-A load step. The digital blocks of the controller are suitable for an on-chip

implementation since they occupy only 0.43 mm2 of silicon area when synthesized in a CMOS

0.18-μm process.

REFERENCES

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87

Chapter 5 Conclusions and Future Work

This thesis presents advanced reconfigurable digital controllers of multi-phase dc-dc converters

utilized for power management systems in low power applications, up to 100 W. The proposed

architectures are suitable on-chip integration and provide practical hardware solutions for a broad

range of implementation issues related to: controller power consumption, dynamic converter

efficiency optimization, current estimation, temperature monitoring, converter parameter

estimation, and combined fast transient response and dynamic current sharing. In the following

sections the thesis contributions are summarized, and future work is discussed.

5.1 Thesis Contributions The most significant contributions of this dissertation are:

1) Multi-Use and Fault-Tolerant Digital Controller IC: A flexible four-phase digital

PWM controller IC that can be used with interleaved, multi-output, and parallel dc-dc

switching converters operating at frequencies up to 10 MHz is proposed. The IC can be

programmed to operate with any number of converter phases and it is fault-tolerant.

During interleaved mode, if a failure in one of the phases occurs, it automatically

switches to operation with reduced number of phases by disabling the faulted phase and

adjusting the angles of the remaining ones. The key element of this IC is a new

multiphase digital pulse-width modulator (MDPWM) that utilizes a programmable

counter, programmable delay line, and digital logic with variable numbers representation.

The MDPWM produces four pulse-width modulated control signals whose switching

frequency can be adjusted between 100 kHz and 10 MHz with an effective resolution of

11 bits of input duty ratio commands. The controller IC is realized in standard 0.18 μm

CMOS process and exhibits low power consumption of 90.25 μA/MHz per phase. Due to

its flexibility and low-power consumption, the IC can be utilized in various applications

including low-power, battery-powered electronic devices where multiple supply voltages

are required.

CHAPTER 5. CONCLUSIONS AND FUTURE WORK 88

2) System for Dynamic Efficiency Optimization of Multi-phase DC-DC Converters: A

novel current-program mode digital controller and a multiphase dc-dc converter with

non-uniform current sharing that dynamically optimize converter efficiency over the full

range of operation are introduced. The converter phases are operated as binary-weighted

constant current sources, i.e. scaled in a binary-logarithmic fashion. To minimize the

system size and provide fast dynamic response, the phases switch at different frequencies

and their components are selected so that the most efficient operating points correspond

to the set currents. The digital controller operates on a modification of the “phase

shadowing” principle. Depending on the output load, the number of active phases is

dynamically configured. The new architecture of the controller does not require an

analog-to-digital converter for current measurement and is suitable for high-frequency

low power converters. An experimental 4-phase, 70-W, 12 V-to-1.8 V buck converter

utilizing the digital control architecture with logarithmic current sharing is built. A

comparison of the efficiency with an equivalent uniform current shared converter shows

that, at medium and light loads, the presented system results in efficiency improvements

of up to 6% and 25%, respectively.

3) Reconfigurable Digital Controllers with Multi-Parameter Estimation: A

reconfigurable digital controller architectures providing estimation of inductor currents,

identification of key converter parameters, and temperature monitoring of power switches

in single-phase and multi-phase dc-dc converters are presented. To perform component

parameter estimation and current estimator calibration with multi-phase converters, a

method based on “freezing” phase currents is proposed. The non-linear sensorless multi-

phase average current-mode controller utilizes the identified power stage parameters and

estimated inductor currents to provide fast transient response, while maintaining dynamic

current sharing and equalized thermal stress between converter phases. The equal thermal

stress of converter phases is obtained by regulating phase currents in order that the phase

conduction losses are balanced. The new controller eliminates the need for accurate

output voltage valley point detection and can operate at modest oversampling rates of the

output voltage. Both controller architectures are well-suited for on-chip implementation.

They provide a solution for combining a digital controller, current estimator and remote

temperature monitor on a single integrated circuit. The estimation of the average inductor

CHAPTER 5. CONCLUSIONS AND FUTURE WORK 89

current value over one switching cycle is based on the analog-to-digital conversion of the

inductor voltage and consequent adaptive signal filtering. The adaptive digital IIR filter is

used to compensate for variations of the inductance and dc resistance emulating converter

losses and affecting accuracy of the estimation. The operation of both controllers is

verified with a single-phase 5.5 V-to-1.5 V, 15-W buck converter and dual-phase 12 V-

to-1.8 V, 80-W, buck converter, both operating at a switching frequency of 500 kHz. The

results show that the current and temperature estimations are accurate with error less than

10%. The current estimation has the response time of one switching cycle. Dynamic

current sharing combined with small transient response time, under 5 µs for a 45-A load

current step, are obtained with the dual-phase buck converter having an output capacitor

of 500 µF. The digital blocks of the new multi-phase controller occupy only 0.43 mm2 of

silicon area when implemented in 0.18μm CMOS process.

5.2 Future Work

Future work could include a development of a digital controller IC that now intelligently

combines the best features of all presented controllers in this thesis. For instance, a system for

dynamic efficiency optimizations of multi-phase converters could be merged with the sensorless

non-linear average current-mode controller. The operation of the current-mode controller could

be also modified to dynamically balance converter losses from the information about phase

components and phase currents in the presence of high-frequency load steps. Finally, the current

sink for current estimator calibration and oversampling output voltage ADC for load transient

detection and estimation could be potentially eliminated or simplified (in case of the ADC) by

establishing a “digital communication link” between the switch-mode power supply and its load.

From the information passed to the controller about the operating mode, the specific activity of

the load device, and its current consumption, the current estimator could be periodically

calibrated while the requirement for oversampling of the output voltage would be eliminated.

90

Appendix A Filter Time Constant Calculation

To derive the equation that links the filter time constant τf and inductor time constant τL with

properties of the estimated current in order to perform the filter time constant tuning, the

following approximation is made. It is assumed that during the initial transient, the average

inductor current behaves as a ramp signal with a slope k. The Laplace transform of iL(t) in that

case is equal:

( ) .12s

ksI L ⋅= (A.1)

The sensed current according from the output of the RC filter according to (4.1) and (A.1) is then

equal to:

( ) ( ) ,1111

11

22f

L

L

f

f

L

f

LLsense s

ss

kss

sk

sssIsI

ωω

ωω

ττ

ττ

++

⋅⋅⋅=++

⋅⋅=++

⋅= (A.2)

where ωf=1/τf and ωL=1/τL. The sensed current Isense(s) now can decomposed as:

( ) ,2f

sense sC

sB

sAsI

ω+++= (A.3)

where coefficients A, B, and C are:

,Lf

LfkAωωωω⋅

−⋅= (A.4)

,kB = (A.5)

.Lf

LfkCωωωω⋅

−⋅−= (A.6)

APPENDIX A. FILTER TIME CONSTANT CALCULATION 91

91

By using the fact that the middle term of Isense(s) in (A.3) is equal to IL(s) from (A.1) and after

applying the inverse Laplace transform, the sensed inductor current becomes equal to:

( ) ).()1( tiekti Lt

Lf

Lfsense

f +−⋅⋅

−⋅= ⋅−ω

ωωωω

(A.7)

The difference ΔIpeak between the estimated current and actual inductor current when the output

voltage peak point occurs at t= ΔTpeak is then equal:

(A.8)

where the slope k is equal to ΔI/ ΔTpeak.

From an approximation that e-x ≈ 1-x+x2/2, where x= ωf∙ΔTpeak, to simplify (A.8), it can be shown

the ratio between ωf and ωL is:

(A.9)

Finally, by rearranging (A.9) the inductor time constant τL now can be expressed in terms of the

filter time constant τf as:

(A.10)

92

Appendix B Quantization Error Effects on Current Estimator Accuracy

The accuracy of the digital current estimator is affected by quantization errors introduced by

the input and output voltage ADCs. The steady-state estimated inductor current, according to

Ohm’s law is equal:

eq

outinsense R

nvnvdni ][][][ −⋅= . (B.1)

The worst-case absolute error of isense[n] is found from the sum of absolute values of the partial

derivatives of (1) multiplied with the absolute errors of vin and vout :

outout

sensein

in

sensesense v

viv

vii ∆⋅+∆⋅=∆

δδ

δδ

. (B.2)

After substituting the partial derivatives of isense[n], the absolute error of isense[n] then becomes

equal to

outeq

ineq

sense vR

vRdi ∆⋅−+∆⋅=∆

1, (B.3)

where Δvin, Δvout, are absolute errors of the input voltage and output voltage. Both errors Δvin and

Δvout in the worst case are equal to the half of the quantization step for the input and output ADC.

Table B.2: Current estimator relative error versus quantization step of the output voltage ADC.

relative error [%]

Vq[mV]

1.0 1.1 2.0 2.1 4.0 4.3 8.0 8.5

16.0 17.1

For example, we may consider a 12 V-to-1.5 V buck converter operating at a full load of 30 A

and having Req of 15 mΩ, an output voltage quantization step of ΔVq = 4mV and the input one 4

times larger. The relative error of the current estimation then becomes equal to 4.1%. Table B.1

APPENDIX B. QUANTIZATION ERROR EFFECTS ON CURRENT ESTIMATOR ACCURACY 93

93

provides the values of the relative errors for the current estimation calculated for different sizes

of output quantization steps ΔVq.

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