Design and Implementation of Low Power FFT

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Orthogonal Frequency Division Multiplexing is a scheme used in the area of high-data-rate

mobile wireless communications such as cellular phones, satellite communications and digitalaudio broadcasting. The Fourier transform, in essence, decomposes or separates a waveform or

function into sinusoids of different frequencies which sum to the original waveform. It identifies

or distinguishes the different frequency sinusoids and their respective amplitudes.

In many applications high-speed performance is required. For this purpose, conventional multi-

carrier techniques are usually chosen, but this result in the lowering of spectrum efficiency. So,the principles of Orthogonal Frequency Division Multiplexing are used in such applications. This

paper gives the details of the development of IFFT & FFT algorithms to be used in OFDM

systems based on the IEEE 802.11a standard for WLAN. This system consists of separateOFDM transmitter & receiver. Actually, in the entire architecture of OFDM system, all the

mathematical manipulations take place in these two blocks only, i.e. IFFT & FFT blocks while

rest of the blocks convert the data from one format to another format. In this paper we have

implemented FFT and IFFT blocks. The speed enhancement is the key contribution of the main

processing blocks in OFDM system.

However, the advent of the Discrete Fourier Transform (DFT) made this transmission schememore plausible. The Fast Fourier Transform (FFT) and the Inverse Fast Fourier Transform

(IFFT) are the more efficient implementations of the DFT, are utilized for the base band OFDM

modulation and demodulation process.

VHDL implementation of an optimized 8-point

FFT/IFFT processor in pipeline architecture for

OFDM systemsMounir Arioua, Said Belkouch, Mohamed AgdadEmbedded Systems and Digital Controls Laboratory,

Dept. of Electrical Engineering, ENSAM

Cadi Ayyad University

Marrakech, Morocco

[email protected], [email protected],

[email protected]

Moha Mrabet HassaniElectronic and Instrumentation Laboratory,
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Dept. of Physics, Faculty of Science Semlalia

Cadi Ayyad University

Marrakech, Morocco

[email protected] Fast Fourier Transform (FFT) and its inverse

transform (IFFT) processor are key components in many

communication systems. An optimized implementation of the 8-

point FFT processor with radix-2 algorithm in R2MDCarchitecture is presented in this paper. The butterfly- Processing

Element (PE) used in the 8-FFT processor reduces the

multiplicative complexity by using a real constant multiplication

in one method and eliminates the multiplicative complexity by

using add and shift operations in other proposed method. The

pipeline architecture R2MDC has been implemented with the 8-

point module and simulation results show that this module

significantly achieves a better performance with lower resource

usage.

Keywords- Cooley-Tukey, FF T/IF FT , OFDM , R2MDC,VHDL.

I. INTRODUCTION

The FFT/IFFT is one of the most commonly used digital

signal processing algorithm. Recently, FFT processor has been

widely used in digital signal processing field applied forcommunication systems. FFT/IFFT processors are key

components for an Orthogonal Frequency Division

Multiplexing (OFDM) based wireless broadband

communication system; it is one of the most complex and

intensive computation module of various wireless standards

PHY layer (OFDM-802.11a, MIMO-OFDM 802.11n) [1].

However, the main constraints nowadays for FFT processors

used in wireless communication systems are execution time

and lower power consumption [2]. The main issue in FFT/IFFT

processors is complex multiplication, which is the most

prominent arithmetic operation used in FFT/IFFT blocks. It is

an expensive operation and consumes a large chip area and

power especially when it comes to a large FFT point [3]. To

reduce the complexity of the multiplication, one of the two

proposed methods in this article replaces the expensive

complex multiplication with real and constant multiplications

[4]. The other method optimizes further the processing, by

wiping out the non-trivial complex multiplication with the

twiddle factors and fulfills the processing with no complex

multiplication.

We applied both methods to a simple 8-point FFT and we

compared them to the conventional FFT and to the R2MDC

processor in order to a comparative evaluation.

The paper is organized as follows: Section II discusses the

FFT algorithm implementation (Cooley-Tukey) and complex

multiplication used inside the butterfly-processing element.

Section III devoted for an architectural description of the FFTused module. Section IV shows the resulting implementation

and finally a conclusion is given in section V.

II. FFT ALGORITHM

In this section, a brief overview of IFFT and FFT

algorithms is provided to be effectively used in OFDM

applications.

The N-point discrete Fast Fourier Transform (DFT) is

defined as:


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1

0

[ ] [ ].N

nnk

NX k x n WWhereN

j nk nk

NW e

20 kN1X(k) is the k-th harmonic and x(n) is the n-th input sample.

Direct DFT calculation requires a computational complexity of

O(N2). By using The CooleyTukey FFT algorithm, the

complexity can be reduced to O (N.logrN) [2] [5].

A. The Cooley-Tukey FFT Algorithm

The Cooley-Tukey FFT is the most universal of all FFT

algorithms, because of any factorization of N is possible [5][6]. The most popular Cooley-Tukey FFTs are those were the

transform length is a power of a basis r, i.e., N = rS. These

algorithms are referred to as radix-r algorithms. The most

commonly used are those of basis r = 2 and r = 4.

For r = 2 and S stages, for instance, the following index

mapping of the The CooleyTukey algorithm gives:978-1-61284-732-0/11/$26.00 2010 IEEE

) . ( 1)

2

( ) ( 1) . (

). . a nd ( 1)

2

( ). ().

2

( ) ( ). ( ). ( ). (1

20.120

.120( )12012012

1202 2

2

nkNN

nkk kNN


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nkNnk

NNnnkNn kN

NnNnnkNN

NnnkNNn

nkN

x n x n N W

x n W x n N W W W

X k x n W x n W x n W x n N WN N

N

S S

n Sn Sn n n 2 1

2

1

2 1 2 ... 21 2 1

k2 1 k2 2 k... 2 k kSS

S

S

And: , ,.., , 0 ,1 1 2 1SSn n n n

, ,..., , 0 ,1 1 2 1k k k kS S

The CooleyTukey algorithm is based on a divide-andconquer

approach in the frequency domain and therefore is

referred to as decimation-in-frequency (DIF) FFT. The DFT


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formula is split into two summations:

X(k) can be decimated into even-and odd-indexed

frequency samples:

The computational procedure can be repeated through

decimation of the N/2-point DFTs X(2k) and DFTs X(2K+1).

The entire algorithm involves log2N stages, where each stage

involves N/2 operation units (butterflies). The computation of

the N point DFT via the decimation-in-frequency FFT, as in the

decimation-in-time algorithm requires (N/2).log2N complex

multiplication and N.log2N complex addition [5].

B. 8-point FFT Module

The flow graph of complete DIF decomposition of 8-point

DFT computation is represented in Fig. 1. The basic operation

in the signal flow graph is the butterfly operation; its a 2-point

DFT computation as shown in Fig. 2.Figure 1. 8-point decimation-in-frequency FFT algorithm.

Figure 2. Basic Butterfly computation.

Radix-2 butterfly processor consists of a complex adder and

complex subtraction. Beside that, an additional complex

multiplier for the twiddle factors WN is implemented. The

complex multiplication with the twiddle factor requires fourreal multiplications and two add/subtract operations [1] [3] [7].

C. Complex Multiplication

Since complex multiplication is an expensive operation, we

tend to reduce the multiplicative complexity of the twiddle

factor inside the butterfly processor by calculating only three

real multiplications and three add/subtract operations as in (5)

and (6).

The twiddle factor multiplication:

RjI (X jY ).(C jS) However the complex multiplication can be simplified:

R(C - S) .Y Z

I (C S) .X - Z (6)

With: Z C. (X - Y) (7)C and S are pre-computed and stored in a memory table.

Therefore it is necessary to store the following three

coefficients C, C + S, and C - S.

The implemented algorithm of complex multiplication used

in this work uses three multiplications, one addition and two

subtractions as shown in Fig. 3. This is done at the cost of an

additional third memory table which is given in (7). In the

hardware description language (VHDL) program,_the twiddle

factor multiplier was implemented using component

instantiations of three lpm-mult and three lpm-add-sub modules

from Altera library. Worth to note that lpm modules are

The Fast Fourier Transform (FFT) and its inverse transform (IFFT) processor are key components in manycommunication systems. An optimized implementation of the 8-point FFT processor with radix-2

algorithm in R2MDC architecture is presented in this paper. The butterfly - Processing Element (PE) used

in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in

one method and eliminates the multiplicative complexity by using add and shift operations in other

proposed method. The pipeline architecture R2MDC has been implemented with the 8-point module


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and simulation results show that this module significantly achieves a better performance with lower

resource usage.

In many applications high-speed performance is required. For this purpose, conventional multi-carrier

techniques are usually chosen, but this results in the lowering of spectrum efficiency. So, the principles

of orthogonal frequency division multiplexing are used in such applications. This paper gives the detailsof the development of IFFT & FFT algorithms to be used in OFDM systems based on the IEEE 802.11a

standard for WLAN. This system consists of separate OFDM transmitter & receiver. Actually, in the

entire architecture of OFDM system, all the mathematical manipulations take place in these two blocks

only, i.e. IFFT & FFT blocks while rest of the blocks convert the data from one format to another format.

In this paper we have implemented FFT and IFFT blocks in VHDL. The speed enhancement is the key

contribution of the main processing blocks in OFDM system.

IMPLEMENTATION OF FFT AND IFFTALGORITHMS IN FPGAIlgaz Az1 Suhap Sahin2 Cihan Karakuzu3 Mehmet Ali avuslu41,3,4 Departmant of Electronic and Communication Engineering,Kocaeli University41040,_zmit,Kocaeli2Department of Computer Engineering, Kocaeli University41040,_zmit,Kocaeli1e-mail : [email protected] 2e-mail : [email protected] : [email protected] 4e-mail : [email protected]

ABSTRACT:This article explains implementing of Fast Fourier(FFT) and Inverse Fast Fourier Transformalgorithms(IFFT) in FPGA. The reason of designingthe study on FPGA base is that FPGAs are able torearrange of logical blocks and moreover,mathematical algorithms can confirm faster by meansof parallel data processing. For operating thesealgorithms, it is used the family of Xilinx Virtex2Pxc2vp30fg676-7 FPGA device as a hardware. Inprogramming the hardware and writing codes, VHDLis used. The results show that FFT and IFFTalgorithms result in 0.6 s and 0.72 s cycle time respectively.

Keywords:FFT and IFFT, FPGA, VHDLI. INTRODUCTIONFast Fourier Transform (FFT) , using pattern

dilution in time and frequency to take patterns

from a signal is that a mathematical operations

which allow to calculate Discrete Fourier

Transform (DFT ) quickly.

Inverse Fast Fourier Transform (IFFT), an array

which is obtained its results in time and frequency

domain allows us to obtain datas which are takenby pattern dilution in time and frequency method.

Owing to this conversion, it was passed from

results to first datas. Because of this algorithms, the

patterns which are taken in time or frequency

domain, are converted to time and frequncy

domain.

The first knowing FFT algorithm was suggested

by Gauss in 1805, but the algorithm which is

invented by James Cooley &John Tuckey is


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become the common knowing one [1] and this

algorithm made it possible to live enormous

developments in DSP field. Because, in directly

calculating of DFT , calculation load which is

directly proportional with square of patterns

number (N) reduced to proportional level with

N*logN by means of FFT that based on the

principle of pattern dilution in time. By reducingthis mathematical load , it allows to process real

time implementations such an algorithm that is

wanted to implement as hardware [2].

Designers always effort to provide the balance

between speed and generality. As multipurpose

chips that can realize multiple function but

raltively slow , can be produced, it can be

producted special purpose chips which can realize

a few functions but very speed. A new kind of

processor can provide us the speed and also

functionality together . The most inportant feature

of FPGAs chips which base on reconfigurable and

parrallel data processing , is their unattainable

speed level that they rised. Because FPGA hasconfigurable logic blocks which act as logic

gates.(Figure 1). Logic blocks , at first can be

configured to realize A function then this blocks

can be reconfigured to realize B function and for

another C function this chip can be reconfigured

later because of their programmable devices. [3]

In this study , FFT and IFFT algorithms are

provided to implement as hardware thus it is

composed an alternative source for using this

algorithms in field of speed and applicable subjects

(DSP, OFDM). In addition, because of using FFT

and IFFT algorithms in WiMAX technology. It is

aimed at combine this technology and FPGA

processor under the same field.II. TEOR_CAL INFORMATIONSFFT and IFFT

VHDL implementation of FFT/IFFT Blocksfor OFDMPawan VermaVLSI-ES Division,

Centre for development

of Advanced computing

(CDAC),Mohali

Harpreet KaurVLSI-ES Division,



(CDAC),Mohali

Mandeep singhDEC Division,



(CDAC),Mohali


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Balwinder SinghVLSI-ES Division,



(CDAC),Mohali

balwinder_cdacmohali

@yahoo.com

AbstractIn many applications high-speed performance isrequired. For this purpose, conventional multi-carrier techniquesare usually chosen, but this results in the lowering of spectrumefficiency. So, the principles of Orthogonal Frequency DivisionMultiplexing are used in such applications. This paper gives thedetails of the development of IFFT & FFT algorithms to be usedin OFDM systems based on the IEEE 802.11a standard forWLAN. This system consists of separate OFDM transmitter &receiver. Actually, in the entire architecture of OFDM system, allthe mathematical manipulations take place in these two blocksonly, i.e. IFFT & FFT blocks while rest of the blocks convert thedata from one format to another format. In this paper we haveimplemented FFT and IFFT blocks in VHDL. The speedenhancement is the key contribution of the main processingblocks in OFDM system.

KeywordsFFT, IFFT, OFDM VHDL Simulati onI. INTRODUCTION

Orthogonal Frequency Division Multiplexing (OFDM) has

recently become a key modulation technique for both

broadband wireless and wire-line applications [1], [2]. It has

been adopted for digital audio broadcasting (DAB) and digital

terrestrial television broadcasting (DVB) [3]. OFDM has also

been advocated for digital subscriber loop (DSL) and wireless

local area network (WLAN) applications [1],[ 4]. OFDM, also

known as multicarrier modulation (MCM), incorporates a large

number of orthogonally selected carriers to transmit a highdata-

rate stream in a parallel form in the frequency domain.

The problem of intersymbol- interference (ISI) introduced by a

multipath channel (this limits the bit rate of a conventional

single carrier system), is significantly reduced in OFDM owingto the parallel, i.e. relatively low rate, data transmission

through multiple carriers. Also, the orthogonal nature of the

sub carriers in OFDM allows the sub carrier spectra to be

densely packed in the frequency domain resulting in a high

spectral efficiency. Spectral efficiency and multipath immunity

are two major features of OFDM.

A major drawback of OFDM is its relatively high

sensitivity to frequency and time synchronisation error,

compared to a single carrier system [5], [6]. Frequency

synchronisation error is caused by misalignment in subcarrier

frequencies owing to fluctuations in transmit receive RF

oscillators or channel Doppler frequency. This frequency offset

can destroy the subcarrier orthogonality introducing intercarrier-

interference (ICI). The time synchronization errorrefers to the incorrect timing of OFDM blocks at the receiver

introducing possible inter-block interference (IBI). Both ICI

and IBI degrade the bit-error rate (BER) performance of

OFDM systems [7]. The conventional OFDM uses a cyclicprefix

(CP) as a guard interval between OFDM blocks. The CP

basically absorbs the channel delay-spread and any block

timing error at the receiver avoiding IBI and ICI. Also, CPOFDM

provides easy per subcarrier equalisation in fading

channels


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II. THEORETICAL INFORMATION

In this Section, a brief overview of IFFT and FFT

algorithms is provided to be efficiently used in OFDM

systems. Specific attention is given to the decimation in

frequency (DIF) algorithm, which has been used to calculate

the outputs of both. Generally, we can use decimation in time

(DIT) algorithm also for the calculation. It depends upon the

choice of the programmer whether to use DIT or DIF as per hisconvenience. FFT and IFFT algorithms are based on a specific

mathematical equations array. Certain data that are being

obtained from a signal are replaced in these equations to count

DFTs and owing to these equations; processes are counted very

fast than normal DFT equations.

A. Fast Fourier Transfo rmThe Fast Fourier Transform (FFT) and Inverse Fast Fourier

Transform (IFFT) are derived from the main function, which is

called Discrete Fourier Transform (DFT). In DFT, the

computation for N-points of the DFT will be calculated one by

one for each point. While for FFT/IFFT, the computation is

done simultaneously and this method saves quite a lot of time.

The equations for FFT/IFFT function can be derived from the

general DFT equation 1.2009 International Conference on Advances in Recent Technologies in Communication and Computing978-0-7695-3845-7/09 $25.00 2009 IEEEDOI 10.1109/ARTCom.2009.14018626.00 Authorized licensed use limited to: RMIT University. Downloaded on August 03,2010 at 09:08:28 UTC from IEEE Xplore. Restrictions apply

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