Design and Implementation of a WCDMA Uplink Baseband...
Transcript of Design and Implementation of a WCDMA Uplink Baseband...
Design and Implementation of a Design and Implementation of a WCDMA Uplink WCDMA Uplink BasebandBaseband Receiver ICReceiver IC
Hsi-Pin Ma (馬席彬)
Assistant ProfessorDepartment of Electrical Engineering
National Tsing Hua UniversityFeb. 12, 2004
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OutlineOutline
• Design Flow• Architecture Design• Simulation Channel Model• Functional Simulation Results• Circuit Design• Implementation and Measurements• Conclusions
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Design FlowDesign Flow
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Architecture DesignArchitecture Design
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Common Frame Structure in Uplink Common Frame Structure in Uplink Physical ChannelsPhysical Channels
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Transmitter Architecture and Transmitter Architecture and ConfigurationConfiguration
General Tx Architecture PRACH Transmission
PCPCH Transmission DPDCH & DPCCH Transmission
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Proposed Receiver ArchitectureProposed Receiver Architecture
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Receiver ConfigurationsReceiver Configurations
• (a) Preamble • (b) Message Part
& DPCH• (c) Disable
beamforming
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Criteria for Choosing Major System Criteria for Choosing Major System ParametersParameters
• Beamforming algorithm– Feasibility for IC implementation
• Matched filter– Fast acquisition for channel delay profile– Hardware efficiency– Area and power consumption
• Carrier Synchronization– Fast acquisition for frequency offset– Speed of convergence
• Timing Synchronization– Performance and Area
• RAKE combining algorithm– Performance
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Channel EstimatorChannel Estimator
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Carrier Synchronization Carrier Synchronization (1/2)(1/2)
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Carrier Synchronization Carrier Synchronization (2/2)(2/2)
• (a) Acquisition,• (b) Initial frequency
offset and phase shift calculation,
• (c) Tracking.
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RAKE CombiningRAKE Combining
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RAKE Combining ConceptRAKE Combining Concept
Finger 1Finger 2
Finger 3
Finger 4I
Q
Combined Signal
Q
I
Combining
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Phased Array AntennasPhased Array Antennas
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BasebandBaseband Complex Model for a Linear Complex Model for a Linear Equally Spaced ArrayEqually Spaced Array
DOA (θ,φ)
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BeamformingBeamforming ConceptConcept
CombiningAntenna 2
Antenna 3
Antenna 1
Antenna 4
I
Q
Combined Signal
Q
I
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BeamformerBeamformer/Beam Searcher/Beam Searcher
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Functional SimulationFunctional Simulation
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Simulation Channel ModelSimulation Channel Model
Scalar Channel Model
Vector Channel Model
Power Delay Profile
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Carrier Synchronization Carrier Synchronization (1/2)(1/2)
Preamble Symbols Phasor Difference
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Margin
Carrier Synchronization Carrier Synchronization (2/2)(2/2)
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RAKE CombinerRAKE Combiner
1st Path 2nd Path
Combined
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BeamformerBeamformer/Beam Searcher /Beam Searcher (1/3)(1/3)
2 users
11 users
Simulated Beam Pattern
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BeamformerBeamformer/Beam Searcher /Beam Searcher (2/3)(2/3)
w/o Beamformer w/ Beamformer
2 users
11 users
Matched Filter Output Under Beamformer Test
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BeamformerBeamformer/Beam Searcher /Beam Searcher (3/3)(3/3)
RAKE Combining Output
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Word Length DeterminationWord Length Determination
Input of matched filter
2
2
10log10σµ=SNR
∑=
=n
kkpI
n 1,0
1µ
∑=
−−
=n
kkpI
n 1
22,0
2
11 )( µσ
where
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System PerformanceSystem Performance
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Circuit DesignCircuit Design
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Channel EstimatorChannel Estimator
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Latch File StructureLatch File Structure
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Area ConsiderationArea Consideration
6T
22T
Latch
D-type flip flop
Synthesized Synthesized
CustomLayoutCustom
Layout
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Power Consumption ConsiderationPower Consumption Consideration
Conventional Correlation Method
Proposed Correlation Method
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Low Voltage Operation Consideration Low Voltage Operation Consideration (1/3)(1/3)
• Modified TSPC Ring Decoders– Lower power consumption– Fast response– Operate at low voltage
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Low Voltage Operation Consideration Low Voltage Operation Consideration (2/3)(2/3)
Faster response
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Low Voltage Operation Consideration Low Voltage Operation Consideration (3/3)(3/3)
Original TSPC split-output circuit Modified TSPC split-output circuit
Low Voltage Operation
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Carrier SynchronizationCarrier Synchronization
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RAKE CombinerRAKE Combiner
RAKE Combiner
Correlator
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Beam SearcherBeam Searcher
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BeamformerBeamformer & Phase De& Phase De--rotatorrotator
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Implementation and MeasurementImplementation and Measurement
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FloorplanFloorplan for the Receiverfor the Receiver
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Ratio of Each Building BlockRatio of Each Building BlockTransistor Count
Area
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Die PhotoDie Photo
Custom Layout
Synthesized (ROM)
Other : Automatic Placement & Routing
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Chip FeaturesChip Features
• Baseband processor for uplink W-CDMA receiving operating at 3.84 Mchip/s.
• Operation at 15.36 MHz sampling rate (four samples per chip) at a supply voltage of 2.15 V.
• Provision for both spatial diversity (beamforming) and path diversity (RAKE combiner).
• Low-power latch-file structure for the digital matched filter in the channel estimator.
• Low-complexity correlator-based beam searcher that supports real-time adaptive beamforming based on four-element antenna array.
• Special phase/frequency estimation hardware for fast carrier synchronization.
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Measurement EnvironmentMeasurement Environment
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Communication PerformanceCommunication Performance
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Power DissipationPower Dissipation
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ConclusionsConclusions
• Investigate major specifications for IMT-2000. • Design and implement a baseband receiver IC
conforming to 3GPP W-CDMA uplink transmission.• Improve the receiver performance with advanced
receiving technologies using low-complexity hardware.– RAKE combining– Beamformer
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Related PublicationsRelated Publications• Journal papers
– Hsi-Pin Ma, Ming-Luen Liou, and Tzi-Dar Chiueh, “A 123-mW Digital Beamforming Receiver for Third-Generation W-CDMA Uplink Communications,” accepted by IEEE Journal of Solid-State Circuits for publication.
– Yuan-Hao Huang, Hsi-Pin Ma, Ming-Luen Liou, and Tzi-Dar Chiueh, “An 1.1G MAC/s Sub-Word-Parallel Digital Signal Processor for Wireless Communication Applications,” accepted by IEEEJournal of Solid-State Circuits for publication.
– Hsi-Pin Ma, Steve Heng-Chen Hsu, and Tzi-Dar Chiueh, “Design and Implementation of an Uplink Baseband Receiver for Wideband CDMA Communications,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, No. 12, pp. 2813-2821, December 2002.
• Conference papers– Hsi-Pin Ma, and Tzi-Dar Chiueh, “Design and Implementation of an Uplink Baseband Receiver
IC for Wideband CDMA Communication Systems with Beamforming Capability,” 2002 VLSI Design/CAD Symposium, Taitung, August 12-15, 2002.
– Hsi-Pin Ma, Steve Hengchen Hsu, Tzi-Dar Chiueh, “Real-Time Baseband Signal Processing Module for Wideband CDMA Transceiver,” National Symposium on Telecommunications, December 2000.
– Hsi-Pin Ma, Steve Hengchen Hsu, and Tzi-Dar Chiueh, “An Uplink Baseband Receiver architecture and FPGA Implementation for W-CDMA Systems,” in the IEEE Proc. of the 6th Asia-Pacific Conference on Communications, Seoul, Korea, November 2000, pp. 774-778.
– T. D. Chiueh, H. P. Ma, and H. C. Hsu, “An Uplink Transceiver Architecture for Wideband CDMA Systems,” in Proc. 1999 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS’99), Phuket, Thailand, December 1999, pp. 577-580.
– 經濟部第三代通訊系統核心技術與WB-WCDMA/WLL系統發展研討會,民國八十八年四月